Reference circuitry

Circuit configuration number 1 for QIAA aQFN™73, showing the schematic and the bill of materials.

Figure 1. Circuit configuration no. 1 schematic

Circuit configuration number 2 for QIAA aQFN™73, showing the schematic and the bill of materials.

Figure 2. Circuit configuration no. 2 schematic

Circuit configuration number 3 for QIAA aQFN™73, showing the schematic and the bill of materials.

Figure 3. Circuit configuration no. 3 schematic

Circuit configuration number 4 for QIAA aQFN™73, showing the schematic and the bill of materials.

Figure 4. Circuit configuration no. 4 schematic for QIAA aQFN™73

Circuit configuration number 5 for QIAA aQFN™73, showing the schematic and the bill of materials.

Figure 5. Circuit configuration no. 5 schematic

Circuit configuration number 6 for QIAA aQFN™73, showing the schematic and the bill of materials.

Figure 6. Circuit configuration no. 6 schematic

Circuit configuration number 7 for QIAA aQFN™73, showing the schematic and the bill of materials.

This circuit configuration includes a four-component RF match for improved harmonic suppression when using RADIO with TXPOWER ≥ 5 dBm.

Figure 7. Circuit configuration no. 7 schematic for QIAA aQFN™73

Circuit configuration number 1 for QFAA QFN48, showing the schematic and the bill of materials.

Figure 8. Circuit configuration no. 1 schematic

Circuit configuration number 1 for CKAA WLCSP, showing the schematic and the bill of materials.

Figure 9. Circuit configuration no. 1 schematic for CKAA WLCSP

Circuit configuration number 2 for CKAA WLCSP, showing the schematic and the bill of materials.

Figure 10. Circuit configuration no. 2 schematic for CKAA WLCSP

Circuit configuration number 3 for CKAA WLCSP, showing the schematic and the bill of materials.

Figure 11. Circuit configuration no. 3 schematic for CKAA WLCSP

Circuit configuration number 4 for CKAA WLCSP, showing the schematic and the bill of materials.

Figure 12. Circuit configuration no. 4 schematic for CKAA WLCSP

Circuit configuration number 5 for CKAA WLCSP, showing the schematic and the bill of materials.

Figure 13. Circuit configuration no. 5 schematic for CKAA WLCSP

Circuit configuration number 6 for CKAA WLCSP, showing the schematic and the bill of materials.

Figure 14. Circuit configuration no. 6 schematic for CKAA WLCSP

A well designed PCB is necessary to achieve good RF performance. Poor layout can lead to loss in performance or functionality.

A qualified RF layout for the IC and its surrounding components, including matching networks, can be downloaded from www.nordicsemi.com.

To ensure optimal performance it is essential that you follow the schematics and layout references closely. Especially in the case of the antenna matching circuitry (components between device pin ANT and the antenna), any changes to the layout can change the behavior, resulting in degradation of RF performance or a need to change component values. All reference circuits are designed for use with a 50 Ω single-ended antenna.

A PCB with a minimum of two layers, including a ground plane, is recommended for optimal RF performance. On PCBs with more than two layers, put a keep-out area on the inner layers directly below the antenna matching circuitry (components between device pin ANT and the antenna) to reduce the stray capacitances that influence RF performance.

A matching network is needed between the RF pin ANT and the antenna, to match the antenna impedance (normally 50 Ω) to the optimum RF load impedance for the chip. For optimum performance, the impedance for the matching network should be set as described in the recommended aQFN™73 package reference circuitry from Circuit configuration no. 1 for QIAA aQFN73, the recommended QFN48 reference circuitry from Circuit configuration no. 1 for QFAA QFN48, or the recommended WLCSP reference circuitry from Circuit configuration no. 1 for CKAA WLCSP depending on the package variant used in your design.

The DC supply voltage should be decoupled as close as possible to the VDD pins with high performance RF capacitors. See the schematics for recommended decoupling capacitor values. The supply voltage for the chip should be filtered and routed separately from the supply voltages of any digital circuitry.

Long power supply lines on the PCB should be avoided. All device grounds, VDD connections, and VDD bypass capacitors must be connected as close as possible to the IC. For a PCB with a topside RF ground plane, the VSS pins should be connected directly to the ground plane. For a PCB with a bottom ground plane, the best technique is to have via holes as close as possible to the VSS pads. A minimum of one via hole should be used for each VSS pin.

Fast switching digital signals should not be routed close to the crystal or the power supply lines. Capacitive loading of fast switching digital output lines should be minimized in order to avoid radio interference. Avoid routing the 32MHz crystal lines close to antenna line and antenna ground.

The PCB layout shown in the following figures is a reference layout for the aQFN™ package with internal LDO setup and VBUS supply.

For all available reference layouts, see the product page for the nRF52840 on www.nordicsemi.com.

Figure 15. Top silk layer

Figure 16. Top layer

Figure 17. Mid layer 1

Figure 18. Mid layer 2

Figure 19. Bottom layer