The programmable peripheral interconnect (PPI) enables peripherals to interact autonomously with each other using tasks and events independent of the CPU. The PPI allows precise synchronization between peripherals when real-time application constraints exist and eliminates the need for CPU activity to implement behavior which can be predefined using PPI.
The PPI system has, in addition to the fully programmable peripheral interconnections, a set of channels where the event end point (EEP) and task end points (TEP) are fixed in hardware. These fixed channels can be individually enabled, disabled, or added to PPI channel groups (see CHG[n] registers), in the same way as ordinary PPI channels.
Instance | Channel | Number of channels |
---|---|---|
PPI | 0-19 | 20 |
PPI (fixed) | 20-31 | 12 |
The PPI provides a mechanism to automatically trigger a task in one peripheral as a result of an event occurring in another peripheral. A task is connected to an event through a PPI channel. The PPI channel is composed of three end point registers, one EEP, and two TEPs. A peripheral task is connected to a TEP using the address of the task register associated with the task. Similarly, a peripheral event is connected to an EEP using the address of the event register associated with the event.
On each PPI channel, the signals are synchronized to the 16 MHz clock to avoid any internal violation of setup and hold timings. As a consequence, events that are synchronous to the 16 MHz clock will be delayed by one clock period, while other asynchronous events will be delayed by up to one 16 MHz clock period.
Each TEP implements a fork mechanism that enables a second task to be triggered at the same time as the task specified in the TEP is triggered. This second task is configured in the task end point register in the FORK registers groups, e.g. FORK.TEP[0] is associated with PPI channel CH[0].
There are two ways of enabling and disabling PPI channels:
PPI tasks (for example, CHG[0].EN) can be triggered through the PPI like any other task, which means they can be hooked to a PPI channel as a TEP. One event can trigger multiple tasks by using multiple channels and one task can be triggered by multiple events in the same way.
Some of the PPI channels are pre-programmed. These channels cannot be configured by the CPU, but can be added to groups and enabled and disabled like the general purpose PPI channels. The FORK TEP for these channels are still programmable and can be used by the application.
For a list of pre-programmed PPI channels, see the following table.
Channel | EEP | TEP |
---|---|---|
20 | TIMER0->EVENTS_COMPARE[0] | RADIO->TASKS_TXEN |
21 | TIMER0->EVENTS_COMPARE[0] | RADIO->TASKS_RXEN |
22 | TIMER0->EVENTS_COMPARE[1] | RADIO->TASKS_DISABLE |
23 | RADIO->EVENTS_BCMATCH | AAR->TASKS_START |
24 | RADIO->EVENTS_READY | CCM->TASKS_KSGEN |
25 | RADIO->EVENTS_ADDRESS | CCM->TASKS_CRYPT |
26 | RADIO->EVENTS_ADDRESS | TIMER0->TASKS_CAPTURE[1] |
27 | RADIO->EVENTS_END | TIMER0->TASKS_CAPTURE[2] |
28 | RTC0->EVENTS_COMPARE[0] | RADIO->TASKS_TXEN |
29 | RTC0->EVENTS_COMPARE[0] | RADIO->TASKS_RXEN |
30 | RTC0->EVENTS_COMPARE[0] | TIMER0->TASKS_CLEAR |
31 | RTC0->EVENTS_COMPARE[0] | TIMER0->TASKS_START |
Base address | Peripheral | Instance | Description | Configuration | |
---|---|---|---|---|---|
0x4001F000 | PPI | PPI |
Programmable peripheral interconnect |
Register | Offset | Description | |
---|---|---|---|
TASKS_CHG[0].EN | 0x000 |
Enable channel group 0 |
|
TASKS_CHG[0].DIS | 0x004 |
Disable channel group 0 |
|
TASKS_CHG[1].EN | 0x008 |
Enable channel group 1 |
|
TASKS_CHG[1].DIS | 0x00C |
Disable channel group 1 |
|
TASKS_CHG[2].EN | 0x010 |
Enable channel group 2 |
|
TASKS_CHG[2].DIS | 0x014 |
Disable channel group 2 |
|
TASKS_CHG[3].EN | 0x018 |
Enable channel group 3 |
|
TASKS_CHG[3].DIS | 0x01C |
Disable channel group 3 |
|
TASKS_CHG[4].EN | 0x020 |
Enable channel group 4 |
|
TASKS_CHG[4].DIS | 0x024 |
Disable channel group 4 |
|
TASKS_CHG[5].EN | 0x028 |
Enable channel group 5 |
|
TASKS_CHG[5].DIS | 0x02C |
Disable channel group 5 |
|
CHEN | 0x500 |
Channel enable register |
|
CHENSET | 0x504 |
Channel enable set register |
|
CHENCLR | 0x508 |
Channel enable clear register |
|
CH[0].EEP | 0x510 |
Channel 0 event endpoint |
|
CH[0].TEP | 0x514 |
Channel 0 task endpoint |
|
CH[1].EEP | 0x518 |
Channel 1 event endpoint |
|
CH[1].TEP | 0x51C |
Channel 1 task endpoint |
|
CH[2].EEP | 0x520 |
Channel 2 event endpoint |
|
CH[2].TEP | 0x524 |
Channel 2 task endpoint |
|
CH[3].EEP | 0x528 |
Channel 3 event endpoint |
|
CH[3].TEP | 0x52C |
Channel 3 task endpoint |
|
CH[4].EEP | 0x530 |
Channel 4 event endpoint |
|
CH[4].TEP | 0x534 |
Channel 4 task endpoint |
|
CH[5].EEP | 0x538 |
Channel 5 event endpoint |
|
CH[5].TEP | 0x53C |
Channel 5 task endpoint |
|
CH[6].EEP | 0x540 |
Channel 6 event endpoint |
|
CH[6].TEP | 0x544 |
Channel 6 task endpoint |
|
CH[7].EEP | 0x548 |
Channel 7 event endpoint |
|
CH[7].TEP | 0x54C |
Channel 7 task endpoint |
|
CH[8].EEP | 0x550 |
Channel 8 event endpoint |
|
CH[8].TEP | 0x554 |
Channel 8 task endpoint |
|
CH[9].EEP | 0x558 |
Channel 9 event endpoint |
|
CH[9].TEP | 0x55C |
Channel 9 task endpoint |
|
CH[10].EEP | 0x560 |
Channel 10 event endpoint |
|
CH[10].TEP | 0x564 |
Channel 10 task endpoint |
|
CH[11].EEP | 0x568 |
Channel 11 event endpoint |
|
CH[11].TEP | 0x56C |
Channel 11 task endpoint |
|
CH[12].EEP | 0x570 |
Channel 12 event endpoint |
|
CH[12].TEP | 0x574 |
Channel 12 task endpoint |
|
CH[13].EEP | 0x578 |
Channel 13 event endpoint |
|
CH[13].TEP | 0x57C |
Channel 13 task endpoint |
|
CH[14].EEP | 0x580 |
Channel 14 event endpoint |
|
CH[14].TEP | 0x584 |
Channel 14 task endpoint |
|
CH[15].EEP | 0x588 |
Channel 15 event endpoint |
|
CH[15].TEP | 0x58C |
Channel 15 task endpoint |
|
CH[16].EEP | 0x590 |
Channel 16 event endpoint |
|
CH[16].TEP | 0x594 |
Channel 16 task endpoint |
|
CH[17].EEP | 0x598 |
Channel 17 event endpoint |
|
CH[17].TEP | 0x59C |
Channel 17 task endpoint |
|
CH[18].EEP | 0x5A0 |
Channel 18 event endpoint |
|
CH[18].TEP | 0x5A4 |
Channel 18 task endpoint |
|
CH[19].EEP | 0x5A8 |
Channel 19 event endpoint |
|
CH[19].TEP | 0x5AC |
Channel 19 task endpoint |
|
CHG[0] | 0x800 |
Channel group 0 |
|
CHG[1] | 0x804 |
Channel group 1 |
|
CHG[2] | 0x808 |
Channel group 2 |
|
CHG[3] | 0x80C |
Channel group 3 |
|
CHG[4] | 0x810 |
Channel group 4 |
|
CHG[5] | 0x814 |
Channel group 5 |
|
FORK[0].TEP | 0x910 |
Channel 0 task endpoint |
|
FORK[1].TEP | 0x914 |
Channel 1 task endpoint |
|
FORK[2].TEP | 0x918 |
Channel 2 task endpoint |
|
FORK[3].TEP | 0x91C |
Channel 3 task endpoint |
|
FORK[4].TEP | 0x920 |
Channel 4 task endpoint |
|
FORK[5].TEP | 0x924 |
Channel 5 task endpoint |
|
FORK[6].TEP | 0x928 |
Channel 6 task endpoint |
|
FORK[7].TEP | 0x92C |
Channel 7 task endpoint |
|
FORK[8].TEP | 0x930 |
Channel 8 task endpoint |
|
FORK[9].TEP | 0x934 |
Channel 9 task endpoint |
|
FORK[10].TEP | 0x938 |
Channel 10 task endpoint |
|
FORK[11].TEP | 0x93C |
Channel 11 task endpoint |
|
FORK[12].TEP | 0x940 |
Channel 12 task endpoint |
|
FORK[13].TEP | 0x944 |
Channel 13 task endpoint |
|
FORK[14].TEP | 0x948 |
Channel 14 task endpoint |
|
FORK[15].TEP | 0x94C |
Channel 15 task endpoint |
|
FORK[16].TEP | 0x950 |
Channel 16 task endpoint |
|
FORK[17].TEP | 0x954 |
Channel 17 task endpoint |
|
FORK[18].TEP | 0x958 |
Channel 18 task endpoint |
|
FORK[19].TEP | 0x95C |
Channel 19 task endpoint |
|
FORK[20].TEP | 0x960 |
Channel 20 task endpoint |
|
FORK[21].TEP | 0x964 |
Channel 21 task endpoint |
|
FORK[22].TEP | 0x968 |
Channel 22 task endpoint |
|
FORK[23].TEP | 0x96C |
Channel 23 task endpoint |
|
FORK[24].TEP | 0x970 |
Channel 24 task endpoint |
|
FORK[25].TEP | 0x974 |
Channel 25 task endpoint |
|
FORK[26].TEP | 0x978 |
Channel 26 task endpoint |
|
FORK[27].TEP | 0x97C |
Channel 27 task endpoint |
|
FORK[28].TEP | 0x980 |
Channel 28 task endpoint |
|
FORK[29].TEP | 0x984 |
Channel 29 task endpoint |
|
FORK[30].TEP | 0x988 |
Channel 30 task endpoint |
|
FORK[31].TEP | 0x98C |
Channel 31 task endpoint |
Address offset: 0x000 + (n × 0x8)
Enable channel group n
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID | A | ||||||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | Access | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | W |
EN |
Enable channel group n |
||||||||||||||||||||||||||||||||
Trigger |
1 |
Trigger task |
Address offset: 0x004 + (n × 0x8)
Disable channel group n
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID | A | ||||||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | Access | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | W |
DIS |
Disable channel group n |
||||||||||||||||||||||||||||||||
Trigger |
1 |
Trigger task |
Address offset: 0x500
Channel enable register
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID | f | e | d | c | b | a | Z | Y | X | W | V | U | T | S | R | Q | P | O | N | M | L | K | J | I | H | G | F | E | D | C | B | A | |||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | Access | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A-T | RW |
CH[i] (i=0..19) |
Enable or disable channel i |
||||||||||||||||||||||||||||||||
Disabled |
0 |
Disable channel |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Enable channel |
|||||||||||||||||||||||||||||||||
U-f | RW |
CH[i] (i=20..31) |
Enable or disable channel i |
||||||||||||||||||||||||||||||||
Disabled |
0 |
Disable channel |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Enable channel |
Address offset: 0x504
Channel enable set register
Read: reads value of CH{i} field in CHEN register.
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID | f | e | d | c | b | a | Z | Y | X | W | V | U | T | S | R | Q | P | O | N | M | L | K | J | I | H | G | F | E | D | C | B | A | |||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | Access | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A-T | RW |
CH[i] (i=0..19) |
Channel i enable set register. Writing '0' has no effect. |
||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: channel disabled |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Read: channel enabled |
|||||||||||||||||||||||||||||||||
Set |
1 |
Write: Enable channel |
|||||||||||||||||||||||||||||||||
U-f | RW |
CH[i] (i=20..31) |
Channel i enable set register. Writing '0' has no effect. |
||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: channel disabled |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Read: channel enabled |
|||||||||||||||||||||||||||||||||
Set |
1 |
Write: Enable channel |
Address offset: 0x508
Channel enable clear register
Read: reads value of CH{i} field in CHEN register.
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID | f | e | d | c | b | a | Z | Y | X | W | V | U | T | S | R | Q | P | O | N | M | L | K | J | I | H | G | F | E | D | C | B | A | |||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | Access | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A-T | RW |
CH[i] (i=0..19) |
Channel i enable clear register. Writing '0' has no effect. |
||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: channel disabled |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Read: channel enabled |
|||||||||||||||||||||||||||||||||
Clear |
1 |
Write: disable channel |
|||||||||||||||||||||||||||||||||
U-f | RW |
CH[i] (i=20..31) |
Channel i enable clear register. Writing '0' has no effect. |
||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: channel disabled |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Read: channel enabled |
|||||||||||||||||||||||||||||||||
Clear |
1 |
Write: disable channel |
Address offset: 0x510 + (n × 0x8)
Channel n event endpoint
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | |||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | Access | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
EEP |
Pointer to event register. Accepts only addresses to registers from the Event group. |
Address offset: 0x514 + (n × 0x8)
Channel n task endpoint
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | |||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | Access | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
TEP |
Pointer to task register. Accepts only addresses to registers from the Task group. |
Address offset: 0x800 + (n × 0x4)
Channel group n
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID | f | e | d | c | b | a | Z | Y | X | W | V | U | T | S | R | Q | P | O | N | M | L | K | J | I | H | G | F | E | D | C | B | A | |||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | Access | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A-T | RW |
CH[i] (i=0..19) |
Include or exclude channel i |
||||||||||||||||||||||||||||||||
Excluded |
0 |
Exclude |
|||||||||||||||||||||||||||||||||
Included |
1 |
Include |
|||||||||||||||||||||||||||||||||
U-f | RW |
CH[i] (i=20..31) |
Include or exclude channel i |
||||||||||||||||||||||||||||||||
Excluded |
0 |
Exclude |
|||||||||||||||||||||||||||||||||
Included |
1 |
Include |
Address offset: 0x910 + (n × 0x4)
Channel n task endpoint
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | |||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | Access | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
TEP |
Pointer to task register |