AHB multilayer enables parallel access paths between multiple masters and slaves in a system. Access is resolved using priorities.
Each bus master is connected to all the slave devices using an interconnection matrix. The bus masters are assigned priorities, which are used to resolve access when two (or more) bus masters request access to the same slave device. When that occurs, the following rules apply:
Some peripherals, such as RADIO, do not have a safe stalling mechanism (no internal data buffering, or opportunity to pause incoming data). Being a low priority bus master might cause loss of data for such peripherals upon bus contention. To avoid AHB bus contention when using multiple bus masters, follow these guidelines:
Bus master name | Description |
---|---|
CPU | |
CTRL-AP | |
USB | |
CRYPTOCELL | |
SPIM1/SPIS1/TWIM1/TWIS1 | Same priority and mutually exclusive |
RADIO | |
CCM/ECB/AAR | Same priority and mutually exclusive |
SAADC | |
UARTE0 | |
SPIM0/SPIS0/TWIM0/TWIS0 | Same priority and mutually exclusive |
SPIM2/SPIS2 | Same priority and mutually exclusive |
NFCT | |
I2S | |
PDM | |
PWM0 | |
PWM1 | |
PWM2 | |
QSPI | |
PWM3 | |
UARTE1 | |
SPIM3 |
Defined bus masters are the CPU and peripherals with implemented EasyDMA. The available slaves are RAM AHB slaves. How the bus masters and slaves are connected using the interconnection matrix is illustrated in Memory.