Pin assignments

The pin assignment figures and tables describe the pinouts for the product variants of the chip.

The nRF52833 device provides flexibility regarding GPIO pin routing and configuration. However, some pins have limitations or recommendations for pin configurations and uses.

aQFN™73 ball assignments

The ball assignment figure and table in the following section describe the assignments for this variant of the chip.

Figure 1. aQFN™73 ball assignments, top view
aQFN73 ball assignments

Table 1. aQFN™73 ball assignments
Pin Name Function Description Recommended usage
A8

P0.31

AIN7

Digital I/O

Analog input

General purpose I/O

Analog input

 Standard drive, low frequency I/O only
A10

P0.29

AIN5

Digital I/O

Analog input

General purpose I/O

Analog input

 Standard drive, low frequency I/O only
A12

P0.02

AIN0

Digital I/O

Analog input

General purpose I/O

Analog input

 Standard drive, low frequency I/O only
A14 P0.19 Digital I/O General purpose I/O Standard drive, low frequency I/O only
A16 P1.05 Digital I/O General purpose I/O Standard drive, low frequency I/O only
A18 N.C.      
A20 P0.25 Digital I/O General purpose I/O Standard drive, low frequency I/O only
A22 VDD Power Power supply  
A23 XC2 Analog input Connection for 32 MHz crystal  
B1 VDD Power Power supply  
B3 DCC Power DC/DC converter output  
B5 DEC4 Power 1.3 V regulator supply decoupling Must be connected to DEC6 (pin E24)
B7 VSS Power Ground  
B9

P0.30

AIN6

Digital I/O

Analog input

General purpose I/O

Analog input

 Standard drive, low frequency I/O only
B11

P0.28

AIN4

Digital I/O

Analog input

General purpose I/O

Analog input

 Standard drive, low frequency I/O only
B13

P0.03

AIN1

Digital I/O

Analog input

General purpose I/O

Analog input

 Standard drive, low frequency I/O only
B15 P1.03 Digital I/O General purpose I/O Standard drive, low frequency I/O only
B17 P0.23 Digital I/O General purpose I/O Standard drive, low frequency I/O only
B19 N.C.      
B24 XC1 Analog input Connection for 32 MHz crystal  
C1 DEC1 Power 1.1 V regulator supply decoupling  
D2

P0.00

XL1

Digital I/O

Analog input

General purpose I/O

Connection for 32.768 kHz crystal

  
D23 DEC3 Power Power supply, decoupling  
E24 DEC6 Power 1.3 V regulator supply decoupling Must be connected to DEC4 (pin B5)
F2

P0.01

XL2

Digital I/O

Analog input

General purpose I/O

Connection for 32.768 kHz crystal

  
F23 VSS_PA Power Ground (radio supply)  
G1 P0.26 Digital I/O General purpose I/O  
H2 P0.27 Digital I/O General purpose I/O  
H23 ANT RF Single-ended radio antenna connection See Reference circuitry for guidelines on how to ensure good RF performance
J1

P0.04

AIN2

Digital I/O

Analog input

General purpose I/O

Analog input

  
J24

P0.10

NFC2

Digital I/O

NFC input

General purpose I/O

NFC antenna connection

 Standard drive, low frequency I/O only
K2

P0.05

AIN3

Digital I/O

Analog input

General purpose I/O

Analog input

  
L1 P0.06 Digital I/O General purpose I/O  
L24

P0.09

NFC1

Digital I/O

NFC input

General purpose I/O

NFC antenna connection

 Standard drive, low frequency I/O only
M2

P0.07

TRACECLK

Digital I/O

Trace clock

General purpose I/O

Trace buffer clock

  
N1 P0.08 Digital I/O General purpose I/O  
N24

DEC5

Not connected

 Power

1.3 V regulator supply decoupling for build codes Axx and earlier.

Not connected for build codes Bxx and later.

 
P2 P1.08 Digital I/O General purpose I/O  
P23 P1.07 Digital I/O General purpose I/O Standard drive, low frequency I/O only
R1

P1.09

TRACEDATA3

Digital I/O

Trace data

General purpose I/O

Trace buffer TRACEDATA[3]

  
R24 P1.06 Digital I/O General purpose I/O Standard drive, low frequency I/O only
T2

P0.11

TRACEDATA2

Digital I/O

Trace data

General purpose I/O

Trace buffer TRACEDATA[2]

  
T23 N.C.      
U1

P0.12

TRACEDATA1

Digital I/O

Trace data

General purpose I/O

Trace buffer TRACEDATA[1]

  
U24 P1.04 Digital I/O General purpose I/O Standard drive, low frequency I/O only
V23 N.C.      
W1 VDD Power Power supply  
W24 P1.02 Digital I/O General purpose I/O Standard drive, low frequency I/O only
Y2 VDDH Power High voltage power supply  
Y23 P1.01 Digital I/O General purpose I/O Standard drive, low frequency I/O only
AA24 SWDCLK Debug Serial wire debug clock input for debug and programming  
AB2 N.C.      
AC5 DECUSB Power USB 3.3 V regulator supply decoupling  
AC9 P0.14 Digital I/O General purpose I/O  
AC11 P0.16 Digital I/O General purpose I/O  
AC13

P0.18

nRESET

 Digital I/O

General purpose I/O

Configurable as pin RESET

  
AC15 N.C.      
AC17 P0.21 Digital I/O General purpose I/O  
AC19 N.C.      
AC21 N.C.      
AC24 SWDIO Debug Serial wire debug I/O for debug and programming  
AD2 VBUS Power 5 V input for USB 3.3 V regulator  
AD4 D- USB USB D-  
AD6 D+ USB USB D+  
AD8 P0.13 Digital I/O General purpose I/O  
AD10 P0.15 Digital I/O General purpose I/O  
AD12 P0.17 Digital I/O General purpose I/O  
AD14 VDD Power Power supply  
AD16 P0.20 Digital I/O General purpose I/O  
AD18 P0.22 Digital I/O General purpose I/O  
AD20 P0.24 Digital I/O General purpose I/O  
AD22

P1.00

TRACEDATA0

Digital I/O

Trace data

General purpose I/O

Trace buffer TRACEDATA[0]

Serial wire output (SWO)

  
AD23 VDD Power Power supply  
Die pad VSS Power Ground pad Exposed die pad must be connected to ground (VSS) for proper device operation
Note: For more information on standard drive, see GPIO — General purpose input/output. Low frequency I/O is a signal with a frequency up to 10 kHz.
Note: If SPIM0, SPIM1, or SPIM2 is used with 8 Mbps data rate, the recommended GPIOs for the clock signal (SCK) are P0.27, P1.08, P0.04, and P1.09.

QFN40 pin assignments

The pin assignment figure and table describe the assignments for this variant of the chip.

Figure 2. QFN40 pin assignments, top view

Table 2. QFN40 pin assignments
Pin Name Function Description Recommended usage
Left side of the chip
1 DEC1 Power 1.1 V Digital supply decoupling  
2

P0.00

XL1

Digital I/O

Analog input

General purpose I/O pin.

Connection for 32.768 kHz crystal

  
3

P0.01

XL2

Digital I/O

Analog input

General purpose I/O pin

Connection for 32.768 kHz crystal

  
4

P0.04

AIN2

Digital I/O

Analog input

General purpose I/O pin

Analog input

  
5

P0.05

AIN3

Digital I/O

Analog input

General purpose I/O pin

Analog input

  
6 P1.09 Digital I/O General purpose I/O pin  
7 P0.11 Digital I/O General purpose I/O pin  
8 VDD Power Power supply  
9 VDDH Power High voltage power supply  
10 VBUS Power 5 V input for USB 3.3 V regulator  
Bottom side of the chip
11 DECUSB Power USB 3.3 V regulator supply decoupling  
12 D- USB USB D-  
13 D+ USB USB D+  
14 P0.15 Digital I/O General purpose I/O  
15 P0.17 Digital I/O General purpose I/O  
16

P0.18

nRESET

 Digital I/O

General purpose I/O

Configurable as pin RESET

  
17 P0.20 Digital I/O General purpose I/O  
18 VDD Power Power supply  
19 SWDIO Debug Serial wire debug I/O for debug and programming  
20 SWDCLK Debug Serial wire debug clock input for debug and programming  
Right side of the chip
21

DEC5

Not connected

 Power

1.3 V regulator supply decoupling for build codes Axx and earlier.

Not connected for build codes Bxx and later.

 
22

P0.09

NFC1

Digital I/O

NFC input

General purpose I/O

NFC antenna connection

 Standard drive, low frequency I/O only
23

P0.10

NFC2

Digital I/O

NFC input

General purpose I/O

NFC antenna connection

 Standard drive, low frequency I/O only
24 ANT RF Single-ended radio antenna connection See Reference circuitry for guidelines on how to ensure good RF performance
25 VSS_PA Power Ground (radio supply)  
26 DEC6 Power 1.3 V regulator supply decoupling Must be connected to DEC4 (pin 38)
27 DEC3 Power Power supply, decoupling  
28 XC1 Analog input Connection for 32 MHz crystal  
29 XC2 Analog input Connection for 32 MHz crystal  
30 VDD Power Power supply  
Top side of the chip
31

P0.03

AIN1

Digital I/O

Analog input

General purpose I/O pin

Analog input

 Standard drive, low frequency I/O only
32

P0.02

AIN0

Digital I/O

Analog input

General purpose I/O pin

Analog input

 Standard drive, low frequency I/O only
33

P0.28

AIN4

Digital I/O

Analog input

General purpose I/O pin

Analog input

 Standard drive, low frequency I/O only
34

P0.29

AIN5

Digital I/O

Analog input

General purpose I/O pin

Analog input

 Standard drive, low frequency I/O only
35

P0.30

AIN6

Digital I/O

Analog input

General purpose I/O pin

Analog input

 Standard drive, low frequency I/O only
36

P0.31

AIN7

Digital I/O

Analog input

General purpose I/O pin

Analog input

  
37 VSS Power Ground  
38 DEC4 Power 1.3 V regulator supply decoupling Must be connected to DEC6 (pin 26)
39 DCC Power DC/DC converter output  
40 VDD Power Power supply  
Backside of the the chip
Die pad VSS Power Ground pad Exposed die pad must be connected to ground (VSS) for proper device operation
Note: For more information on standard drive, see GPIO — General purpose input/output. Low frequency I/O is a signal with a frequency up to 10 kHz.
Note: If SPIM0, SPIM1, or SPIM2 is used with 8 Mbps data rate, the recommended GPIOs for the clock signal (SCK) are P1.09, P0.04, and P0.31.

WLCSP ball assignments

The ball assignment figure and table describe the assignments for this variant of the chip.

Figure 3. WLCSP ball assignments, top view
WLCSP ball assignments

Table 3. WLCSP ball assignments
Pin Name Function Description Recommended usage
A1 XC1 Analog input Connection for 32 MHz crystal  
A2 XC2 Analog input Connection for 32 MHz crystal  
A3 P0.25 Digital I/O General purpose I/O Standard drive, low frequency I/O only
A4

P0.03

AIN1

Digital I/O

Analog input

General purpose I/O pin

Analog input

 Standard drive, low frequency I/O only
A5

P0.29

AIN5

Digital I/O

Analog input

General purpose I/O pin

Analog input

 Standard drive, low frequency I/O only
A6 DEC4 Power 1.3 V regulator supply decoupling Must be connected to DEC6 (ball C2)
A7 VSS Power Ground  
A8 DCC Power DC/DC converter output  
A9 VDD Power Power supply  
B3 VDD Power Power supply  
B4 P1.03 Digital I/O General purpose I/O Standard drive, low frequency I/O only
B5

P0.30

AIN6

Digital I/O

Analog input

General purpose I/O pin

Analog input

 Standard drive, low frequency I/O only
B6

P0.31

AIN7

Digital I/O

Analog input

General purpose I/O pin

Analog input

 Standard drive, low frequency I/O only
B7

P0.01

XL2

Digital I/O

Analog input

General purpose I/O pin

Connection for 32.768 kHz crystal

  
B8

P0.00

XL1

Digital I/O

Analog input

General purpose I/O pin.

Connection for 32.768 kHz crystal

  
B9 DEC1 Power 1.1 V Digital supply decoupling  
C1 VSS_PA Power Ground (radio supply)  
C2 DEC6 Power 1.3 V regulator supply decoupling Must be connected to DEC4 (ball A6)
C4 P1.05 Digital I/O General purpose I/O Standard drive, low frequency I/O only
C5 P0.19 Digital I/O General purpose I/O Standard drive, low frequency I/O only
C6

P0.02

AIN0

Digital I/O

Analog input

General purpose I/O pin

Analog input

 Standard drive, low frequency I/O only
C7

P0.28

AIN4

Digital I/O

Analog input

General purpose I/O pin

Analog input

 Standard drive, low frequency I/O only
C8 P0.27 Digital I/O General purpose I/O  
C9 P0.26 Digital I/O General purpose I/O  
D3 VSS Power Ground  
D4 VSS Power Ground  
D5 VSS Power Ground  
D6 VSS Power Ground  
D7 P0.23 Digital I/O General purpose I/O Standard drive, low frequency I/O only
D8

P0.04

AIN2

Digital I/O

Analog input

General purpose I/O pin

Analog input

  
D9

P0.05

AIN3

Digital I/O

Analog input

General purpose I/O pin

Analog input

  
E1 ANT RF Single-ended radio antenna connection See Reference circuitry for guidelines on how to ensure good RF performance
E2

P0.10

NFC2

Digital I/O

NFC input

General purpose I/O

NFC antenna connection

 Standard drive, low frequency I/O only
E3 P1.06 Digital I/O General purpose I/O Standard drive, low frequency I/O only
E4 VSS Power Ground  
E5 VSS Power Ground  
E6 VSS Power Ground  
E7 P0.08 Digital I/O General purpose I/O  
E8

P0.07

TRACECLK

Digital I/O

Trace clock

General purpose I/O

Trace buffer clock

  
E9 P0.06 Digital I/O General purpose I/O  
F1

DEC5

Not connected

 Power

1.3 V regulator supply decoupling for build codes Axx and earlier.

Not connected for build codes Bxx and later.

 
F2

P0.09

NFC1

Digital I/O

NFC input

General purpose I/O

NFC antenna connection

 Standard drive, low frequency I/O only
F3 P1.01 Digital I/O General purpose I/O Standard drive, low frequency I/O only
F4 VSS Power Ground  
F5 VSS Power Ground  
F6 VSS Power Ground  
F7 P0.13 Digital I/O General purpose I/O  
F8

P1.09

TRACEDATA3

Digital I/O

Trace data

General purpose I/O

Trace buffer TRACEDATA[3]

  
F9 P1.08 Digital I/O General purpose I/O  
G1 P1.07 Digital I/O General purpose I/O Standard drive, low frequency I/O only
G2 P1.04 Digital I/O General purpose I/O Standard drive, low frequency I/O only
G3 P0.24 Digital I/O General purpose I/O Standard drive, low frequency I/O only
G4 P0.21 Digital I/O General purpose I/O  
G5 P0.20 Digital I/O General purpose I/O  
G6 P0.16 Digital I/O General purpose I/O  
G8

P0.11

TRACEDATA2

Digital I/O

Trace data

General purpose I/O

Trace buffer TRACEDATA[2]

  
G9 VDD Power Power supply  
H1 P1.02 Digital I/O General purpose I/O Standard drive, low frequency I/O only
H2 SWDCLK Debug Serial wire debug clock input for debug and programming  
H3

P1.00

TRACEDATA0

Digital I/O

Trace data

General purpose I/O

Trace buffer TRACEDATA[0]

Serial wire output (SWO)

  
H4

P0.18

nRESET

 Digital I/O

General purpose I/O

Configurable as pin RESET

  
H5 P0.15 Digital I/O General purpose I/O  
H6

P0.12

TRACEDATA1

Digital I/O

Trace data

General purpose I/O

Trace buffer TRACEDATA[1]

  
H7 D- USB USB D-  
H8 VBUS Power 5 V input for USB 3.3 V regulator  
H9 VDDH Power High voltage power supply  
J1 VDD Power Power supply  
J2 SWDIO Debug Serial wire debug I/O for debug and programming  
J3 P0.22 Digital I/O General purpose I/O  
J4 VDD Power Power supply  
J5 P0.17 Digital I/O General purpose I/O  
J6 P0.14 Digital I/O General purpose I/O  
J7 D+ USB USB D+  
J8 DECUSB Power USB 3.3 V regulator supply decoupling  
J9 VSS Power Ground  
Note: For more information on standard drive, see GPIO — General purpose input/output. Low frequency I/O is a signal with a frequency up to 10 kHz.
Note: If SPIM0, SPIM1, or SPIM2 is used with 8 Mbps data rate, the recommended GPIOs for the clock signal (SCK) are P0.27, P1.08, P0.04, and P1.09.