The 2.4 GHz radio transceiver is compatible with multiple radio standards, such as 1 Mbps and 2 Mbps Bluetooth low energy, as well as Nordic's proprietary 1 Mbps and 2 Mbps modes of operation.
EasyDMA in combination with an automated packet assembler and packet disassembler, and an automated CRC generator and CRC checker, makes it very easy to configure and use the RADIO. See RADIO block diagram for details.
The RADIO includes a device address match unit and an interframe spacing control unit that can be utilized to simplify address white listing and interframe spacing respectively, in Bluetooth Smart and similar applications.
The RADIO also includes a received signal strength indicator (RSSI) and a bit counter. The bit counter generates events when a preconfigured number of bits have been sent or received by the RADIO.
The RADIO peripheral uses EasyDMA for reading of data packets from and writing to RAM, without CPU involvement.
As illustrated in RADIO block diagram, the RADIO's EasyDMA utilizes the same PACKETPTR for receiving and transmitting packets, and this pointer can only point to the Data RAM region. See Memory for more information about the different memoryregions.
The DISABLED event indicates that the EasyDMA has finished accessing the RAM.
The structure of a radio packet is described in detail in Packet configuration. The data that is stored in Data RAM and transported by EasyDMA consists of the following fields:
In addition, a static add-on is sent immediately after the payload.
The size of each of the above fields in the frame is configurable, and the space occupied in RAM depends on these settings. A size of zero is possible for any of the fields, it is up to the user to make sure that the resulting frame complies with the RF protocol chosen. For the field sizes defined in bits, the occupation in RAM will always be rounded up to the next full byte size (for instance 3 bit length will allocate 1 byte in RAM, 9 bit length will allocate 2 bytes, etc.).
The sizes of the fields S0, LENGTH and S1 can be individually configured by the S0LEN, LFLEN and S1LEN fields of the PCNF0 register respectively. The size of the payload is configured through the value in RAM corresponding to the LENGTH field. The size of the static add-on to the payload is configured through the STATLEN field in PCNF1 register.
The MAXLEN field in the PCNF1 register configures the maximum packet payload plus add-on size in number of bytes that can be transmitted or received by the RADIO. This feature can be used to ensure that the RADIO does not overwrite, or read beyond, the RAM assigned to the packet payload. This means that if the packet payload length defined by the PCNF1.STATLEN and the LENGTH field in the packet specify a packet larger than MAXLEN, the payload will be truncated at MAXLEN. The packet's LENGTH field will not be altered when the payload is truncated. The RADIO will calculate CRC as if the packet length is equal to MAXLEN.
RADIO packet contains the following fields: PREAMBLE, ADDRESS, S0, LENGTH, S1, PAYLOAD and CRC.
The content of a RADIO packet is illustrated in On-air packet layout. The RADIO sends the different fields in the packet in the order they are illustrated below, from left to right:
PREAMBLE is sent with least significant bit first on-air. The size of the PREAMBLE depends on the mode selected in the MODE register:
Not shown in the figure above is the static payload add-on (the length of which is defined in PCNF1.STATLEN, and which is 0 bytes long in a standard BLE packet). The static payload add-on is sent between the PAYLOAD and CRC fields.
The RADIO packets are stored in memory, inside instances of a radio packet data structure as illustrated in In-RAM representation of radio packet - S0, LENGTH and S1 are optional. The PREAMBLE, ADDRESS and CRC fields are omitted in this data structure.
The byte ordering on the air is always:
The bit endianness, i.e. the order in which the bits are sent and received, is configured in PCNF1.ENDIAN for the fields S0, LENGTH, S1 and PAYLOAD.
The sizes of the fields S0, LENGTH and S1 can be individually configured in the S0LEN, LFLEN and S1LEN fields of the PCNF0 register respectively. If any of these fields are configured to be less than 8 bit long, the least significant bits of the fields are used, as seen from the RAM representation.
If S0, LENGTH or S1 are specified with zero length, their fields will be omitted in memory. Otherwise each field will be represented as a separate byte, regardless of the number of bits in their on-air counterpart.
Independent of the configuration of MAXLEN, the combined length of S0, LENGTH, S1 and PAYLOAD cannot exceed 258 bytes.
The on-air radio ADDRESS field is composed of two parts, the base address field and the address prefix field.
The size of the base address field is configurable via BALEN in PCNF1. The base address is truncated from LSByte if the BALEN is less than 4. See Definition of logical addresses.
The on-air addresses are defined in the BASEn and PREFIXn registers, and it is only when writing these registers the user will have to relate to actual on-air addresses. For other radio address registers such as the TXADDRESS, RXADDRESSES and RXMATCH registers, logical radio addresses ranging from 0 to 7 are being used. The relationship between the on-air radio addresses and the logical addresses is described in Definition of logical addresses.
Logical address | Base address | Prefix byte |
---|---|---|
0 | BASE0 | PREFIX0.AP0 |
1 | BASE1 | PREFIX0.AP1 |
2 | BASE1 | PREFIX0.AP2 |
3 | BASE1 | PREFIX0.AP3 |
4 | BASE1 | PREFIX1.AP4 |
5 | BASE1 | PREFIX1.AP5 |
6 | BASE1 | PREFIX1.AP6 |
7 | BASE1 | PREFIX1.AP7 |
The RADIO is able to do packet whitening and de-whitening.
See WHITEEN in PCNF1 register for how to enable whitening. When enabled, whitening and de-whitening will be handled by the RADIO automatically as packets are sent and received.
The whitening word is generated using polynomial g(D) = D7+ D4 + 1, which then is XORed with the data packet that is to be whitened, or de-whitened. See the figure below.
Whitening and de-whitening will be performed over the whole packet (except for the preamble and the address field).
The linear feedback shift register, illustrated in Data whitening and de-whitening can be initialised via the DATAWHITEIV register.
The CRC generator in the RADIO calculates the CRC over the whole packet excluding the preamble. If desirable, the address field can be excluded from the CRC calculation as well
See CRCCNF register for more information.
The CRC polynomial is configurable as illustrated in CRC generation of an n bit CRC where bit 0 in the CRCPOLY register corresponds to X0 and bit 1 corresponds to X1 etc. See CRCPOLY for more information.
As illustrated in CRC generation of an n bit CRC, the CRC is calculated by feeding the packet serially through the CRC generator. Before the packet is clocked through the CRC generator, the CRC generator's latches b0 through bn will be initialized with a predefined value specified in the CRCINIT register. When the whole packet is clocked through the CRC generator, latches b0 through bn will hold the resulting CRC. This value will be used by the RADIO during both transmission and reception but it is not available to be read by the CPU at any time. A received CRC can however be read by the CPU via the RXCRC register independent of whether or not it has passed the CRC check.
The length (n) of the CRC is configurable, see CRCCNF for more information.
After the whole packet including the CRC has been received, the RADIO will generate a CRCOK event if no CRC errors were detected, or alternatively generate a CRCERROR event if CRC errors were detected.
The status of the CRC check can be read from the CRCSTATUS register after a packet has been received.
The RADIO can enter a number of states.
The RADIO can enter the states described the table below. An overview state diagram for the RADIO is illustrated in Radio states. This figure shows how the tasks and events relate to the RADIO's operation. The RADIO does not prevent a task from being triggered from the wrong state. If a task is triggered from the wrong state, for example if the RXEN task is triggered from the RXDISABLE state, this may lead to incorrect behaviour. As illustrated in Radio states, the PAYLOAD event is always generated even if the payload is zero.
State | Description |
---|---|
DISABLED | No operations are going on inside the radio and the power consumption is at a minimum |
RXRU | The radio is ramping up and preparing for reception |
RXIDLE | The radio is ready for reception to start |
RX | Reception has been started and the addresses enabled in the RXADDRESSES register are being monitored |
TXRU | The radio is ramping up and preparing for transmission |
TXIDLE | The radio is ready for transmission to start |
TX | The radio is transmitting a packet |
RXDISABLE | The radio is disabling the receiver |
TXDISABLE | The radio is disabling the transmitter |
Before the RADIO is able to transmit a packet, it must first ramp-up in TX mode.
See TXRU in Radio states and Transmit sequence. A TXRU ramp-up sequence is initiated when the TXEN task is triggered. After the radio has successfully ramped up it will generate the READY event indicating that a packet transmission can be initiate. A packet transmission is initiated by triggering the START task. As illustrated in Radio states the START task can first be triggered after the RADIO has entered into the TXIDLE state.
Transmit sequence illustrates a single packet transmission where the CPU manually triggers the different tasks needed to control the flow of the RADIO, i.e. no shortcuts are used. If shortcuts are not used, a certain amount of delay caused by CPU execution is expected between READY and START, and between END and DISABLE. As illustrated in Transmit sequence the RADIO will by default transmit '1's between READY and START, and between END and DISABLED. What is transmitted can be programmed through the DTX field in the MODECNF0 register.
A slightly modified version of the transmit sequence from Transmit sequence is illustrated in Transmit sequence using shortcuts to avoid delays where the RADIO is configured to use shortcuts between READY and START, and between END and DISABLE, which means that no delay is introduced.
The RADIO is able to send multiple packets one after the other without having to disable and re-enable the RADIO between packets, this is illustrated in Transmission of multiple packets .
Before the RADIO is able to receive a packet, it must first ramp up in RX mode
See RXRU in Radio states and Receive sequence. An RXRU ramp-up sequence is initiated when the RXEN task is triggered. After the radio has successfully ramped up it will generate the READY event indicating that a packet reception can be initiated. A packet reception is initiated by triggering the START task. As illustrated in Radio states the START task can, first be triggered after the RADIO has entered into the RXIDLE state.
Receive sequence illustrates a single packet reception where the CPU manually triggers the different tasks needed to control the flow of the RADIO, i.e. no shortcuts are used. If shortcuts are not used, a certain amount of delay, caused by CPU execution, is expected between READY and START, and between END and DISABLE. As illustrated Receive sequence the RADIO will be listening and possibly receiving undefined data, illustrated with an 'X', from START and until a packet with valid preamble (P) is received.
A slightly modified version of the receive sequence from Receive sequence is illustrated in Receive sequence using shortcuts to avoid delays where the the RADIO is configured to use shortcuts between READY and START, and between END and DISABLE, which means that no delay is introduced.
The RADIO is able to receive multiple packets one after the other without having to disable and re-enable the RADIO between packets, this is illustrated Reception of multiple packets.
The RADIO implements a mechanism for measuring the power in the received signal. This feature is called received signal strength indicator (RSSI).
The RSSI is measured continuously and the value filtered using a single-pole IIR filter. After a signal level change, the RSSI will settle after approximately RSSISETTLE.
Sampling of the received signal strength is started by using the RSSISTART task. The sample can be read from the RSSISAMPLE register.
The sample period of the RSSI is defined by RSSIPERIOD. The RSSISAMPLE will hold the filtered received signal strength after this sample period.
For the RSSI sample to be valid, the RADIO has to be enabled in receive mode (RXEN task) and the reception has to be started (READY event followed by START task).
Interframe spacing is the time interval between two consecutive packets.
It is defined as the time (in microseconds) from the end of the last bit of the previous packet received and to the start of the first bit of the subsequent packet that is transmitted. The radio is able to enforce this interval as specified in the TIFS register as long as TIFS is not specified to be shorter than the radio’s turn-around time, i.e. the time needed to switch off the receiver, and switch back on the transmitter.
TIFS is only enforced if END_DISABLE and DISABLED_TXEN or END_DISABLE and DISABLED_RXEN shortcuts are enabled. TIFS is only qualified for use in BLE_1MBIT mode, and default ramp-up mode. The use of shortcuts and timing is illustrated in Ramp up and TIFS Timing Details.
The device address match feature is tailored for address white listing in a Bluetooth Smart and similar implementations.
This feature enables on-the-fly device address matching while receiving a packet on air. This feature only works in receive mode and as long as the radio is configured for little endian, see PCNF1.ENDIAN.
The device address match unit assumes that the 48 first bits of the payload is the device address and that bit number 6 in S0 is the TxAdd bit. See the Bluetooth Core Specification for more information about device addresses, TxAdd and whitelisting.
The radio is able to listen for eight different device addresses at the same time. These addresses are specified in a DAB/DAP register pair, one pair per address, in addition to a TxAdd bit configured in the DACNF register. The DAB register specifies the 32 least significant bits of the device address, while the DAP register specifies the 16 most significant bits of the device address.
Each of the device addresses can be individually included or excluded from the matching mechanism. This is configured in the DACNF register.
Radio implements a simple counter that can be configured to generate an event after a specific number of bits have been transmitted or received.
By using shortcuts, this counter can be started from different events generated by the radio and hence count relative to these.
The bit counter is started by triggering the BCSTART task, and stopped by triggering the BCSTOP task. A BCMATCH event will be generated when the bit counter has counted the number of bits specified in the BCC register. The bit counter will continue to count bits until the DISABLED event is generated or until the BCSTOP task is triggered. The CPU can therefore, after a BCMATCH event, reconfigure the BCC value for new BCMATCH events within the same packet.
The bit counter can only be started after the radio has received the ADDRESS event.
The bit counter will stop and reset on BCSTOP, STOP, END and DISABLE tasks.
The figure below illustrates how the bit counter can be used to generate a BCMATCH event in the beginning of the packet payload, and again generate a second BCMATCH event after sending 2 bytes (16 bits) of the payload.
Base address | Peripheral | Instance | Description | Configuration | |
---|---|---|---|---|---|
0x40001000 | RADIO | RADIO |
2.4 GHz radio |
Register | Offset | Description | |
---|---|---|---|
TASKS_TXEN | 0x000 |
Enable RADIO in TX mode |
|
TASKS_RXEN | 0x004 |
Enable RADIO in RX mode |
|
TASKS_START | 0x008 |
Start RADIO |
|
TASKS_STOP | 0x00C |
Stop RADIO |
|
TASKS_DISABLE | 0x010 |
Disable RADIO |
|
TASKS_RSSISTART | 0x014 |
Start the RSSI and take one single sample of the receive signal strength. |
|
TASKS_RSSISTOP | 0x018 |
Stop the RSSI measurement |
|
TASKS_BCSTART | 0x01C |
Start the bit counter |
|
TASKS_BCSTOP | 0x020 |
Stop the bit counter |
|
EVENTS_READY | 0x100 |
RADIO has ramped up and is ready to be started |
|
EVENTS_ADDRESS | 0x104 |
Address sent or received |
|
EVENTS_PAYLOAD | 0x108 |
Packet payload sent or received |
|
EVENTS_END | 0x10C |
Packet sent or received |
|
EVENTS_DISABLED | 0x110 |
RADIO has been disabled |
|
EVENTS_DEVMATCH | 0x114 |
A device address match occurred on the last received packet |
|
EVENTS_DEVMISS | 0x118 |
No device address match occurred on the last received packet |
|
EVENTS_RSSIEND | 0x11C |
Sampling of receive signal strength complete. |
|
EVENTS_BCMATCH | 0x128 |
Bit counter reached bit count value. |
|
EVENTS_CRCOK | 0x130 |
Packet received with CRC ok |
|
EVENTS_CRCERROR | 0x134 |
Packet received with CRC error |
|
SHORTS | 0x200 |
Shortcuts between local events and tasks |
|
INTENSET | 0x304 |
Enable interrupt |
|
INTENCLR | 0x308 |
Disable interrupt |
|
CRCSTATUS | 0x400 |
CRC status |
|
RXMATCH | 0x408 |
Received address |
|
RXCRC | 0x40C |
CRC field of previously received packet |
|
DAI | 0x410 |
Device address match index |
|
PACKETPTR | 0x504 |
Packet pointer |
|
FREQUENCY | 0x508 |
Frequency |
|
TXPOWER | 0x50C |
Output power |
|
MODE | 0x510 |
Data rate and modulation |
|
PCNF0 | 0x514 |
Packet configuration register 0 |
|
PCNF1 | 0x518 |
Packet configuration register 1 |
|
BASE0 | 0x51C |
Base address 0 |
|
BASE1 | 0x520 |
Base address 1 |
|
PREFIX0 | 0x524 |
Prefixes bytes for logical addresses 0-3 |
|
PREFIX1 | 0x528 |
Prefixes bytes for logical addresses 4-7 |
|
TXADDRESS | 0x52C |
Transmit address select |
|
RXADDRESSES | 0x530 |
Receive address select |
|
CRCCNF | 0x534 |
CRC configuration |
|
CRCPOLY | 0x538 |
CRC polynomial |
|
CRCINIT | 0x53C |
CRC initial value |
|
UNUSED0 | 0x540 |
Reserved |
|
TIFS | 0x544 |
Inter Frame Spacing in us |
|
RSSISAMPLE | 0x548 |
RSSI sample |
|
STATE | 0x550 |
Current radio state |
|
DATAWHITEIV | 0x554 |
Data whitening initial value |
|
BCC | 0x560 |
Bit counter compare |
|
DAB[0] | 0x600 |
Device address base segment 0 |
|
DAB[1] | 0x604 |
Device address base segment 1 |
|
DAB[2] | 0x608 |
Device address base segment 2 |
|
DAB[3] | 0x60C |
Device address base segment 3 |
|
DAB[4] | 0x610 |
Device address base segment 4 |
|
DAB[5] | 0x614 |
Device address base segment 5 |
|
DAB[6] | 0x618 |
Device address base segment 6 |
|
DAB[7] | 0x61C |
Device address base segment 7 |
|
DAP[0] | 0x620 |
Device address prefix 0 |
|
DAP[1] | 0x624 |
Device address prefix 1 |
|
DAP[2] | 0x628 |
Device address prefix 2 |
|
DAP[3] | 0x62C |
Device address prefix 3 |
|
DAP[4] | 0x630 |
Device address prefix 4 |
|
DAP[5] | 0x634 |
Device address prefix 5 |
|
DAP[6] | 0x638 |
Device address prefix 6 |
|
DAP[7] | 0x63C |
Device address prefix 7 |
|
DACNF | 0x640 |
Device address match configuration |
|
MODECNF0 | 0x650 |
Radio mode configuration register 0 |
|
POWER | 0xFFC |
Peripheral power control |
Address offset: 0x000
Enable RADIO in TX mode
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID |
A |
||||||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | Access | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | W |
TASKS_TXEN |
Enable RADIO in TX mode |
||||||||||||||||||||||||||||||||
Trigger |
1 |
Trigger task |
Address offset: 0x004
Enable RADIO in RX mode
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID |
A |
||||||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | Access | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | W |
TASKS_RXEN |
Enable RADIO in RX mode |
||||||||||||||||||||||||||||||||
Trigger |
1 |
Trigger task |
Address offset: 0x008
Start RADIO
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID |
A |
||||||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | Access | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | W |
TASKS_START |
Start RADIO |
||||||||||||||||||||||||||||||||
Trigger |
1 |
Trigger task |
Address offset: 0x00C
Stop RADIO
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID |
A |
||||||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | Access | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | W |
TASKS_STOP |
Stop RADIO |
||||||||||||||||||||||||||||||||
Trigger |
1 |
Trigger task |
Address offset: 0x010
Disable RADIO
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID |
A |
||||||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | Access | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | W |
TASKS_DISABLE |
Disable RADIO |
||||||||||||||||||||||||||||||||
Trigger |
1 |
Trigger task |
Address offset: 0x014
Start the RSSI and take one single sample of the receive signal strength.
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID |
A |
||||||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | Access | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | W |
TASKS_RSSISTART |
Start the RSSI and take one single sample of the receive signal strength. |
||||||||||||||||||||||||||||||||
Trigger |
1 |
Trigger task |
Address offset: 0x018
Stop the RSSI measurement
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID |
A |
||||||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | Access | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | W |
TASKS_RSSISTOP |
Stop the RSSI measurement |
||||||||||||||||||||||||||||||||
Trigger |
1 |
Trigger task |
Address offset: 0x01C
Start the bit counter
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID |
A |
||||||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | Access | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | W |
TASKS_BCSTART |
Start the bit counter |
||||||||||||||||||||||||||||||||
Trigger |
1 |
Trigger task |
Address offset: 0x020
Stop the bit counter
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID |
A |
||||||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | Access | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | W |
TASKS_BCSTOP |
Stop the bit counter |
||||||||||||||||||||||||||||||||
Trigger |
1 |
Trigger task |
Address offset: 0x100
RADIO has ramped up and is ready to be started
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID |
A |
||||||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | Access | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
EVENTS_READY |
RADIO has ramped up and is ready to be started |
||||||||||||||||||||||||||||||||
NotGenerated |
0 |
Event not generated |
|||||||||||||||||||||||||||||||||
Generated |
1 |
Event generated |
Address offset: 0x104
Address sent or received
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID |
A |
||||||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | Access | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
EVENTS_ADDRESS |
Address sent or received |
||||||||||||||||||||||||||||||||
NotGenerated |
0 |
Event not generated |
|||||||||||||||||||||||||||||||||
Generated |
1 |
Event generated |
Address offset: 0x108
Packet payload sent or received
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID |
A |
||||||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | Access | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
EVENTS_PAYLOAD |
Packet payload sent or received |
||||||||||||||||||||||||||||||||
NotGenerated |
0 |
Event not generated |
|||||||||||||||||||||||||||||||||
Generated |
1 |
Event generated |
Address offset: 0x10C
Packet sent or received
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID |
A |
||||||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | Access | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
EVENTS_END |
Packet sent or received |
||||||||||||||||||||||||||||||||
NotGenerated |
0 |
Event not generated |
|||||||||||||||||||||||||||||||||
Generated |
1 |
Event generated |
Address offset: 0x110
RADIO has been disabled
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID |
A |
||||||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | Access | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
EVENTS_DISABLED |
RADIO has been disabled |
||||||||||||||||||||||||||||||||
NotGenerated |
0 |
Event not generated |
|||||||||||||||||||||||||||||||||
Generated |
1 |
Event generated |
Address offset: 0x114
A device address match occurred on the last received packet
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID |
A |
||||||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | Access | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
EVENTS_DEVMATCH |
A device address match occurred on the last received packet |
||||||||||||||||||||||||||||||||
NotGenerated |
0 |
Event not generated |
|||||||||||||||||||||||||||||||||
Generated |
1 |
Event generated |
Address offset: 0x118
No device address match occurred on the last received packet
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID |
A |
||||||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | Access | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
EVENTS_DEVMISS |
No device address match occurred on the last received packet |
||||||||||||||||||||||||||||||||
NotGenerated |
0 |
Event not generated |
|||||||||||||||||||||||||||||||||
Generated |
1 |
Event generated |
Address offset: 0x11C
Sampling of receive signal strength complete.
A new RSSI sample is ready for readout from the RADIO.RSSISAMPLE register
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID |
A |
||||||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | Access | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
EVENTS_RSSIEND |
Sampling of receive signal strength complete. A new RSSI sample is ready for readout from the RADIO.RSSISAMPLE register |
||||||||||||||||||||||||||||||||
NotGenerated |
0 |
Event not generated |
|||||||||||||||||||||||||||||||||
Generated |
1 |
Event generated |
Address offset: 0x128
Bit counter reached bit count value.
Bit counter value is specified in the RADIO.BCC register
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID |
A |
||||||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | Access | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
EVENTS_BCMATCH |
Bit counter reached bit count value. Bit counter value is specified in the RADIO.BCC register |
||||||||||||||||||||||||||||||||
NotGenerated |
0 |
Event not generated |
|||||||||||||||||||||||||||||||||
Generated |
1 |
Event generated |
Address offset: 0x130
Packet received with CRC ok
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID |
A |
||||||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | Access | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
EVENTS_CRCOK |
Packet received with CRC ok |
||||||||||||||||||||||||||||||||
NotGenerated |
0 |
Event not generated |
|||||||||||||||||||||||||||||||||
Generated |
1 |
Event generated |
Address offset: 0x134
Packet received with CRC error
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID |
A |
||||||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | Access | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
EVENTS_CRCERROR |
Packet received with CRC error |
||||||||||||||||||||||||||||||||
NotGenerated |
0 |
Event not generated |
|||||||||||||||||||||||||||||||||
Generated |
1 |
Event generated |
Address offset: 0x200
Shortcuts between local events and tasks
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID |
H |
G |
F |
E |
D |
C |
B |
A |
|||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | Access | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
READY_START |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Disable shortcut |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Enable shortcut |
|||||||||||||||||||||||||||||||||
B | RW |
END_DISABLE |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Disable shortcut |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Enable shortcut |
|||||||||||||||||||||||||||||||||
C | RW |
DISABLED_TXEN |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Disable shortcut |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Enable shortcut |
|||||||||||||||||||||||||||||||||
D | RW |
DISABLED_RXEN |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Disable shortcut |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Enable shortcut |
|||||||||||||||||||||||||||||||||
E | RW |
ADDRESS_RSSISTART |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Disable shortcut |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Enable shortcut |
|||||||||||||||||||||||||||||||||
F | RW |
END_START |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Disable shortcut |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Enable shortcut |
|||||||||||||||||||||||||||||||||
G | RW |
ADDRESS_BCSTART |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Disable shortcut |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Enable shortcut |
|||||||||||||||||||||||||||||||||
H | RW |
DISABLED_RSSISTOP |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Disable shortcut |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Enable shortcut |
Address offset: 0x304
Enable interrupt
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID |
K |
J |
I |
H |
G |
F |
E |
D |
C |
B |
A |
||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | Access | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
READY |
Write '1' to enable interrupt for event READY |
||||||||||||||||||||||||||||||||
Set |
1 |
Enable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Read: Enabled |
|||||||||||||||||||||||||||||||||
B | RW |
ADDRESS |
Write '1' to enable interrupt for event ADDRESS |
||||||||||||||||||||||||||||||||
Set |
1 |
Enable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Read: Enabled |
|||||||||||||||||||||||||||||||||
C | RW |
PAYLOAD |
Write '1' to enable interrupt for event PAYLOAD |
||||||||||||||||||||||||||||||||
Set |
1 |
Enable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Read: Enabled |
|||||||||||||||||||||||||||||||||
D | RW |
END |
Write '1' to enable interrupt for event END |
||||||||||||||||||||||||||||||||
Set |
1 |
Enable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Read: Enabled |
|||||||||||||||||||||||||||||||||
E | RW |
DISABLED |
Write '1' to enable interrupt for event DISABLED |
||||||||||||||||||||||||||||||||
Set |
1 |
Enable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Read: Enabled |
|||||||||||||||||||||||||||||||||
F | RW |
DEVMATCH |
Write '1' to enable interrupt for event DEVMATCH |
||||||||||||||||||||||||||||||||
Set |
1 |
Enable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Read: Enabled |
|||||||||||||||||||||||||||||||||
G | RW |
DEVMISS |
Write '1' to enable interrupt for event DEVMISS |
||||||||||||||||||||||||||||||||
Set |
1 |
Enable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Read: Enabled |
|||||||||||||||||||||||||||||||||
H | RW |
RSSIEND |
Write '1' to enable interrupt for event RSSIEND A new RSSI sample is ready for readout from the RADIO.RSSISAMPLE register |
||||||||||||||||||||||||||||||||
Set |
1 |
Enable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Read: Enabled |
|||||||||||||||||||||||||||||||||
I | RW |
BCMATCH |
Write '1' to enable interrupt for event BCMATCH Bit counter value is specified in the RADIO.BCC register |
||||||||||||||||||||||||||||||||
Set |
1 |
Enable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Read: Enabled |
|||||||||||||||||||||||||||||||||
J | RW |
CRCOK |
Write '1' to enable interrupt for event CRCOK |
||||||||||||||||||||||||||||||||
Set |
1 |
Enable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Read: Enabled |
|||||||||||||||||||||||||||||||||
K | RW |
CRCERROR |
Write '1' to enable interrupt for event CRCERROR |
||||||||||||||||||||||||||||||||
Set |
1 |
Enable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Read: Enabled |
Address offset: 0x308
Disable interrupt
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID |
K |
J |
I |
H |
G |
F |
E |
D |
C |
B |
A |
||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | Access | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
READY |
Write '1' to disable interrupt for event READY |
||||||||||||||||||||||||||||||||
Clear |
1 |
Disable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Read: Enabled |
|||||||||||||||||||||||||||||||||
B | RW |
ADDRESS |
Write '1' to disable interrupt for event ADDRESS |
||||||||||||||||||||||||||||||||
Clear |
1 |
Disable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Read: Enabled |
|||||||||||||||||||||||||||||||||
C | RW |
PAYLOAD |
Write '1' to disable interrupt for event PAYLOAD |
||||||||||||||||||||||||||||||||
Clear |
1 |
Disable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Read: Enabled |
|||||||||||||||||||||||||||||||||
D | RW |
END |
Write '1' to disable interrupt for event END |
||||||||||||||||||||||||||||||||
Clear |
1 |
Disable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Read: Enabled |
|||||||||||||||||||||||||||||||||
E | RW |
DISABLED |
Write '1' to disable interrupt for event DISABLED |
||||||||||||||||||||||||||||||||
Clear |
1 |
Disable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Read: Enabled |
|||||||||||||||||||||||||||||||||
F | RW |
DEVMATCH |
Write '1' to disable interrupt for event DEVMATCH |
||||||||||||||||||||||||||||||||
Clear |
1 |
Disable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Read: Enabled |
|||||||||||||||||||||||||||||||||
G | RW |
DEVMISS |
Write '1' to disable interrupt for event DEVMISS |
||||||||||||||||||||||||||||||||
Clear |
1 |
Disable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Read: Enabled |
|||||||||||||||||||||||||||||||||
H | RW |
RSSIEND |
Write '1' to disable interrupt for event RSSIEND A new RSSI sample is ready for readout from the RADIO.RSSISAMPLE register |
||||||||||||||||||||||||||||||||
Clear |
1 |
Disable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Read: Enabled |
|||||||||||||||||||||||||||||||||
I | RW |
BCMATCH |
Write '1' to disable interrupt for event BCMATCH Bit counter value is specified in the RADIO.BCC register |
||||||||||||||||||||||||||||||||
Clear |
1 |
Disable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Read: Enabled |
|||||||||||||||||||||||||||||||||
J | RW |
CRCOK |
Write '1' to disable interrupt for event CRCOK |
||||||||||||||||||||||||||||||||
Clear |
1 |
Disable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Read: Enabled |
|||||||||||||||||||||||||||||||||
K | RW |
CRCERROR |
Write '1' to disable interrupt for event CRCERROR |
||||||||||||||||||||||||||||||||
Clear |
1 |
Disable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Read: Enabled |
Address offset: 0x400
CRC status
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID |
A |
||||||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | Access | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | R |
CRCSTATUS |
CRC status of packet received |
||||||||||||||||||||||||||||||||
CRCError |
0 |
Packet received with CRC error |
|||||||||||||||||||||||||||||||||
CRCOk |
1 |
Packet received with CRC ok |
Address offset: 0x408
Received address
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID |
A |
A |
A |
||||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | Access | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | R |
RXMATCH |
Received address Logical address of which previous packet was received |
Address offset: 0x40C
CRC field of previously received packet
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
|||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | Access | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | R |
RXCRC |
CRC field of previously received packet CRC field of previously received packet |
Address offset: 0x410
Device address match index
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID |
A |
A |
A |
||||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | Access | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | R |
DAI |
Device address match index Index (n) of device address, see DAB[n] and DAP[n], that got an address match. |
Address offset: 0x504
Packet pointer
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
|||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | Access | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
PACKETPTR |
Packet pointer Packet address to be used for the next transmission or reception. When transmitting, the packet pointed to by this address will be transmitted and when receiving, the received packet will be written to this address. This address is a byte aligned ram address. |
Address offset: 0x508
Frequency
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID |
B |
A |
A |
A |
A |
A |
A |
A |
|||||||||||||||||||||||||||
Reset 0x00000002 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | |||
ID | Access | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
FREQUENCY |
[0..100] |
Radio channel frequency Frequency = 2400 + FREQUENCY (MHz). |
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B | RW |
MAP |
Channel map selection. |
||||||||||||||||||||||||||||||||
Default |
0 |
Channel map between 2400 MHZ .. 2500 MHz Frequency = 2400 + FREQUENCY (MHz) |
|||||||||||||||||||||||||||||||||
Low |
1 |
Channel map between 2360 MHZ .. 2460 MHz Frequency = 2360 + FREQUENCY (MHz) |
Address offset: 0x50C
Output power
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID |
A |
A |
A |
A |
A |
A |
A |
A |
|||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | Access | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
TXPOWER |
RADIO output power. Output power in number of dBm, i.e. if the value -20 is specified the output power will be set to -20dBm. |
||||||||||||||||||||||||||||||||
Pos4dBm |
0x04 |
+4 dBm |
|||||||||||||||||||||||||||||||||
Pos3dBm |
0x03 |
+3 dBm |
|||||||||||||||||||||||||||||||||
0dBm |
0x00 |
0 dBm |
|||||||||||||||||||||||||||||||||
Neg4dBm |
0xFC |
-4 dBm |
|||||||||||||||||||||||||||||||||
Neg8dBm |
0xF8 |
-8 dBm |
|||||||||||||||||||||||||||||||||
Neg12dBm |
0xF4 |
-12 dBm |
|||||||||||||||||||||||||||||||||
Neg16dBm |
0xF0 |
-16 dBm |
|||||||||||||||||||||||||||||||||
Neg20dBm |
0xEC |
-20 dBm |
|||||||||||||||||||||||||||||||||
Neg30dBm |
0xE2 |
-40 dBm |
Deprecated |
||||||||||||||||||||||||||||||||
Neg40dBm |
0xD8 |
-40 dBm |
Address offset: 0x510
Data rate and modulation
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID |
A |
A |
A |
A |
|||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | Access | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
MODE |
Radio data rate and modulation setting. The radio supports Frequency-shift Keying (FSK) modulation. |
||||||||||||||||||||||||||||||||
Nrf_1Mbit |
0 |
1 Mbit/s Nordic proprietary radio mode |
|||||||||||||||||||||||||||||||||
Nrf_2Mbit |
1 |
2 Mbit/s Nordic proprietary radio mode |
|||||||||||||||||||||||||||||||||
Ble_1Mbit |
3 |
1 Mbit/s Bluetooth Low Energy |
|||||||||||||||||||||||||||||||||
Ble_2Mbit |
4 |
2 Mbit/s Bluetooth Low Energy |
Address offset: 0x514
Packet configuration register 0
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID |
G |
F |
E |
E |
E |
E |
C |
A |
A |
A |
A |
||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | Access | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
LFLEN |
Length on air of LENGTH field in number of bits. |
||||||||||||||||||||||||||||||||
C | RW |
S0LEN |
Length on air of S0 field in number of bytes. |
||||||||||||||||||||||||||||||||
E | RW |
S1LEN |
Length on air of S1 field in number of bits. |
||||||||||||||||||||||||||||||||
F | RW |
S1INCL |
Include or exclude S1 field in RAM |
||||||||||||||||||||||||||||||||
Automatic |
0 |
Include S1 field in RAM only if S1LEN > 0 |
|||||||||||||||||||||||||||||||||
Include |
1 |
Always include S1 field in RAM independent of S1LEN |
|||||||||||||||||||||||||||||||||
G | RW |
PLEN |
Length of preamble on air. Decision point: TASKS_START task |
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8bit |
0 |
8-bit preamble |
|||||||||||||||||||||||||||||||||
16bit |
1 |
16-bit preamble |
Address offset: 0x518
Packet configuration register 1
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID |
E |
D |
C |
C |
C |
B |
B |
B |
B |
B |
B |
B |
B |
A |
A |
A |
A |
A |
A |
A |
A |
||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | Access | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
MAXLEN |
[0..255] |
Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. |
|||||||||||||||||||||||||||||||
B | RW |
STATLEN |
[0..255] |
Static length in number of bytes The static length parameter is added to the total length of the payload when sending and receiving packets, e.g. if the static length is set to N the radio will receive or send N bytes more than what is defined in the LENGTH field of the packet. |
|||||||||||||||||||||||||||||||
C | RW |
BALEN |
[2..4] |
Base address length in number of bytes The address field is composed of the base address and the one byte long address prefix, e.g. set BALEN=2 to get a total address of 3 bytes. |
|||||||||||||||||||||||||||||||
D | RW |
ENDIAN |
On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields. |
||||||||||||||||||||||||||||||||
Little |
0 |
Least Significant bit on air first |
|||||||||||||||||||||||||||||||||
Big |
1 |
Most significant bit on air first |
|||||||||||||||||||||||||||||||||
E | RW |
WHITEEN |
Enable or disable packet whitening |
||||||||||||||||||||||||||||||||
Disabled |
0 |
Disable |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Enable |
Address offset: 0x51C
Base address 0
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
|||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | Access | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
BASE0 |
Base address 0 Radio base address 0. |
Address offset: 0x520
Base address 1
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
|||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | Access | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
BASE1 |
Base address 1 Radio base address 1. |
Address offset: 0x524
Prefixes bytes for logical addresses 0-3
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID |
D |
D |
D |
D |
D |
D |
D |
D |
C |
C |
C |
C |
C |
C |
C |
C |
B |
B |
B |
B |
B |
B |
B |
B |
A |
A |
A |
A |
A |
A |
A |
A |
|||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | Access | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A-D | RW |
AP[i] (i=0..3) |
Address prefix i. |
Address offset: 0x528
Prefixes bytes for logical addresses 4-7
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID |
D |
D |
D |
D |
D |
D |
D |
D |
C |
C |
C |
C |
C |
C |
C |
C |
B |
B |
B |
B |
B |
B |
B |
B |
A |
A |
A |
A |
A |
A |
A |
A |
|||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | Access | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A-D | RW |
AP[i] (i=4..7) |
Address prefix i. |
Address offset: 0x52C
Transmit address select
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID |
A |
A |
A |
||||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | Access | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
TXADDRESS |
Transmit address select Logical address to be used when transmitting a packet. |
Address offset: 0x530
Receive address select
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID |
H |
G |
F |
E |
D |
C |
B |
A |
|||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | Access | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A-H | RW |
ADDR[i] (i=0..7) |
Enable or disable reception on logical address i. |
||||||||||||||||||||||||||||||||
Disabled |
0 |
Disable |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Enable |
Address offset: 0x534
CRC configuration
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID |
B |
A |
A |
||||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | Access | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
LEN |
[1..3] |
CRC length in number of bytes. |
|||||||||||||||||||||||||||||||
Disabled |
0 |
CRC length is zero and CRC calculation is disabled |
|||||||||||||||||||||||||||||||||
One |
1 |
CRC length is one byte and CRC calculation is enabled |
|||||||||||||||||||||||||||||||||
Two |
2 |
CRC length is two bytes and CRC calculation is enabled |
|||||||||||||||||||||||||||||||||
Three |
3 |
CRC length is three bytes and CRC calculation is enabled |
|||||||||||||||||||||||||||||||||
B | RW |
SKIPADDR |
Include or exclude packet address field out of CRC calculation. |
||||||||||||||||||||||||||||||||
Include |
0 |
CRC calculation includes address field |
|||||||||||||||||||||||||||||||||
Skip |
1 |
CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. |
Address offset: 0x538
CRC polynomial
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
|||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | Access | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
CRCPOLY |
CRC polynomial Each term in the CRC polynomial is mapped to a bit in this register which index corresponds to the term's exponent. The least significant term/bit is hard-wired internally to 1, and bit number 0 of the register content is ignored by the hardware. The following example is for an 8 bit CRC polynomial: x8 + x7 + x3 + x2 + 1 = 1 1000 1101 . |
Address offset: 0x53C
CRC initial value
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
|||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | Access | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
CRCINIT |
CRC initial value Initial value for CRC calculation. |
Address offset: 0x544
Inter Frame Spacing in us
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID |
A |
A |
A |
A |
A |
A |
A |
A |
|||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | Access | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
TIFS |
Inter Frame Spacing in us Inter frame space is the time interval between two consecutive packets. It is defined as the time, in micro seconds, from the end of the last bit of the previous packet to the start of the first bit of the subsequent packet. |
Address offset: 0x548
RSSI sample
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID |
A |
A |
A |
A |
A |
A |
A |
||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | Access | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | R |
RSSISAMPLE |
[0..127] |
RSSI sample RSSI sample result. The value of this register is read as a positive value while the actual received signal strength is a negative value. Actual received signal strength is therefore as follows: received signal strength = -A dBm |
Address offset: 0x550
Current radio state
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID |
A |
A |
A |
A |
|||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | Access | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | R |
STATE |
Current radio state |
||||||||||||||||||||||||||||||||
Disabled |
0 |
RADIO is in the Disabled state |
|||||||||||||||||||||||||||||||||
RxRu |
1 |
RADIO is in the RXRU state |
|||||||||||||||||||||||||||||||||
RxIdle |
2 |
RADIO is in the RXIDLE state |
|||||||||||||||||||||||||||||||||
Rx |
3 |
RADIO is in the RX state |
|||||||||||||||||||||||||||||||||
RxDisable |
4 |
RADIO is in the RXDISABLED state |
|||||||||||||||||||||||||||||||||
TxRu |
9 |
RADIO is in the TXRU state |
|||||||||||||||||||||||||||||||||
TxIdle |
10 |
RADIO is in the TXIDLE state |
|||||||||||||||||||||||||||||||||
Tx |
11 |
RADIO is in the TX state |
|||||||||||||||||||||||||||||||||
TxDisable |
12 |
RADIO is in the TXDISABLED state |
Address offset: 0x554
Data whitening initial value
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID |
A |
A |
A |
A |
A |
A |
A |
||||||||||||||||||||||||||||
Reset 0x00000040 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | Access | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
DATAWHITEIV |
Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. Bit 0 corresponds to Position 6 of the LSFR, Bit 1 to Position 5, etc. |
Address offset: 0x560
Bit counter compare
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
|||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | Access | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
BCC |
Bit counter compare Bit counter compare register |
Address offset: 0x600 + (n × 0x4)
Device address base segment n
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
|||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | Access | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
DAB |
Device address base segment n |
Address offset: 0x620 + (n × 0x4)
Device address prefix n
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
A |
|||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | Access | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
DAP |
Device address prefix n |
Address offset: 0x640
Device address match configuration
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID |
P |
O |
N |
M |
L |
K |
J |
I |
H |
G |
F |
E |
D |
C |
B |
A |
|||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | Access | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A-H | RW |
ENA[i] (i=0..7) |
Enable or disable device address matching using device address i |
||||||||||||||||||||||||||||||||
Disabled |
0 |
Disabled |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Enabled |
|||||||||||||||||||||||||||||||||
I-P | RW |
TXADD[i] (i=0..7) |
TxAdd for device address i |
Address offset: 0x650
Radio mode configuration register 0
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID |
C |
C |
A |
||||||||||||||||||||||||||||||||
Reset 0x00000200 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
ID | Access | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
RU |
Radio ramp-up time |
||||||||||||||||||||||||||||||||
Default |
0 |
Default ramp-up time (tRXEN), compatible with firmware written for nRF51 |
|||||||||||||||||||||||||||||||||
Fast |
1 |
Fast ramp-up (tRXEN,FAST), see electrical specification for more information |
|||||||||||||||||||||||||||||||||
C | RW |
DTX |
Default TX value Specifies what the RADIO will transmit when it is not started, i.e. between: RADIO.EVENTS_READY and RADIO.TASKS_START RADIO.EVENTS_END and RADIO.TASKS_START RADIO.EVENTS_END and RADIO.EVENTS_DISABLED |
||||||||||||||||||||||||||||||||
B1 |
0 |
Transmit '1' |
|||||||||||||||||||||||||||||||||
B0 |
1 |
Transmit '0' |
|||||||||||||||||||||||||||||||||
Center |
2 |
Transmit center frequency When tuning the crystal for centre frequency, the RADIO must be set in DTX = Center mode to be able to achieve the expected accuracy. |
Address offset: 0xFFC
Peripheral power control
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ID |
A |
||||||||||||||||||||||||||||||||||
Reset 0x00000001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | |||
ID | Access | Field | Value ID | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
POWER |
Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. |
||||||||||||||||||||||||||||||||
Disabled |
0 |
Peripheral is powered off |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Peripheral is powered on |
Symbol | Description | Min. | Typ. | Max. | Units | ||||
---|---|---|---|---|---|---|---|---|---|
fOP |
Operating frequencies |
2360 | 2500 | MHz | |||||
fPLL,PROG,RES |
PLL programming resolution |
2 | kHz | ||||||
fPLL,CH,SP |
PLL channel spacing |
1 | MHz | ||||||
fDELTA,1M |
Frequency deviation @ 1 Mbps |
±170 | kHz | ||||||
fDELTA,BLE,1M |
Frequency deviation @ BLE 1 Mbps |
±250 | kHz | ||||||
fDELTA,2M |
Frequency deviation @ 2 Mbps |
±320 | kHz | ||||||
fDELTA,BLE,2M |
Frequency deviation @ BLE 2 Mbps |
±500 | kHz | ||||||
fskSPS |
On-the-air data rate |
1 | 2 | Mbps |
Symbol | Description | Min. | Typ. | Max. | Units | ||||
---|---|---|---|---|---|---|---|---|---|
ITX,PLUS4dBM,DCDC |
TX only run current (DCDC, 3V) PRF =+4 dBm |
7.0 | mA | ||||||
ITX,PLUS4dBM |
TX only run current PRF = +4 dBm |
15.4 | mA | ||||||
ITX,0dBM,DCDC |
TX only run current (DCDC, 3V)PRF = 0dBm |
4.6 | mA | ||||||
ITX,0dBM |
TX only run current PRF = 0dBm |
10.1 | mA | ||||||
ITX,MINUS4dBM,DCDC |
TX only run current DCDC, 3V PRF = -4dBm |
3.6 | mA | ||||||
ITX,MINUS4dBM |
TX only run current PRF = -4 dBm |
7.8 | mA | ||||||
ITX,MINUS8dBM,DCDC |
TX only run current DCDC, 3V PRF = -8 dBm |
3.2 | mA | ||||||
ITX,MINUS8dBM |
TX only run current PRF = -8 dBm |
6.8 | mA | ||||||
ITX,MINUS12dBM,DCDC |
TX only run current DCDC, 3V PRF = -12 dBm |
2.9 | mA | ||||||
ITX,MINUS12dBM |
TX only run current PRF = -12 dBm |
6.2 | mA | ||||||
ITX,MINUS16dBM,DCDC |
TX only run current DCDC, 3V PRF = -16 dBm |
2.7 | mA | ||||||
ITX,MINUS16dBM |
TX only run current PRF = -16 dBm |
5.7 | mA | ||||||
ITX,MINUS20dBM,DCDC |
TX only run current DCDC, 3V PRF = -20 dBm |
2.5 | mA | ||||||
ITX,MINUS20dBM |
TX only run current PRF = -20 dBm |
5.4 | mA | ||||||
ITX,MINUS40dBM,DCDC |
TX only run current DCDC, 3V PRF = -40 dBm |
2.1 | mA | ||||||
ITX,MINUS40dBM |
TX only run current PRF = -40 dBm |
4.3 | mA |
Symbol | Description | Min. | Typ. | Max. | Units | ||||
---|---|---|---|---|---|---|---|---|---|
IRX,1M,DCDC |
RX only run current (DCDC, 3V) 1 Mbps / 1 Mbps BLE |
4.6 | mA | ||||||
IRX,1M |
RX only run current 1 Mbps / 1 Mbps BLE |
10.0 | mA | ||||||
IRX,2M,DCDC |
RX only run current (DCDC, 3V) 2 Mbps / 2 Mbps BLE |
5.2 | mA | ||||||
IRX,2M |
RX only run current 2 Mbps / 2 Mbps BLE |
11.2 | mA | ||||||
ISTART,RX,1M,DCDC |
RX start-up current (DCDC, 3 V) 1 Mbps / 1 Mbps BLE |
3.5 | mA | ||||||
ISTART,RX,1M |
RX start-up current 1 Mbps / 1 Mbps BLE |
6.7 | mA |
Symbol | Description | Min. | Typ. | Max. | Units | ||||
---|---|---|---|---|---|---|---|---|---|
PRF |
Maximum output power |
4 | 8 | dBm | |||||
PRFC |
RF power control range |
24 | dB | ||||||
PRFCR |
RF power accuracy |
±4 | dB | ||||||
PRF1,1 |
1st Adjacent Channel Transmit Power 1 MHz (1 Mbps) |
-25 | dBc | ||||||
PRF2,1 |
2nd Adjacent Channel Transmit Power 2 MHz (1 Mbps) |
-50 | dBc | ||||||
PRF1,2 |
1st Adjacent Channel Transmit Power 2 MHz (2 Mbps) |
-25 | dBc | ||||||
PRF2,2 |
2nd Adjacent Channel Transmit Power 4 MHz (2 Mbps) |
-50 | dBc |
Symbol | Description | Min. | Typ. | Max. | Units | ||||
---|---|---|---|---|---|---|---|---|---|
PRX,MAX |
Maximum received signal strength at < 0.1% BER |
0 | dBm | ||||||
PSENS,IT,1M |
Sensitivity, 1 Mbps nRF mode ideal transmitter1 |
-93 | dBm | ||||||
PSENS,IT,2M |
Sensitivity, 2 Mbps nRF mode ideal transmitter2 |
-89 | dBm | ||||||
PSENS,IT,SP,1M,BLE |
Sensitivity, 1 Mbps BLE ideal transmitter, <=37 bytes BER=1E-33 |
-96 | dBm | ||||||
PSENS,IT,LP,1M,BLE |
Sensitivity, 1 Mbps BLE ideal transmitter >=128 bytes BER=1E-4 4 |
-95 | dBm | ||||||
PSENS,IT,SP,2M,BLE |
Sensitivity, 2 Mbps BLE ideal transmitter, Packet length <=37bytes |
-93 | dBm |
RX selectivity with equal modulation on interfering signal5
Symbol | Description | Min. | Typ. | Max. | Units | ||||
---|---|---|---|---|---|---|---|---|---|
C/I1M,co-channel |
1 Mbps mode, Co-Channel interference |
9 | dB | ||||||
C/I1M,-1MHz |
1 Mbps mode, Adjacent (-1 MHz) interference |
-2 | dB | ||||||
C/I1M,+1MHz |
1 Mbps mode, Adjacent (+1 MHz) interference |
-10 | dB | ||||||
C/I1M,-2MHz |
1 Mbps mode, Adjacent (-2 MHz) interference |
-19 | dB | ||||||
C/I1M,+2MHz |
1 Mbps mode, Adjacent (+2 MHz) interference |
-42 | dB | ||||||
C/I1M,-3MHz |
1 Mbps mode, Adjacent (-3 MHz) interference |
-38 | dB | ||||||
C/I1M,+3MHz |
1 Mbps mode, Adjacent (+3 MHz) interference |
-48 | dB | ||||||
C/I1M,±6MHz |
1 Mbps mode, Adjacent (≥6 MHz) interference |
-50 | dB | ||||||
C/I1MBLE,co-channel |
1 Mbps BLE mode, Co-Channel interference |
6 | dB | ||||||
C/I1MBLE,-1MHz |
1 Mbps BLE mode, Adjacent (-1 MHz) interference |
-2 | dB | ||||||
C/I1MBLE,+1MHz |
1 Mbps BLE mode, Adjacent (+1 MHz) interference |
-9 | dB | ||||||
C/I1MBLE,-2MHz |
1 Mbps BLE mode, Adjacent (-2 MHz) interference |
-22 | dB | ||||||
C/I1MBLE,+2MHz |
1 Mbps BLE mode, Adjacent (+2 MHz) interference |
-46 | dB | ||||||
C/I1MBLE,>3MHz |
1 Mbps BLE mode, Adjacent (≥3 MHz) interference |
-50 | dB | ||||||
C/I1MBLE,image |
Image frequency Interference |
-22 | dB | ||||||
C/I1MBLE,image,1MHz |
Adjacent (1 MHz) interference to in-band image frequency |
-35 | dB | ||||||
C/I2M,co-channel |
2 Mbps mode, Co-Channel interference |
10 | dB | ||||||
C/I2M,-2MHz |
2 Mbps mode, Adjacent (-2 MHz) interference |
6 | dB | ||||||
C/I2M,+2MHz |
2 Mbps mode, Adjacent (+2 MHz) interference |
-14 | dB | ||||||
C/I2M,-4MHz |
2 Mbps mode, Adjacent (-4 MHz) interference |
-20 | dB | ||||||
C/I2M,+4MHz |
2 Mbps mode, Adjacent (+4 MHz) interference |
-44 | dB | ||||||
C/I2M,-6MHz |
2 Mbps mode, Adjacent (-6 MHz) interference |
-42 | dB | ||||||
C/I2M,+6MHz |
2 Mbps mode, Adjacent (+6 MHz) interference |
-47 | dB | ||||||
C/I2M,≥12MHz |
2 Mbps mode, Adjacent (≥12 MHz) interference |
-52 | dB |
RX intermodulation6
Symbol | Description | Min. | Typ. | Max. | Units | ||||
---|---|---|---|---|---|---|---|---|---|
PIMD,5TH,1M |
IMD performance, 1 Msps, 5th offset channel, Packet length <= 37 bytes |
-33 | dBm | ||||||
PIMD,5TH,1M,BLE |
IMD performance, BLE 1 Msps, 5th offset channel, Packet length <= 37 bytes |
-30 | dBm | ||||||
PIMD,5TH,2M |
IMD performance, 2 Msps, 5th offset channel, Packet length <= 37 bytes |
-33 | dBm | ||||||
PIMD,5TH,2M,BLE |
IMD performance, BLE 2 Msps, 5th offset channel, Packet length <= 37 bytes |
-31 | dBm |
Symbol | Description | Min. | Typ. | Max. | Units | ||||
---|---|---|---|---|---|---|---|---|---|
tTXEN |
Time between TXEN task and READY event after channel FREQUENCY configured. Compatible with old devices. |
140 | 140 | µs | |||||
tTXEN,FAST |
Time between TXEN task and READY event after channel FREQUENCY configured (Fast Mode) |
40 | 40 | µs | |||||
tTXDISABLE,1M |
Time between DISABLE task and DISABLED event when the radio was in TX for MODE = Nrf_1Mbit and MODE = Ble_1Mbit |
6 | 6 | µs | |||||
tTXDISABLE,2M |
Time between DISABLE task and DISABLED event when the radio was in TX and mode is set to 2 Mbps |
4 | 4 | µs | |||||
tRXEN |
Time between the RXEN task and READY event after channel FREQUENCY configured in default mode. Compatible with old devices. |
140 | 140 | µs | |||||
tRXEN,FAST |
Time between the RXEN task and READY event after channel FREQUENCY configured in fast mode |
40 | 40 | µs | |||||
tSWITCH |
The minimum time taken to switch from RX to TX or TX to RX when channel FREQUENCY unchanged |
20 | µs | ||||||
tRXDISABLE |
Time between DISABLE task and DISABLED event when the radio was in RX |
0 | 0 | µs | |||||
tTXCHAIN |
Digital propagation delay (in radio only) when transmitting. Does not include EasyDMA access time. |
0.6 | µs | ||||||
tRXCHAIN |
Digital propagation delay (in radio only) when receiving. Does not include EasyDMA access time. |
9.4 | µs | ||||||
tRXCHAIN,2M |
Digital propagation delay in 2 Mbps mode (radio only) when receiving. Does not include EasyDMA access time. |
5 | µs |
Symbol | Description | Min. | Typ. | Max. | Units | ||||
---|---|---|---|---|---|---|---|---|---|
RSSIACC |
RSSI accuracy valid range -90 to -20 dBm |
±2 | dB | ||||||
RSSIRESOLUTION |
RSSI resolution |
1 | dB | ||||||
RSSIPERIOD |
RSSI sampling time from RSSI_START task |
0.25 | µs | ||||||
RSSISETTLE |
RSSI settling time after signal level change |
15 | µs |
Symbol | Description | Min. | Typ. | Max. | Units | ||||
---|---|---|---|---|---|---|---|---|---|
tDISABLEDJITTER |
Jitter on DISABLED event relative to END event when shortcut between END and DISABLE is enabled. |
0.25 | µs | ||||||
tREADYJITTER |
Jitter on READY event relative to TXEN and RXEN task. |
0.25 | µs |