AHB multilayer enables parallel access paths between multiple masters and slaves in a system. Access is resolved using priorities.
Each bus master is connected to the slave devices using an interconnection matrix. The bus masters are assigned priorities. Priorities are used to resolve access when two (or more) bus masters request access to the same slave device. The following applies:
Below is a list of bus masters in the system and their priorities.
Bus master name | Description |
---|---|
CPU | |
SPIM0/SPIS0 | Same priority and mutually exclusive |
RADIO | |
CCM/ECB/AAR | Same priority and mutually exclusive |
SAADC | |
UARTE0 | |
TWIM0/TWIS0 | Same priority and mutually exclusive |
Defined bus masters are the CPU and the peripherals with implemented EasyDMA, and the available slaves are RAM AHB slaves. How the bus masters and slaves are connected using the interconnection matrix is illustrated in Memory.