Pin assignments
The pin assignment figures and tables describe the pinouts for the product variants of the chip.
WLCSP ball assignments
The ball assignment figure and table describe the assignments for this variant of the chip.
Figure 1. WLCSP ball assignments
| Pin | Name | Function | Description | Recommended usage |
|---|---|---|---|---|
| A1 | D- | Analog input | USB D- data line | |
| A2 | D+ | Analog input | USB D+ data line | |
| A3 | DEC | Power | System decoupling capacitor | |
| A4 | SW | Power | BUCK regulator output (to inductor) | |
| A5 | PVSS | Power | Ground (DC/DC) | |
| B1 | VBUS | Power | Input supply | |
| B2 | VBUS | Power | Input supply | |
| B3 | VOUTBSET1 | Digital I/O | BUCK regulator output voltage selection | Toggle only when the device is in Power OFF |
| B4 | VOUTBSET0 | Digital I/O | BUCK regulator output voltage selection | Toggle only when the device is in Power OFF |
| B5 | VOUTB | Power | BUCK regulator output | |
| C1 | VSYS | Power | System voltage output; automatically enabled after power-on reset | |
| C2 | VSYS | Power | System voltage output; automatically enabled after power-on reset | |
| C3 | VTERMSET | Digital I/O | Battery charging termination voltage selection | Toggle only when the device is in Power OFF |
| C4 | AVSS | Power | Ground | |
| C5 | AVSS | Power | Ground | |
| D1 | VBAT | Power | Battery | |
| D2 | VBAT | Power | Battery | |
| D3 | SHPHLD | Digital I/O | Shipping mode hold | |
| D4 | SHPACT | Digital I/O | Shipping mode activate | |
| D5 | ISET | Digital I/O |
VBUS current limit selection: 0 mA to 100 mA (SDP mode only) 1 mA to 500 mA |
|
| E1 | NTC | Analog input | NTC resistor | |
| E2 | ICHG | Analog input | Charge current limiting resistor | |
| E3 | ERR | Digital OUT | Open-drain LED driver; enabled when error condition in charging | |
| E4 | CHG | Digital OUT | Open-drain LED driver; enabled when battery is charging | |
| E5 | MODE | Digital I/O | 0 - automatic 1 - Forced PWM |
Note: VOUTBSET1 and VOUTBSET0 balls are located close to AVSS, DEC, and VSYS to allow connection to tracks on the PCB without any via holes.
QFN24 pin assignments
The pin assignment figure and table describe the assignments for this variant of the chip.
Figure 2. QFN pin assignments
| Pin | Name | Function | Description |
|---|---|---|---|
| 1 | VOUTB | Power | BUCK regulator output |
| 2 | VOUTBSET1 | Digital I/O | BUCK regulator output voltage selection |
| 3 | VOUTBSET2 | Digital I/O | BUCK regulator output voltage selection |
| 4 | NC | ||
| 5 | ISET | Digital I/O | VBUS current limit selection: 0 mA to 100 mA (SDP mode only) 1 mA to 500 mA |
| 6 | SHPACT | Digital I/O | Shipping mode activate |
| 7 | MODE | Digital I/O | 0 - automatic 1 - Forced PWM |
| 8 | CHG | Digital OUT | Open-drain LED driver; enabled when battery is charging |
| 9 | VTERMSET | Battery charging termination voltage selection | Toggle only when the device is in Power OFF |
| 10 | ERR | Digital OUT | Open-drain LED driver; enabled when error condition in charging |
| 11 | SHPHLD | Digital I/O | Shipping mode hold |
| 12 | ICHG | Analog input | Charge current limiting resistor |
| 13 | NC | ||
| 14 | NTC | Analog input | NTC resistor |
| 15 | VBAT | Power | Battery |
| 16 | VSYS | Power | System voltage output; automatically enabled after power-on reset |
| 17 | VBUS | Power | Input supply |
| 18 | NC | ||
| 19 | D- | Analog input | USB D- data line |
| 20 | D+ | Analog input | USB D+ data line |
| 21 | DEC | Power | System decoupling capacitor |
| 22 | SW | Power | BUCK regulator output (to inductor) |
| 23 | PVSS | Power | Ground (DC/DC) |
| 24 | NC |