Programming

When programming an nRF52 Series 32-bit SoC, the software is written to specific memory regions in flash.

The following sections in the nRF52832 Product Specification contain relevant information for programming SoCs:

• nRF52 series devices use flash-based non-volatile memory (NVM) in the code flash and UICR memory regions. For details, see section Memory in the nRF52832 Product Specification.
• See section Memory in the nRF52832 Product Specification for information about flash page size and number.
  Important: The Non-volatile memory controller (NVMC) is only able to write bits in the NVM that are erased (set to ‘1’). The NVMC is used for writing and erasing all flash memory. Before a write can be performed, the NVM must be enabled for writing in CONFIG.WEN. Similarly, before an erase can be performed, the NVM must be configured for erasing in CONFIG.EEN. The CPU is halted when the NVMC is performing a write/erase operation. Check the Ready flag to make sure the NVMC is not busy with an ongoing write or erase operation before performing an operation with the NVMC.
• The Debug and trace module provides access to the on-chip debug functionality. This is a standard two-pin serial wire debug (SWD) interface as defined by Arm® For details, see Debug and trace section in the nRF52832 Product Specification.
  Note: The SWDIO line has an internal pull-up resistor and the SWDCLK line has an internal pull-down resistor.
• See section NVMC — Non-volatile memory controller in the nRF52832 Product Specification for detailed specifications regarding timing for write/erase operations. For example, it takes the NVMC 67.5 (min) to 338 microseconds (max) to write one word in flash, and it takes between 6.72 (min) and 295.3 (max) milliseconds to erase all flash. Based on this information, the theoretical fastest run-time of flash programming algorithms can be calculated. The theoretical best time to write the entire flash of an nRF52832 device is approximately 8.85 seconds: (512 * 1024) / 4 * (67.5 * 10^-6).
  Note: This is theoretical because it does not take real-world overhead into consideration, such as external tester interface, algorithm executed in RAM, SWDP speed, etc.