Use the standard SWD Arm® CoreSight™ Debug Access Port (DAP) protocol to enter Debug interface (DIF) mode. A standard DAP as provided by ARM is used and the Debug Port (DP) is in an always-on domain to secure that the CxxxPWRUPREQ can be issued even if the device is in System OFF mode.
For more information about DIF mode, see section Debug interface (DIF) mode in the nRF52832 Product Specification.
Before the external debugger can access the CPU, it must first request and make sure that the appropriate power domains are powered up. This is handled using the built-in CxxxPWRUPREQ and CxxxPWRUPACK feature found in the Arm CoreSight DAP. As long as the debugger is requesting the debug domain or the complete system to be powered up, the device will be in debug interface mode.