PCB land pattern design

This chapter contains a recommended PCB land pattern for the aQFN73™ package.

The layout in the following figures illustrates the use of a four-layer board with micro vias:

Figure 1. Top layer
Top layer
Figure 2. Mid layer 1
Mid layer 1
Figure 3. Mid layer 2
Mid layer 1
Figure 4. Bottom layer
Bottom layer
Figure 5. Top silkscreen overlay
Top silkscreen overlay
Figure 6. Top solder mask
Top solder mask
Figure 7. Top paste mask
Top paste mask
Figure 8. Via capping
Via capping

Due to the 0.5 mm pitch of the pads in the aQFN™ package, using via-in-pad technology for routing inner pads is required. Using IPC-4761 Type VII: Filled and capped vias is recommended to ensure good soldering.

Table 1. Used design rules
Parameter Design rule (mm)
Minimum trace width 0.145
Minimum clearance 0.145
Hole size blind via 0.15
Hole size through hole via 0.305
Via pad blind via 0.35
Via pad through hole via 0.61

As the copper pad diameter is small, to ensure an even surface with good solderability, using Electroless Nickel Immersion Gold (ENIG) or similar surface finish on the circuit board is recommended.

For more information on the PCB land pattern design, see the reference layout files at www.nordicsemi.com.