On the nRF51 Series, the processor core and the AHB and APB bus-system ran on a 16 MHz clock. On the nRF52 Series, the processor core and AHB system run at 64 MHz, while the APB system runs at 16 MHz. This means that reading from or writing to peripherals on the APB system will take relatively longer time on the nRF52 Series.
However, because Cortex®-M4 uses a write buffer, the core is able to continue executing code that does not access the system bus further. Reordering APB-intensive code to interleave APB accesses with non-memory operations can therefore speed up the code. Read accesses will always stall the processor until the bus transfer is completed, and it will force the write buffer to be emptied before the read is initiated.
Executing code from flash has a wait-state penalty on the nRF52 Series. This is because of the increased processor frequency compared to the nRF51 Series which had zero wait states on executing code from flash. The number of wait-states can be looked up in the product specification, and depends on whether the cache is enabled or not. Wait-states when executing code from flash are mitigated by a direct-mapped cache that can be enabled through the NVMC peripheral. Cortex-M4F does prefetching, so sequential code executing is capable of running without stalling the pipeline in many cases.