| nRF5340 Revision 1 v1.8 |
10.01.2024 |
- Added: No. 159. “Data can be corrupted in certain clock configurations ”
- Added: No. 166. “VREGMAIN can malfunction in LDO mode”
- Added: No. 167. “SPU FLASHACCERR is generated after re-enabling USBD ”
- Added: No. 168. “CPU can malfunction after sleep”
|
| nRF5340 Revision 1 v1.7 |
13.09.2023 |
- Added: No. 155. “Incorrect value for ED_RSSISCALE”
- Added: No. 157. “On-the-fly decryption fails for direction finding packets”
- Added: No. 162. “WLCSP package dimension A3 is incorrect”
- Added: No. 163. “Gain error exceeds specified value when using VDD as reference ”
- Added: No. 165. “Network core can malfunction after CPU sleep”
- Updated: No. 161. “Network core is not fully reset after Force-OFF”
|
| nRF5340 Revision 1 v1.6 |
01.03.2023 |
- Added: No. 160. “VREGMAIN and VREGRADIO can malfunction in DC/DC mode”
- Added: No. 161. “Core is not fully reset after Force-OFF”
|
| nRF5340 Revision 1 v1.5 |
04.11.2022 |
- Added: No. 158. “Using POWER register clears RADIO trim values ”
|
| nRF5340 Revision 1 v1.4 |
06.09.2022 |
- Added: No. 152. “Incorrect value for I_S10”
- Added: No. 153. “GPIOTE with low-power latency setting does not register IN events in System ON IDLE”
- Added: No. 154. “WLCSP package dimension L is incorrect”
|
| nRF5340 Rev 1 v1.3 |
10.02.2022 |
- Added: No. 140. “Soft reset during LFRC calibration prevents watchdog reset and LFCLK from being started”
|
| nRF5340 Rev 1 v1.2 |
03.12.2021 |
- Added: No. 133. “Degraded radio performance with QSPI”
- Added: No. 135. “No output from SPIM4”
- Added: No. 136. “QSPI has limited supply voltage range”
- Added: No. 137. “LFRC calibration is not performed”
|
| nRF5340 Rev 1 v1.1 |
22.10.2021 |
- Added: No. 134. “Incorrect value for IRADIO_TX3”
- Added: No. 138. “LPCOMP consumes additional current”
|
| nRF5340 Rev1 v1.0 |
03.12.2020 |
- Added: No. 6. “Disabling instruction cache causes skip of next instruction”
- Added: No. 43. “Reading QSPI registers after XIP might halt application CPU”
- Added: No. 44. “TASKS_RESUME impacts UARTE”
- Added: No. 47. “I2C timing spec is violated at 400 kHz”
- Added: No. 55. “Bits in RESETREAS are set when they should not be”
- Added: No. 65. “Events are not generated when switching from scan mode to
no-scan mode with BURST disabled”
- Added: No. 70. “Event FIELDDETECTED may be generated too early”
- Added: No. 71. “Frame delay timing is too short after SLP_REQ”
- Added: No. 75. “False SEQEND[0] and SEQEND[1] events are generated”
- Added: No. 76. “Non-secure code can detect secure events”
- Added: No. 87. “RSSI parameter adjustment”
- Added: No. 99. “Mode 3 is not functional at 96 MHz”
- Added: No. 112. “24-bit sample in a 32-bit half-frame is received incorrectly”
- Added: No. 113. “Reading DTX in MODECNF0 gives incorrect value”
- Added: No. 117. “Changing MODE requires additional configuration”
- Added: No. 119. “Writes to LATCH register take several CPU cycles to take
effect”
- Added: No. 121. “Configuration of peripheral requires additional steps”
- Added: No. 122. “Successive triggering of CTRLAP.ERASEALL has no effect”
|