6 |
Network |
NVMC |
Disabling instruction cache causes skip of next instruction
|
|
X |
43 |
Application |
QSPI |
Reading QSPI registers after XIP might halt application CPU
|
|
X |
44 |
Application, Network |
UARTE |
TASKS_RESUME impacts UARTE
|
|
X |
47 |
Application, Network |
TWIM |
I2C timing spec is violated at 400 kHz
|
|
X |
55 |
Application, Network |
RESET |
Bits in RESETREAS are set when they should not be
|
|
X |
65 |
Application |
SAADC |
Events are not generated when switching from scan mode to no-scan mode with BURST disabled
|
|
X |
70 |
Application |
NFCT |
Event FIELDDETECTED may be generated too early
|
|
X |
71 |
Application |
NFCT |
Frame delay timing is too short after SLP_REQ
|
|
X |
75 |
Application |
PWM |
False SEQEND[0] and SEQEND[1] events are generated
|
|
X |
76 |
Application |
DPPI |
Non-secure code can detect secure events
|
|
X |
87 |
Network |
RADIO |
RSSI parameter adjustment
|
|
X |
99 |
Application |
QSPI |
Mode 3 is not functional at 96 MHz
|
X |
|
112 |
Application |
I2S |
24-bit sample in a 32-bit half-frame is received incorrectly
|
X |
|
113 |
Network |
RADIO |
Reading DTX in MODECNF0 gives incorrect value
|
|
X |
117 |
Network |
RADIO |
Changing MODE requires additional configuration
|
|
X |
119 |
Network |
GPIO |
Writes to LATCH register take several CPU cycles to take effect
|
|
X |
121 |
Application |
QSPI |
Configuration of peripheral requires additional steps
|
X |
|
122 |
Network |
CTRL-AP |
Successive triggering of CTRLAP.ERASEALL has no effect
|
X |
|