Revision history

See the following list for an overview of changes from previous versions of this document.

Version Date Change
nRF5340 Engineering D v1.0 03.12.2020
  • Added: No. 6. “Disabling instruction cache causes skip of next instruction”
  • Added: No. 43. “Reading QSPI registers after XIP might halt application CPU”
  • Added: No. 44. “TASKS_RESUME impacts UARTE”
  • Added: No. 47. “I2C timing spec is violated at 400 kHz”
  • Added: No. 55. “Bits in RESETREAS are set when they should not be”
  • Added: No. 65. “Events are not generated when switching from scan mode to no-scan mode with BURST disabled”
  • Added: No. 70. “Event FIELDDETECTED may be generated too early”
  • Added: No. 71. “Frame delay timing is too short after SLP_REQ”
  • Added: No. 75. “False SEQEND[0] and SEQEND[1] events are generated”
  • Added: No. 76. “Non-secure code can detect secure events”
  • Added: No. 87. “RSSI parameter adjustment”
  • Added: No. 99. “Mode 3 is not functional at 96 MHz”
  • Added: No. 112. “24-bit sample in a 32-bit half-frame is received incorrectly”
  • Added: No. 113. “Reading DTX in MODECNF0 gives incorrect value”
  • Added: No. 117. “Changing MODE requires additional configuration”
  • Added: No. 119. “Writes to LATCH register take several CPU cycles to take effect”
  • Added: No. 121. “Configuration of peripheral requires additional steps”
  • Added: No. 122. “Successive triggering of CTRLAP.ERASEALL has no effect”