The anomalies listed in this table are no longer present in the current chip version.
For a detailed description of the fixed anomalies, see the Errata for revision Revision 1.
| ID | Module | Description |
|---|---|---|
| 192 | CLOCK | LFRC frequency offset after calibration |
| 197 | POWER | DCDC of REG0 not functional |
| 201 | CLOCK | EVENTS_HFCLKSTARTED might be generated twice |
| 202 | POWER | Device does not start up in high voltage mode |