This anomaly applies to IC Rev. Engineering C, build codes CKAA-CA0, QIAA-CA0.
The erase or write operation fails or takes longer time than specified.
NVMC erase or write operation initiated using an external debugger. CPU is not halted.
The NVMC erase or write operation fails or takes longer time than specified.
Halt the CPU by writing to DHCSR (Debug Halting Control and Status Register) before starting NVMC erase or write operation from the external debugger. See the ARM infocenter to get the details of the DHCSR register.
Programming tools provided by Nordic Semiconductor comply with this.