This anomaly applies to Revision 3, build codes QFAA-Gx0, QFAB-Gx0, CIAA-Gx0.
It was inherited from the previous IC revision
Revision 2.
Symptoms
CPU does not resume execution.
Conditions
The following conditions are present:
- CPU enters IDLE state between 32 to 48 16 MHz clock cycles before SPIM END event.
- SPIM is the only peripheral preventing System ON IDLE state.
- CPU is configured to resume execution after SPIM END event.
- PPI channels are not configured on the SPIM END event.
- SPIM END_START shortcut is not enabled.
- Constant Latency mode is not enabled.
Consequences
CPU does not execute.
Workaround
Connect the SPIM END event to an available PPI channel. The PPI channel does not have to be connected to a task end point.