15 |
POWER |
RAM[x].POWERSET/CLR read as zero
|
X |
20 |
RTC |
Register values are invalid
|
X |
31 |
CLOCK |
Calibration values are not correctly loaded from FICR at reset
|
X |
36 |
CLOCK |
Some registers are not reset when expected
|
X |
66 |
TEMP |
Linearity specification not met with default settings
|
X |
68 |
CLOCK |
EVENTS_HFCLKSTARTED can be generated before HFCLK is stable
|
X |
77 |
CLOCK |
RC oscillator is not calibrated when first started
|
X |
78 |
TIMER |
High current consumption when using timer STOP task only
|
X |
81 |
GPIO |
PIN_CNF is not retained when in debug interface mode
|
X |
83 |
TWIS |
STOPPED event occurs twice if the STOP task is triggered during a transaction
|
X |
88 |
WDT |
Increased current consumption when configured to pause in System ON idle
|
X |
136 |
System |
Bits in RESETREAS are set when they should not be
|
X |
155 |
GPIOTE |
IN event may occur more than once on input edge
|
X |
156 |
GPIOTE |
Some CLR tasks give unintentional behavior
|
X |
173 |
GPIO |
Writes to LATCH register take several CPU cycles to take effect
|
X |
176 |
System |
Flash erase through CTRL-AP fails due to watchdog time-out
|
X |
179 |
RTC |
COMPARE event is generated twice from a single RTC compare match
|
X |
183 |
PWM |
False SEQEND[0] and SEQEND[1] events
|
X |
184 |
NVMC |
Erase or write operations from the external debugger fail when CPU is not halted
|
X |
204 |
RADIO |
Switching between TX and RX causes unwanted emissions
|
X |
210 |
GPIO |
Bits in GPIO LATCH register are incorrectly set to 1
|
X |
212 |
SAADC |
Events are not generated when switching from scan mode to no-scan mode with burst enabled
|
X |
213 |
WDT |
WDT configuration is cleared when entering system OFF
|
X |
219 |
TWIM |
I2C timing spec is violated at 400 kHz
|
X |
237 |
SAADC |
TASKS_CALIBRATEOFFSET shall only be used before TASKS_START or after EVENTS_END
|
X |
241 |
SAADC |
Static 400 µA current after SAADC is disabled
|
X |
242 |
NVMC |
NVMC operations during POFWARN cause the CPU to hang
|
X |
245 |
RADIO |
CRC is wrong when data whitening is enabled and address field is included in CRC calculation
|
X |
246 |
System |
Intermittent extra current consumption when going to sleep
|
X |
252 |
SAADC |
Unexpected behavior when TASKS_CALIBRATEOFFSET is used during sampling
|
X |
262 |
POWER |
CPU does not resume execution after CPU IDLE
|
X |