| nRF52810 Revision 2 v1.5 |
05.06.2023 |
- Added: No. 241. “Static 400 µA current after SAADC is disabled”
- Added: No. 262. “CPU does not resume execution after CPU IDLE”
- Updated: No. 246. “Intermittent extra current consumption when going to sleep”
|
| nRF52810 Revision 2 v1.4 |
09.02.2022 |
- Added: No. 204. “Switching between TX and RX causes unwanted emissions”
- Added: No. 252. “Unexpected behavior when TASKS_CALIBRATEOFFSET is used during sampling”
|
| nRF52810 Revision 2 v1.3 |
09.11.2020 |
- Added: No. 242. “NVMC operations during POFWARN cause the CPU to hang”
- Added: No. 245. “CRC is wrong when data whitening is enabled and address field is included in CRC calculation”
- Added: No. 246. “Intermittent extra current consumption when going to sleep”
|
| nRF52810 Revision 2 v1.2 |
10.07.2020 |
- Added: No. 78. “High current consumption when using timer STOP task only”
- Added: No. 212. “Events are not generated when switching from scan mode to
no-scan mode with burst enabled”
- Added: No. 237. “TASKS_CALIBRATEOFFSET shall only be used before TASKS_START
or after EVENTS_END”
|
| nRF52810 Rev 2 v1.1 |
12.09.2019 |
- Updated: No. 156. “Some CLR tasks give unintentional behavior”
- Added: No. 213. “WDT configuration is cleared when entering system OFF”
- Added: No. 219. “I2C timing spec is violated at 400 kHz”
|
| nRF52810 Rev 2 v1.0 |
31.01.2019 |
- Added: No. 15. “RAM[x].POWERSET/CLR read as zero”
- Added: No. 20. “Register values are invalid”
- Added: No. 31. “Calibration values are not correctly loaded from FICR at
reset”
- Added: No. 36. “Some registers are not reset when expected”
- Added: No. 66. “Linearity specification not met with default settings”
- Added: No. 68. “EVENTS_HFCLKSTARTED can be generated before HFCLK is stable”
- Added: No. 77. “RC oscillator is not calibrated when first started”
- Added: No. 81. “PIN_CNF is not retained when in debug interface mode”
- Added: No. 83. “STOPPED event occurs twice if the STOP task is triggered
during a transaction”
- Added: No. 88. “Increased current consumption when configured to pause in
System ON idle”
- Added: No. 136. “Bits in RESETREAS are set when they should not be”
- Added: No. 155. “IN event may occur more than once on input edge”
- Added: No. 156. “Some CLR tasks give unintentional behavior”
- Added: No. 173. “Writes to LATCH register take several CPU cycles to take
effect”
- Added: No. 176. “Flash erase through CTRL-AP fails due to watchdog time-out”
- Added: No. 179. “COMPARE event is generated twice from a single RTC compare
match”
- Added: No. 183. “False SEQEND[0] and SEQEND[1] events”
- Added: No. 184. “Erase or write operations from the external debugger fail
when CPU is not halted”
- Added: No. 204. “Switching beween TX and RX causes unwanted emissions”
- Added: No. 210. “Bits in GPIO LATCH register are incorrectly set to 1”
|