S130 SDS v2.0: Processor usage patterns for the Flash API

This section describes the processor availability and interrupt processing time for the SoftDevice when the Flash API is being used.

Figure 1. Flash API activity (some priority levels left out for clarity)

When using the Flash API, the pattern of SoftDevice CPU activity at interrupt priority level 0 is as follows:

First, there is an interrupt at priority level 0 that sets up and performs the flash activity. The CPU is halted for most of the time in this interrupt.
After the first interrupt is finished, there is another interrupt at priority level 2 that does some cleanup after the flash operation.

SoftDevice processing activity in the different priority levels during flash erase and write is outlined in the table below.

Table 1. Processor usage for the Flash API
Parameter	Description	Typical	Max
t_{ISR(0),FlashErase}	Interrupt processing when erasing a flash page. Note that the CPU is halted for most of the length of this interrupt.		22.6 ms
t_{ISR(0),FlashWrite}	Interrupt processing when writing one or more words to flash. Note that the CPU is halted for most of the length of this interrupt. The Max time provided is for writing one word. When writing more than one word, please see the Product Specification to find out how long time is needed for per word to write, and add to the Max time provided in this table.		550 μs
t_ISR(2)	Priority level 2 interrupt at the end of flash write or erase.	30 μs

Flash API processor usage patterns