This section gives an overview of interrupt levels used by the SoftDevice, and the interrupt levels that are available for the application.
To implement the SoftDevice API as SuperVisor Calls (SVCs, see Application Programming Interface (API)) and ensure that embedded protocol real-time requirements are met independently of the application processing, the SoftDevice implements an interrupt model where application interrupts and SoftDevice interrupts are interleaved. This model will result in application interrupts being postponed or preempted, leading to longer perceived application interrupt latency and interrupt execution times.
The application must take care to select the correct interrupt priorities for application events according to the guidelines that follow. The NVIC API to the SoC Library supports safe configuration of interrupt priorities from the application.
The ARM® Cortex® -M0 processor has four configurable interrupt priorities ranging from 0 to 3 (with 0 being highest priority). On reset, all interrupts are configured with the highest priority (0).
The SoftDevice reserves and uses the following priority levels, which must remain unused by the application programmer:
The application can use the remaining interrupt priority levels, in addition to the main, or thread, context.
As seen from Figure 1, the application has available priority level 1, located between the priority levels reserved by the SoftDevice. This enables a low-latency application interrupt to support fast sensor interfaces. An application interrupt at this priority will only experience latency from SoftDevice interrupts at priority level 0, while application interrupts at priority level 3 can experience latency from both SoftDevice priority levels in addition to its own priority level 1 interrupts.
Figure 2 shows an example of how interrupts with different priorities may run and preemt each other.