nrf_mesh_config_core.h

/* Copyright (c) 2010 - 2017, Nordic Semiconductor ASA
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *
 * 1. Redistributions of source code must retain the above copyright notice, this
 * list of conditions and the following disclaimer.
 *
 * 2. Redistributions in binary form, except as embedded into a Nordic
 * Semiconductor ASA integrated circuit in a product or a software update for
 * such product, must reproduce the above copyright notice, this list of
 * conditions and the following disclaimer in the documentation and/or other
 * materials provided with the distribution.
 *
 * 3. Neither the name of Nordic Semiconductor ASA nor the names of its
 * contributors may be used to endorse or promote products derived from this
 * software without specific prior written permission.
 *
 * 4. This software, with or without modification, must only be used with a
 * Nordic Semiconductor ASA integrated circuit.
 *
 * 5. Any software provided in binary form under this license must not be reverse
 * engineered, decompiled, modified and/or disassembled.
 *
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 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef NRF_MESH_CONFIG_CORE_H__
#define NRF_MESH_CONFIG_CORE_H__

#include "nrf_mesh_defines.h"

#ifndef PERSISTENT_STORAGE
#define PERSISTENT_STORAGE 1
#endif

#ifndef NRF_MESH_UECC_ENABLE
#define NRF_MESH_UECC_ENABLE 1
#endif

#ifndef AES_USE_HARDWARE
#define AES_USE_HARDWARE 1
#endif

#ifndef CORE_TX_QUEUE_BUFFER_SIZE_ORIGINATOR
#define CORE_TX_QUEUE_BUFFER_SIZE_ORIGINATOR 256
#endif

#ifndef CORE_TX_QUEUE_BUFFER_SIZE_RELAY
#define CORE_TX_QUEUE_BUFFER_SIZE_RELAY 128
#endif

#ifndef CORE_TX_QUEUE_BUFFER_SIZE_INSTABURST_ORIGINATOR
#define CORE_TX_QUEUE_BUFFER_SIZE_INSTABURST_ORIGINATOR 4096
#endif

#ifndef CORE_TX_QUEUE_BUFFER_SIZE_INSTABURST_RELAY
#define CORE_TX_QUEUE_BUFFER_SIZE_INSTABURST_RELAY 2048
#endif

#ifndef CORE_TX_INSTABURST_CHANNELS
#define CORE_TX_INSTABURST_CHANNELS \
 {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, \
 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36}
#endif

#ifndef CORE_TX_REPEAT_ORIGINATOR_DEFAULT
#define CORE_TX_REPEAT_ORIGINATOR_DEFAULT 1
#endif

#ifndef CORE_TX_REPEAT_RELAY_DEFAULT
#define CORE_TX_REPEAT_RELAY_DEFAULT 1
#endif

#ifndef CCM_DEBUG_MODE_ENABLED
#define CCM_DEBUG_MODE_ENABLED 0
#endif

#ifndef FIFO_STATS
#define FIFO_STATS 0
#endif

#ifndef INTERNAL_EVT_ENABLE
#define INTERNAL_EVT_ENABLE 1
#endif

#ifndef INTERNAL_EVENT_BUFFER_SIZE
#define INTERNAL_EVENT_BUFFER_SIZE 32
#endif

#ifndef NRF_MESH_LOG_ENABLE
#define NRF_MESH_LOG_ENABLE 1
#endif

#ifndef LOG_LEVEL_DEFAULT
#define LOG_LEVEL_DEFAULT LOG_LEVEL_WARN
#endif

#ifndef LOG_MSK_DEFAULT
#define LOG_MSK_DEFAULT LOG_GROUP_STACK
#endif

#ifndef LOG_ENABLE_RTT
#define LOG_ENABLE_RTT 1
#endif

#ifndef LOG_CALLBACK_DEFAULT
#if defined(NRF51) || defined(NRF52_SERIES)
 #define LOG_CALLBACK_DEFAULT log_callback_rtt
#else
 #define LOG_CALLBACK_DEFAULT log_callback_stdout
#endif
#endif

#ifndef MSG_CACHE_ENTRY_COUNT
#define MSG_CACHE_ENTRY_COUNT 32
#endif

#ifndef NETWORK_SEQNUM_IV_UPDATE_START_THRESHOLD
#define NETWORK_SEQNUM_IV_UPDATE_START_THRESHOLD (NETWORK_SEQNUM_MAX / 2)
#endif

#ifndef NETWORK_SEQNUM_IV_UPDATE_END_THRESHOLD
#define NETWORK_SEQNUM_IV_UPDATE_END_THRESHOLD (NETWORK_SEQNUM_MAX - TRANSPORT_SAR_SEQNUM_DIFF_MAX)
#endif

/* Sanity check for NETWORK_SEQNUM_IV_UPDATE_END_THRESHOLD */
#if NETWORK_SEQNUM_IV_UPDATE_START_THRESHOLD > NETWORK_SEQNUM_IV_UPDATE_END_THRESHOLD
#error "The network sequence number start threshold must be lower than the end threshold."
#endif
#if NETWORK_SEQNUM_IV_UPDATE_END_THRESHOLD > (NETWORK_SEQNUM_MAX - TRANSPORT_SAR_SEQNUM_DIFF_MAX)
#error "The network sequence number IV update threshold must be low enough to fit a full SAR session."
#endif

#ifndef NETWORK_SEQNUM_FLASH_BLOCK_SIZE
#define NETWORK_SEQNUM_FLASH_BLOCK_SIZE 8192
#endif

#ifndef NETWORK_SEQNUM_FLASH_BLOCK_THRESHOLD
#define NETWORK_SEQNUM_FLASH_BLOCK_THRESHOLD 64
#endif

#ifndef NET_FLASH_PAGE_COUNT
#define NET_FLASH_PAGE_COUNT 1
#endif

#ifndef TRANSPORT_SAR_SESSIONS_MAX
#define TRANSPORT_SAR_SESSIONS_MAX (4)
#endif

#ifndef TRANSPORT_SAR_RX_CACHE_LEN
#define TRANSPORT_SAR_RX_CACHE_LEN (8)
#endif

#ifndef TRANSPORT_SAR_SEGACK_TTL_DEFAULT
#define TRANSPORT_SAR_SEGACK_TTL_DEFAULT (8)
#endif

#ifndef PACKET_MGR_DEBUG_MODE
#define PACKET_MGR_DEBUG_MODE 0
#endif


#ifndef PACKET_MGR_MEMORY_POOL_SIZE
#define PACKET_MGR_MEMORY_POOL_SIZE 4096
#endif

#ifndef PACKET_MGR_BLAME_MODE
#define PACKET_MGR_BLAME_MODE 0
#endif

#ifndef PACKET_BUFFER_DEBUG_MODE
#define PACKET_BUFFER_DEBUG_MODE 0
#endif

#ifndef REPLAY_CACHE_ENTRIES
#define REPLAY_CACHE_ENTRIES 32
#endif

#ifndef FLASH_MANAGER_PAGE_COUNT_MAX
#define FLASH_MANAGER_PAGE_COUNT_MAX 255
#endif

#ifndef FLASH_MANAGER_POOL_SIZE
#define FLASH_MANAGER_POOL_SIZE 256
#endif

#ifndef FLASH_MANAGER_ENTRY_MAX_SIZE
#define FLASH_MANAGER_ENTRY_MAX_SIZE 128
#endif

#endif