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nRF5 Getting Started
  Product development with nRF5 Series SoCs
    Available protocols
    Nordic tools and downloads
    Software development
    Hardware design
    Hardware testing
    Product certification
    Production programming and testing
  Software development Getting Started Guides
    nRF5 Series: Developing with SEGGER Embedded Studio
      Revision history
      Minimum requirements
      Related documentation
      Development kits, boards, and chips
      SoftDevices
      Running a first test
      Setting up your toolchain
        Nordic tools and downloads
        Setting up the nRF5 SDK
        Installing SEGGER tools
        Installing the nRF5x Command Line Tools
      Programming an application
        Erasing the board
        Importing Keil projects
        Compiling the application
        Configuring placement of the SoftDevice
        Programming the firmware
        Adding files
          Adding source files
          Including header files
      Communicating with the board
        Connecting via RTT
          Connecting via RTT on Windows
          Connecting via RTT on Linux
        Connecting via CDC-UART
      Testing the application
        Testing with a mobile device
        Testing with a computer
      Debugging
      Glossary
        DK (Development Kit)
        GNU Compiler Collection (GCC)
        Integrated Development Environment (IDE)
        Real Time Transfer (RTT)
        SEGGER Embedded Studio (SES)
        SoftDevice
        System on Chip (SoC)
        Target
        Universal Asynchronous Receiver/Transmitter (UART)
      Acronyms and abbreviations
      Legal notices
    nRF5 Series: Developing on Windows with ARM Keil MDK
      Revision history
      Minimum requirements
      Related documentation
      Development kits, boards, and chips
      SoftDevices
      Running a first test
      Setting up your toolchain
        Nordic tools and downloads
        Installing the ARM Keil MDK
        Setting up the nRF5 SDK
        Installing the nRF5x Command Line Tools
        Installing nRFgo Studio
      Programming an application
        Erasing the board
        Compiling the application
        Programming the SoftDevice
        Programming the application
      Communicating with the board
        Connecting via RTT
        Connecting via CDC-UART
      Testing the application
        Testing with a mobile device
        Testing with a computer
      Debugging
      Glossary
        DK (Development Kit)
        Device Family Pack
        GNU Compiler Collection (GCC)
        Integrated Development Environment (IDE)
        Real Time Transfer (RTT)
        SEGGER Embedded Studio (SES)
        SoftDevice
        System on Chip (SoC)
        Target
        Universal Asynchronous Receiver/Transmitter (UART)
      Acronyms and abbreviations
      Legal notices
  Product development with nRF5 Series SoCs
    Available protocols
    Nordic tools and downloads
    Software development
    Hardware design
    Hardware testing
    Product certification
    Production programming and testing
  Software development Getting Started Guides
    nRF5 Series: Developing with SEGGER Embedded Studio
      Revision history
      Minimum requirements
      Related documentation
      Development kits, boards, and chips
      SoftDevices
      Running a first test
      Setting up your toolchain
        Nordic tools and downloads
        Setting up the nRF5 SDK
        Installing SEGGER tools
        Installing the nRF5x Command Line Tools
      Programming an application
        Erasing the board
        Importing Keil projects
        Compiling the application
        Configuring placement of the SoftDevice
        Programming the firmware
        Adding files
          Adding source files
          Including header files
      Communicating with the board
        Connecting via RTT
          Connecting via RTT on Windows
          Connecting via RTT on Linux
        Connecting via CDC-UART
      Testing the application
        Testing with a mobile device
        Testing with a computer
      Debugging
      Glossary
        DK (Development Kit)
        GNU Compiler Collection (GCC)
        Integrated Development Environment (IDE)
        Real Time Transfer (RTT)
        SEGGER Embedded Studio (SES)
        SoftDevice
        System on Chip (SoC)
        Target
        Universal Asynchronous Receiver/Transmitter (UART)
      Acronyms and abbreviations
      Legal notices
    nRF5 Series: Developing on Windows with ARM Keil MDK
      Revision history
      Minimum requirements
      Related documentation
      Development kits, boards, and chips
      SoftDevices
      Running a first test
      Setting up your toolchain
        Nordic tools and downloads
        Installing the ARM Keil MDK
        Setting up the nRF5 SDK
        Installing the nRF5x Command Line Tools
        Installing nRFgo Studio
      Programming an application
        Erasing the board
        Compiling the application
        Programming the SoftDevice
        Programming the application
      Communicating with the board
        Connecting via RTT
        Connecting via CDC-UART
      Testing the application
        Testing with a mobile device
        Testing with a computer
      Debugging
      Glossary
        DK (Development Kit)
        Device Family Pack
        GNU Compiler Collection (GCC)
        Integrated Development Environment (IDE)
        Real Time Transfer (RTT)
        SEGGER Embedded Studio (SES)
        SoftDevice
        System on Chip (SoC)
        Target
        Universal Asynchronous Receiver/Transmitter (UART)
      Acronyms and abbreviations
      Legal notices
nRF91 Series
  nRF9160
    nRF9160 Product Specification
      Revision history
      About this document
        Document status
        Peripheral chapters
        Register tables
          Fields and values
          Permissions
        Registers
          DUMMY
      Product overview
        Introduction
        Block diagram
        Peripheral interface
          Peripheral ID
          Peripherals with shared ID
          Peripheral registers
          Bit set and clear
          Tasks
          Events
          Publish / Subscribe
          Shortcuts
          Interrupts
          Secure/non-secure peripherals
      Application core
        CPU
          CPU and support module configuration
          Electrical specification
            CPU performance
        Memory
          Memory map
          Instantiation
          Peripheral access control capabilities
        VMC — Volatile memory controller
          Registers
            RAM[n].POWER
            RAM[n].POWERSET
            RAM[n].POWERCLR
        NVMC — Non-volatile memory controller
          Writing to flash
          Erasing a secure page in flash
          Erasing a non-secure page in flash
          Writing to user information configuration registers (UICR)
          Erase all
          NVMC protection mechanisms
            NVMC blocking
            NVMC power failure protection
          Cache
          Registers
            READY
            READYNEXT
            CONFIG
            ERASEALL
            ERASEPAGEPARTIALCFG
            ICACHECNF
            IHIT
            IMISS
            CONFIGNS
            WRITEUICRNS
          Electrical specification
            Flash programming
            Cache size
        FICR — Factory information configuration registers
          Registers
            INFO.DEVICEID[n]
            INFO.PART
            INFO.VARIANT
            INFO.PACKAGE
            INFO.RAM
            INFO.FLASH
            INFO.CODEPAGESIZE
            INFO.CODESIZE
            INFO.DEVICETYPE
            TRIMCNF[n].ADDR
            TRIMCNF[n].DATA
            TRNG90B.BYTES
            TRNG90B.RCCUTOFF
            TRNG90B.APCUTOFF
            TRNG90B.STARTUP
            TRNG90B.ROSC1
            TRNG90B.ROSC2
            TRNG90B.ROSC3
            TRNG90B.ROSC4
        UICR — User information configuration registers
          Registers
            APPROTECT
            XOSC32M
            HFXOSRC
            HFXOCNT
            SECUREAPPROTECT
            ERASEPROTECT
            OTP[n]
            KEYSLOT.CONFIG[n].DEST
            KEYSLOT.CONFIG[n].PERM
            KEYSLOT.KEY[n].VALUE[o]
        EasyDMA
          EasyDMA error handling
          EasyDMA array list
        AHB multilayer interconnect
      Power and clock management
        Functional description
          Power management
            System ON mode
            System OFF mode
              Emulated System OFF mode
          Power supply
            General purpose I/O supply
          Power supply monitoring
            Power supply supervisor
            Battery monitoring on VDD
            Electrical specification
              Device startup times
              Power supply supervisor
          Clock management
            HFCLK clock controller
            LFCLK clock controller
              32.768 kHz RC oscillator (LFRC)
            Electrical specification
              64 MHz internal oscillator (HFINT)
               64 MHz high accuracy oscillator (HFXO)
              32.768 kHz high accuracy oscillator (LFXO)
              32.768 kHz RC oscillator (LFRC)
          Reset
            Power-on reset
            Pin reset
            Wakeup from System OFF mode reset
            Soft reset
            Watchdog reset
            Brownout reset
            Retained registers
            Reset behavior
            Electrical specification
              Pin reset
        Current consumption
          Electrical specification
            Sleep
            Application CPU active current consumption
            I2S
            PDM
            PWM
            SAADC
            TIMER
            SPIM
            SPIS
            TWIM
            TWIS
            UARTE
            WDT
            Modem current consumption
            GPS current consumption
        Register description
          POWER — Power control
            Registers
              TASKS_CONSTLAT
              TASKS_LOWPWR
              SUBSCRIBE_CONSTLAT
              SUBSCRIBE_LOWPWR
              EVENTS_POFWARN
              EVENTS_SLEEPENTER
              EVENTS_SLEEPEXIT
              PUBLISH_POFWARN
              PUBLISH_SLEEPENTER
              PUBLISH_SLEEPEXIT
              INTEN
              INTENSET
              INTENCLR
              RESETREAS
              POWERSTATUS
              GPREGRET[n]
          CLOCK — Clock control
            Registers
              TASKS_HFCLKSTART
              TASKS_HFCLKSTOP
              TASKS_LFCLKSTART
              TASKS_LFCLKSTOP
              SUBSCRIBE_HFCLKSTART
              SUBSCRIBE_HFCLKSTOP
              SUBSCRIBE_LFCLKSTART
              SUBSCRIBE_LFCLKSTOP
              EVENTS_HFCLKSTARTED
              EVENTS_LFCLKSTARTED
              PUBLISH_HFCLKSTARTED
              PUBLISH_LFCLKSTARTED
              INTEN
              INTENSET
              INTENCLR
              INTPEND
              HFCLKRUN
              HFCLKSTAT
              LFCLKRUN
              LFCLKSTAT
              LFCLKSRCCOPY
              LFCLKSRC
          REGULATORS — Voltage regulators control
            Registers
              SYSTEMOFF
              DCDCEN
      Peripherals
        CRYPTOCELL — ARM TrustZone CryptoCell 310
          Usage
          Always-on (AO) power domain
          Lifecycle state (LCS)
          Cryptographic key selection
            RTL key
            Device root key
          Direct memory access (DMA)
          Standards
          Registers
            ENABLE
          Host interface
            HOST_RGF block
              Registers
                HOST_CRYPTOKEY_SEL
                HOST_IOT_KPRTL_LOCK
                HOST_IOT_KDR0
                HOST_IOT_KDR1
                HOST_IOT_KDR2
                HOST_IOT_KDR3
                HOST_IOT_LCS
        DPPI - Distributed programmable peripheral interconnect
          Subscribing to and publishing on channels
          DPPI configuration (DPPIC)
          Connection examples
          Special considerations for a system implementing TrustZone for Cortex-M processors
          Registers
            TASKS_CHG[n].EN
            TASKS_CHG[n].DIS
            SUBSCRIBE_CHG[n].EN
            SUBSCRIBE_CHG[n].DIS
            CHEN
            CHENSET
            CHENCLR
            CHG[n]
        EGU — Event generator unit
          Registers
            TASKS_TRIGGER[n]
            SUBSCRIBE_TRIGGER[n]
            EVENTS_TRIGGERED[n]
            PUBLISH_TRIGGERED[n]
            INTEN
            INTENSET
            INTENCLR
          Electrical specification
            EGU Electrical Specification
        GPIO — General purpose input/output
          Pin configuration
          Pin sense mechanism
          GPIO security
          Registers
            OUT ( Retained )
            OUTSET
            OUTCLR
            IN
            DIR ( Retained )
            DIRSET
            DIRCLR
            LATCH ( Retained )
            DETECTMODE ( Retained )
            DETECTMODE_SEC ( Retained )
            PIN_CNF[n]
          Electrical specification
            GPIO Electrical Specification
        GPIOTE — GPIO tasks and events
          Pin events and tasks
          Port event
          Tasks and events pin configuration
          Registers
            TASKS_OUT[n]
            TASKS_SET[n]
            TASKS_CLR[n]
            SUBSCRIBE_OUT[n]
            SUBSCRIBE_SET[n]
            SUBSCRIBE_CLR[n]
            EVENTS_IN[n]
            EVENTS_PORT
            PUBLISH_IN[n]
            PUBLISH_PORT
            INTENSET
            INTENCLR
            CONFIG[n]
          Electrical specification
        IPC — Interprocessor communication
          IPC and PPI connections
          Registers
            TASKS_SEND[n]
            SUBSCRIBE_SEND[n]
            EVENTS_RECEIVE[n]
            PUBLISH_RECEIVE[n]
            INTEN
            INTENSET
            INTENCLR
            INTPEND
            SEND_CNF[n]
            RECEIVE_CNF[n]
            GPMEM[n]
          Electrical specification
            IPC Electrical Specification
        I2S — Inter-IC sound interface
          Mode
          Transmitting and receiving
          Left right clock (LRCK)
          Serial clock (SCK)
          Master clock (MCK)
          Width, alignment and format
          EasyDMA
          Module operation
          Pin configuration
          Registers
            TASKS_START
            TASKS_STOP
            SUBSCRIBE_START
            SUBSCRIBE_STOP
            EVENTS_RXPTRUPD
            EVENTS_STOPPED
            EVENTS_TXPTRUPD
            PUBLISH_RXPTRUPD
            PUBLISH_STOPPED
            PUBLISH_TXPTRUPD
            INTEN
            INTENSET
            INTENCLR
            ENABLE
            CONFIG.MODE
            CONFIG.RXEN
            CONFIG.TXEN
            CONFIG.MCKEN
            CONFIG.MCKFREQ
            CONFIG.RATIO
            CONFIG.SWIDTH
            CONFIG.ALIGN
            CONFIG.FORMAT
            CONFIG.CHANNELS
            RXD.PTR
            TXD.PTR
            RXTXD.MAXCNT
            PSEL.MCK
            PSEL.SCK
            PSEL.LRCK
            PSEL.SDIN
            PSEL.SDOUT
          Electrical specification
            I2S timing specification
        KMU — Key management unit
          Functional view
          Access control
          Protecting the UICR content
          Usage
            OTP
            Key storage
              Selecting a key slot
              Writing to a key slot
              Reading a key value
              Push over secure APB
              Revoking the key slots
            STATUS register
          Registers
            TASKS_PUSH_KEYSLOT
            EVENTS_KEYSLOT_PUSHED
            EVENTS_KEYSLOT_REVOKED
            EVENTS_KEYSLOT_ERROR
            INTEN
            INTENSET
            INTENCLR
            INTPEND
            STATUS
            SELECTKEYSLOT
        PDM — Pulse density modulation interface
          Master clock generator
          Module operation
          Decimation filter
          EasyDMA
          Hardware example
          Pin configuration
          Registers
            TASKS_START
            TASKS_STOP
            SUBSCRIBE_START
            SUBSCRIBE_STOP
            EVENTS_STARTED
            EVENTS_STOPPED
            EVENTS_END
            PUBLISH_STARTED
            PUBLISH_STOPPED
            PUBLISH_END
            INTEN
            INTENSET
            INTENCLR
            ENABLE
            PDMCLKCTRL
            MODE
            GAINL
            GAINR
            RATIO
            PSEL.CLK
            PSEL.DIN
            SAMPLE.PTR
            SAMPLE.MAXCNT
          Electrical specification
            PDM Electrical Specification
        PWM — Pulse width modulation
          Wave counter
          Decoder with EasyDMA
          Limitations
          Pin configuration
          Registers
            TASKS_STOP
            TASKS_SEQSTART[n]
            TASKS_NEXTSTEP
            SUBSCRIBE_STOP
            SUBSCRIBE_SEQSTART[n]
            SUBSCRIBE_NEXTSTEP
            EVENTS_STOPPED
            EVENTS_SEQSTARTED[n]
            EVENTS_SEQEND[n]
            EVENTS_PWMPERIODEND
            EVENTS_LOOPSDONE
            PUBLISH_STOPPED
            PUBLISH_SEQSTARTED[n]
            PUBLISH_SEQEND[n]
            PUBLISH_PWMPERIODEND
            PUBLISH_LOOPSDONE
            SHORTS
            INTEN
            INTENSET
            INTENCLR
            ENABLE
            MODE
            COUNTERTOP
            PRESCALER
            DECODER
            LOOP
            SEQ[n].PTR
            SEQ[n].CNT
            SEQ[n].REFRESH
            SEQ[n].ENDDELAY
            PSEL.OUT[n]
        RTC — Real-time counter
          Clock source
          Resolution versus overflow and the prescaler
          Counter register
          Overflow
          Tick event
          Event control
          Compare
          Task and event jitter/delay
          Reading the counter register
          Registers
            TASKS_START
            TASKS_STOP
            TASKS_CLEAR
            TASKS_TRIGOVRFLW
            SUBSCRIBE_START
            SUBSCRIBE_STOP
            SUBSCRIBE_CLEAR
            SUBSCRIBE_TRIGOVRFLW
            EVENTS_TICK
            EVENTS_OVRFLW
            EVENTS_COMPARE[n]
            PUBLISH_TICK
            PUBLISH_OVRFLW
            PUBLISH_COMPARE[n]
            INTENSET
            INTENCLR
            EVTEN
            EVTENSET
            EVTENCLR
            COUNTER
            PRESCALER
            CC[n]
          Electrical specification
        SAADC — Successive approximation analog-to-digital converter
          Overview
          Digital output
          Analog inputs and channels
          Operation modes
            One-shot mode
            Continuous mode
            Oversampling
            Scan mode
          EasyDMA
          Resistor ladder
          Reference
          Acquisition time
          Limits event monitoring
          Registers
            TASKS_START
            TASKS_SAMPLE
            TASKS_STOP
            TASKS_CALIBRATEOFFSET
            SUBSCRIBE_START
            SUBSCRIBE_SAMPLE
            SUBSCRIBE_STOP
            SUBSCRIBE_CALIBRATEOFFSET
            EVENTS_STARTED
            EVENTS_END
            EVENTS_DONE
            EVENTS_RESULTDONE
            EVENTS_CALIBRATEDONE
            EVENTS_STOPPED
            EVENTS_CH[n].LIMITH
            EVENTS_CH[n].LIMITL
            PUBLISH_STARTED
            PUBLISH_END
            PUBLISH_DONE
            PUBLISH_RESULTDONE
            PUBLISH_CALIBRATEDONE
            PUBLISH_STOPPED
            PUBLISH_CH[n].LIMITH
            PUBLISH_CH[n].LIMITL
            INTEN
            INTENSET
            INTENCLR
            STATUS
            ENABLE
            CH[n].PSELP
            CH[n].PSELN
            CH[n].CONFIG
            CH[n].LIMIT
            RESOLUTION
            OVERSAMPLE
            SAMPLERATE
            RESULT.PTR
            RESULT.MAXCNT
            RESULT.AMOUNT
          Electrical specification
            SAADC Electrical Specification
          Performance factors
        SPIM — Serial peripheral interface master with EasyDMA
          SPI master transaction sequence
          Master mode pin configuration
          Shared resources
          EasyDMA
          Low power
          Registers
            TASKS_START
            TASKS_STOP
            TASKS_SUSPEND
            TASKS_RESUME
            SUBSCRIBE_START
            SUBSCRIBE_STOP
            SUBSCRIBE_SUSPEND
            SUBSCRIBE_RESUME
            EVENTS_STOPPED
            EVENTS_ENDRX
            EVENTS_END
            EVENTS_ENDTX
            EVENTS_STARTED
            PUBLISH_STOPPED
            PUBLISH_ENDRX
            PUBLISH_END
            PUBLISH_ENDTX
            PUBLISH_STARTED
            SHORTS
            INTENSET
            INTENCLR
            ENABLE
            PSEL.SCK
            PSEL.MOSI
            PSEL.MISO
            FREQUENCY
            RXD.PTR
            RXD.MAXCNT
            RXD.AMOUNT
            RXD.LIST
            TXD.PTR
            TXD.MAXCNT
            TXD.AMOUNT
            TXD.LIST
            CONFIG
            ORC
          Electrical specification
            SPIM master interface electrical specifications
            Serial Peripheral Interface Master (SPIM) timing specifications
        SPIS — Serial peripheral interface slave with EasyDMA
          Shared resources
          EasyDMA
          SPI slave operation
          Semaphore operation
          Pin configuration
          Registers
            TASKS_ACQUIRE
            TASKS_RELEASE
            SUBSCRIBE_ACQUIRE
            SUBSCRIBE_RELEASE
            EVENTS_END
            EVENTS_ENDRX
            EVENTS_ACQUIRED
            PUBLISH_END
            PUBLISH_ENDRX
            PUBLISH_ACQUIRED
            SHORTS
            INTENSET
            INTENCLR
            SEMSTAT
            STATUS
            ENABLE
            PSEL.SCK
            PSEL.MISO
            PSEL.MOSI
            PSEL.CSN
            PSELSCK ( Deprecated )
            PSELMISO ( Deprecated )
            PSELMOSI ( Deprecated )
            PSELCSN ( Deprecated )
            RXDPTR ( Deprecated )
            MAXRX ( Deprecated )
            AMOUNTRX ( Deprecated )
            RXD.PTR
            RXD.MAXCNT
            RXD.AMOUNT
            RXD.LIST
            TXDPTR ( Deprecated )
            MAXTX ( Deprecated )
            AMOUNTTX ( Deprecated )
            TXD.PTR
            TXD.MAXCNT
            TXD.AMOUNT
            TXD.LIST
            CONFIG
            DEF
            ORC
          Electrical specification
            SPIS slave interface electrical specifications
            Serial Peripheral Interface Slave (SPIS) timing specifications
        SPU - System protection unit
          General concepts
            Special considerations for ARM TrustZone for Cortex-M enabled system
          Flash access control
            Non-secure callable (NSC) region definition in flash
            Flash access error reporting
            UICR and FICR protections
          RAM access control
            Non-secure callable (NSC) region definition in RAM
            RAM access error reporting
          Peripheral access control
            Peripherals with split security
            Peripheral address mapping
            Special considerations for peripherals with DMA master
            Peripheral access error reporting
          Pin access control
            Direct pin control through the GPIO peripheral
          DPPI access control
            Special considerations regarding the DPPIC configuration registers
          External domain access control
          TrustZone for Cortex-M ID allocation
          Registers
            EVENTS_RAMACCERR
            EVENTS_FLASHACCERR
            EVENTS_PERIPHACCERR
            PUBLISH_RAMACCERR
            PUBLISH_FLASHACCERR
            PUBLISH_PERIPHACCERR
            INTEN
            INTENSET
            INTENCLR
            CAP
            EXTDOMAIN[n].PERM
            DPPI[n].PERM
            DPPI[n].LOCK
            GPIOPORT[n].PERM
            GPIOPORT[n].LOCK
            FLASHNSC[n].REGION
            FLASHNSC[n].SIZE
            RAMNSC[n].REGION
            RAMNSC[n].SIZE
            FLASHREGION[n].PERM
            RAMREGION[n].PERM
            PERIPHID[n].PERM
        TIMER — Timer/counter
          Capture
          Compare
          Task delays
          Task priority
          Registers
            TASKS_START
            TASKS_STOP
            TASKS_COUNT
            TASKS_CLEAR
            TASKS_SHUTDOWN ( Deprecated )
            TASKS_CAPTURE[n]
            SUBSCRIBE_START
            SUBSCRIBE_STOP
            SUBSCRIBE_COUNT
            SUBSCRIBE_CLEAR
            SUBSCRIBE_SHUTDOWN ( Deprecated )
            SUBSCRIBE_CAPTURE[n]
            EVENTS_COMPARE[n]
            PUBLISH_COMPARE[n]
            SHORTS
            INTENSET
            INTENCLR
            MODE
            BITMODE
            PRESCALER
            ONESHOTEN[n]
            CC[n]
          Electrical specification
        TWIM — I2C compatible two-wire interface master with EasyDMA
          Shared resources
          EasyDMA
          Master write sequence
          Master read sequence
          Master repeated start sequence
          Low power
          Master mode pin configuration
          Registers
            TASKS_STARTRX
            TASKS_STARTTX
            TASKS_STOP
            TASKS_SUSPEND
            TASKS_RESUME
            SUBSCRIBE_STARTRX
            SUBSCRIBE_STARTTX
            SUBSCRIBE_STOP
            SUBSCRIBE_SUSPEND
            SUBSCRIBE_RESUME
            EVENTS_STOPPED
            EVENTS_ERROR
            EVENTS_SUSPENDED
            EVENTS_RXSTARTED
            EVENTS_TXSTARTED
            EVENTS_LASTRX
            EVENTS_LASTTX
            PUBLISH_STOPPED
            PUBLISH_ERROR
            PUBLISH_SUSPENDED
            PUBLISH_RXSTARTED
            PUBLISH_TXSTARTED
            PUBLISH_LASTRX
            PUBLISH_LASTTX
            SHORTS
            INTEN
            INTENSET
            INTENCLR
            ERRORSRC
            ENABLE
            PSEL.SCL
            PSEL.SDA
            FREQUENCY
            RXD.PTR
            RXD.MAXCNT
            RXD.AMOUNT
            RXD.LIST
            TXD.PTR
            TXD.MAXCNT
            TXD.AMOUNT
            TXD.LIST
            ADDRESS
          Electrical specification
            TWIM interface electrical specifications
            Two Wire Interface Master (TWIM) timing specifications
          Pullup resistor
        TWIS — I2C compatible two-wire interface slave with EasyDMA
          Shared resources
          EasyDMA
          TWI slave responding to a read command
          TWI slave responding to a write command
          Master repeated start sequence
          Terminating an ongoing TWI transaction
          Low power
          Slave mode pin configuration
          Registers
            TASKS_STOP
            TASKS_SUSPEND
            TASKS_RESUME
            TASKS_PREPARERX
            TASKS_PREPARETX
            SUBSCRIBE_STOP
            SUBSCRIBE_SUSPEND
            SUBSCRIBE_RESUME
            SUBSCRIBE_PREPARERX
            SUBSCRIBE_PREPARETX
            EVENTS_STOPPED
            EVENTS_ERROR
            EVENTS_RXSTARTED
            EVENTS_TXSTARTED
            EVENTS_WRITE
            EVENTS_READ
            PUBLISH_STOPPED
            PUBLISH_ERROR
            PUBLISH_RXSTARTED
            PUBLISH_TXSTARTED
            PUBLISH_WRITE
            PUBLISH_READ
            SHORTS
            INTEN
            INTENSET
            INTENCLR
            ERRORSRC
            MATCH
            ENABLE
            PSEL.SCL
            PSEL.SDA
            RXD.PTR
            RXD.MAXCNT
            RXD.AMOUNT
            RXD.LIST
            TXD.PTR
            TXD.MAXCNT
            TXD.AMOUNT
            TXD.LIST
            ADDRESS[n]
            CONFIG
            ORC
          Electrical specification
            TWIS slave timing specifications
        UARTE — Universal asynchronous receiver/transmitter with EasyDMA
          EasyDMA
          Transmission
          Reception
          Error conditions
          Using the UARTE without flow control
          Parity and stop bit configuration
          Low power
          Pin configuration
          Registers
            TASKS_STARTRX
            TASKS_STOPRX
            TASKS_STARTTX
            TASKS_STOPTX
            TASKS_FLUSHRX
            SUBSCRIBE_STARTRX
            SUBSCRIBE_STOPRX
            SUBSCRIBE_STARTTX
            SUBSCRIBE_STOPTX
            SUBSCRIBE_FLUSHRX
            EVENTS_CTS
            EVENTS_NCTS
            EVENTS_RXDRDY
            EVENTS_ENDRX
            EVENTS_TXDRDY
            EVENTS_ENDTX
            EVENTS_ERROR
            EVENTS_RXTO
            EVENTS_RXSTARTED
            EVENTS_TXSTARTED
            EVENTS_TXSTOPPED
            PUBLISH_CTS
            PUBLISH_NCTS
            PUBLISH_RXDRDY
            PUBLISH_ENDRX
            PUBLISH_TXDRDY
            PUBLISH_ENDTX
            PUBLISH_ERROR
            PUBLISH_RXTO
            PUBLISH_RXSTARTED
            PUBLISH_TXSTARTED
            PUBLISH_TXSTOPPED
            SHORTS
            INTEN
            INTENSET
            INTENCLR
            ERRORSRC
            ENABLE
            PSEL.RTS
            PSEL.TXD
            PSEL.CTS
            PSEL.RXD
            BAUDRATE
            RXD.PTR
            RXD.MAXCNT
            RXD.AMOUNT
            TXD.PTR
            TXD.MAXCNT
            TXD.AMOUNT
            CONFIG
          Electrical specification
            UARTE electrical specification
        WDT — Watchdog timer
          Reload criteria
          Temporarily pausing the watchdog
          Watchdog reset
          Registers
            TASKS_START
            SUBSCRIBE_START
            EVENTS_TIMEOUT
            PUBLISH_TIMEOUT
            INTENSET
            INTENCLR
            RUNSTATUS
            REQSTATUS
            CRV
            RREN
            CONFIG
            RR[n]
          Electrical specification
            Watchdog Timer Electrical Specification
      LTE modem
        Introduction
        SIM card interface
        LTE modem coexistence interface
        LTE modem RF control external interface
        RF front-end interface
        Electrical specification
          Key RF parameters for Cat-M1
          Key RF parameters for Cat-NB1 and Cat-NB2
          Receiver parameters for Cat-M1
          Receiver parameters for Cat-NB1 and Cat-NB2
          Transmitter parameters for Cat-M1
          Transmitter parameters for Cat-NB1 and Cat-NB2
      GPS receiver
        Electrical specification
      Debug and trace
        Overview
          Special consideration regarding debugger access
          DAP - Debug access port
          Debug interface mode
          Real-time debug
          Trace
          Registers
            TARGETID
          Electrical specification
            Trace port
        CTRL-AP - Control access port
          Reset request
          Erase all
          Mailbox interface
          Disabling erase protection
          Registers
            RESET
            ERASEALL
            ERASEALLSTATUS
            APPROTECT.STATUS
            ERASEPROTECT.STATUS
            ERASEPROTECT.DISABLE
            MAILBOX.TXDATA
            MAILBOX.TXSTATUS
            MAILBOX.RXDATA
            MAILBOX.RXSTATUS
            IDR
          Registers
            MAILBOX.RXDATA
            MAILBOX.RXSTATUS
            MAILBOX.TXDATA
            MAILBOX.TXSTATUS
            ERASEPROTECT.LOCK
            ERASEPROTECT.DISABLE
        TAD - Trace and debug control
          Registers
            CLOCKSTART
            CLOCKSTOP
            ENABLE
            PSEL.TRACECLK
            PSEL.TRACEDATA0
            PSEL.TRACEDATA1
            PSEL.TRACEDATA2
            PSEL.TRACEDATA3
            TRACEPORTSPEED ( Retained )
      Hardware and layout
        Pin assignments
          Pin assignments
        Mechanical specifications
          16.00 x 10.50 mm package
      Recommended operating conditions
        VDD_GPIO considerations
      Absolute maximum ratings
      Ordering information
        IC marking
        Box labels
        Order code
        Code ranges and values
        Product options
      Regulatory information
      Legal notices
        Liability disclaimer
        Life support applications
        RoHS and REACH statement
        Trademarks
        Copyright notice
    Errata
      nRF9160 Revision 1 Errata
        Change log
        New and inherited anomalies
          [1] I2S: Excessive power consumption after using STOP task
          [2] NVMC: CPU code execution from RAM halted during flash page erase operation
          [4] GPIO: Bits in GPIO LATCH register are incorrectly set to 1
          [6] POWER: SLEEPENTER and SLEEPEXIT events asserted after pin reset
          [7] KMU: Subsequent accesses between info_mem and main_mem of the flash may not work properly
          [9] SAADC: Reduced SFDR
          [15] REGULATORS: Supply regulators default to LDO mode after reset
          [21] NVMC: Disabling instruction cache causes skip of next instruction
        Fixed anomalies
      nRF9160 Engineering A Errata
        Change log
        New and inherited anomalies
          [1] I2S: Excessive power consumption after using STOP task
          [2] NVMC: CPU code execution from RAM halted during flash page erase operation
          [4] GPIO: Bits in GPIO LATCH register are incorrectly set to 1
          [6] POWER: SLEEPENTER and SLEEPEXIT events asserted after pin reset
          [7] KMU: Subsequent accesses between info_mem and main_mem of the flash may not work properly
          [8] SAADC: Reduced SFDR
          [10] LTE Modem: MAGPIO and MIPI RFFE - high initial voltage
          [12] Debug and Trace: SWD debugger scan
          [14] REGULATORS: Supply regulators default to LDO mode after reset
          [16] SAADC: SAADC result
          [17] Debug and Trace: LTE modem stops when debugging through SWD interface
          [20] RAM: RAM content cannot be trusted upon waking up from System ON IDLE or System OFF mode
          [21] NVMC: Disabling instruction cache causes skip of next instruction
    Compatibility Matrix
      IC revisions and variants
      Documentation and reference design files
      nRF Connect SDK
      Development HW
      Revision history
    nRF9160 DK
      Revision history
      Kit content
        Hardware content
        Related documentation
      Getting started
      Operating modes
        Default mode: Interface MCU
          Device programming
          Virtual COM port
          MSD
          Reset
        nRF ONLY mode
          USB detect
      Hardware description
        Block diagram
        Hardware figures
        Power supply
          nRF9160 supply
          VDD supply rail
          Other power domains
        Antenna interfaces
        GPS
        GPIO interfaces
        nRF52840
          nRF9160 DK board control
          Bluetooth/IEEE 802.15.4 network processor
        Buttons, slide switches, and LEDs
        Debug input and trace options
          Debug output
        Signal routing switches
          Switches for buttons and LEDs
        SIM and eSIM
        Additional nRF9160 interfaces
        SiP enable
        Solder bridge configuration
      Measuring current
        Preparing the development kit for current measurements
        Using an oscilloscope for current profile measurement
        Using a current meter for current measurement
      RF measurements
      Radiated performance of nRF9160 DK
      Glossary
        Band-Pass Filter (BPF)
        Cat-M1
        Cat-NB1
        Clear to Send (CTS)
        DK (Development Kit)
        Fast Identity Online (FIDO)
        Global Positioning System (GPS)
        Hardware Flow Control (HWFC)
        Inter-integrated Circuit (I2C)
        Low-Dropout Regulator (LDO)
        Low-Noise Amplifier (LNA)
        nRF Cloud
        Operational Amplifier (op-amp)
        Receive Data (RXD)
        Request to Send (RTS)
        SAW filter
        Surface Acoustic Wave (SAW)
        System in Package (SiP)
        System on Chip (SoC)
        Transmit Data (TXD)
      Acronyms and abbreviations
      Legal notices
    nRF9160 DK Errata v0.7
  nRF91 AT Commands
    Revision history
    AT command syntax
      Set command <CMD>[=...]
      Read command <CMD>?
      Test command <CMD>=?
      Response
    General
      Request manufacturer identification +CGMI
        Set command
        Read command
        Test command
      Request model identification +CGMM
        Set command
        Read command
        Test command
      Request revision identification +CGMR
        Set command
        Read command
        Test command
      Request product serial number identification +CGSN
        Set command
        Read command
        Test command
      Request IMSI +CIMI
        Set command
        Read command
        Test command
    Mobile termination control and status commands
      Functional mode +CFUN
        Set command
        Read command
        Test command
      PIN code +CPIN
        Set command
        Read command
        Test command
      Remaining PIN retries +CPINR
        Set command
        Read command
        Test command
      List all available AT commands +CLAC
        Set command
        Read command
        Test command
      Extended signal quality +CESQ
        Set command
        Read command
        Test command
      Signal quality notification %CESQ
        Set command
        Read command
        Test command
      SNR signal quality notification %XSNRSQ
        Set command
        Read command
        Test command
      Restricted SIM access +CRSM
        Set command
        Read command
        Test command
      Generic SIM access +CSIM
        Set command
        Read command
        Test command
      Device activity status +CPAS
        Set command
        Read command
        Test command
      Indicator control +CIND
        Set command
        Read command
        Test command
      IP address format +CGPIAF
        Set command
        Read command
        Test command
      Current band %XCBAND
        Set command
        Read command
        Test command
      Read neighbor cells %NBRGRSRP
        Set command
        Read command
        Test command
      Mode of operation (CS/PS) +CEMODE
        Set command
        Read command
        Test command
      UICC state %XSIM
        Set command
        Read command
        Test command
      Authenticated access %XSUDO
        Set command
        Read command
        Test command
      Public key storage management %XPMNG
        Set command
        Read command
        Test command
      RF test execution %XRFTEST
        Set command
          RX testing
          TX testing
          GPS SNR testing
          RX SNR testing
        Read command
        Test command
      Band lock %XBANDLOCK
        Set command
        Read command
        Test command
      Data profile %XDATAPRFL
        Set command
        Read command
        Test command
      Connectivity statistics %XCONNSTAT
        Set command
        Read command
        Test command
      Battery voltage %XVBAT
        Set command
        Read command
        Test command
      Customer production done %XPRODDONE
        Set command
        Read command
        Test command
      Credential storage management %CMNG
        Set command
        Read command
        Test command
      Internal temperature %XTEMP
        Set command
        Read command
        Test command
      High level for internal temperature %XTEMPHIGHLVL
        Set command
        Read command
        Test command
      Clock +CCLK
        Set command
        Read command
        Test command
      Modem trace activation %XMODEMTRACE
        Set command
        Read command
        Test command
      System mode %XSYSTEMMODE
        Set command
        Read command
        Test command
      PTW setting %XPTW
        Set command
        Read command
        Test command
    SiP pin configuration
      COEX0 pin control configuration %XCOEX0
        Set command
        Read command
        Test command
      MAGPIO configuration %XMAGPIO
        Set command
        Read command
        Test command
      SiP-external MIPIRFFE device introduction %XMIPIRFFEDEV
        Set command
        Read command
        Delete configuration
      SiP-external MIPIRFFE device control configuration %XMIPIRFFECTRL
        Set command
        Use cases INIT(0), OFF(2), and PWROFF(3)
        Use case ON(1)
        Delete configuration
    Packet domain commands
      Define PDP Context +CGDCONT
        Set command
        Read command
        Test command
      Packet domain event reporting +CGEREP
        Set command
        Read command
        Test command
      Packet domain event unsolicited result codes +CGEV
      PDP context activate +CGACT
        Set command
        Read command
        Test command
      Allocate new CID %XNEWCID
        Set command
        Read command
        Test command
      Map CID to PDN ID %XGETPDNID
        Set command
        Read command
        Test command
      QoS dynamic params +CGEQOSRDP
        Set command
        Read command
        Test command
      Show PDP address(es) +CGPADDR
        Set command
        Read command
        Test command
      PDN connection dynamic parameters +CGCONTRDP
        Set command
        Read command
        Test command
      PS attach or detach +CGATT
        Set command
        Read command
        Test command
      Power preference indication for EPS +CEPPI
        Set command
        Read command
        Test command
      Protocol configuration options notification %XPCO
        Set command
        Read command
        Test command
      Usage of ePCO/PCO in PDN connection establishment %XEPCO
        Set command
        Read command
        Test command
      APN class access %XAPNCLASS
        Set command
        Read command
        Test command
      External IP stack IPv6 address resolution/refresh failure %XIPV6FAIL
        Set command
        Read command
        Test command
      Define PDN connection authentication parameters +CGAUTH
        Set command
        Read command
        Test command
    Network service related commands
      PLMN selection +COPS
        Set command
        Read command
        Test command
      Power saving mode setting +CPSMS
        Set command
        Read command
        Test command
      eDRX setting +CEDRXS
        Set command
        Read command
        Test command
      Read EDRX dynamic parameters +CEDRXRDP
        Set command
        Read command
        Test command
      Subscriber number +CNUM
        Set command
        Read command
        Test command
      Read operator name +COPN
        Set command
        Read command
        Test command
      Facility lock +CLCK
        Set command
        Read command
        Test command
      Change password +CPWD
        Set command
        Read command
        Test command
      Network registration status +CEREG
        Set command
        Read command
        Test command
      Subscribe unsolicited operator name indications %XOPNAME
        Set command
        Read command
        Test command
      Subscribe unsolicited network time notifications %XTIME
        Set command
        Read command
        Test command
      Set release assistance information %XRAI
        Set command
        Read command
        Test command
      Operator ID %XOPERID
        Set command
        Read command
        Test command
      Read modem parameters %XMONITOR
        Set command
        Read command
        Test command
    Mobile termination errors
      Report mobile termination errors +CMEE
        Set command
        Read command
        Test command
      Report network error codes +CNEC
        Set command
        Read command
        Test command
      Extended error report +CEER
        Set command
        Read command
        Test command
    SMS commands
      Message format +CMGF
        Set command
        Read command
        Test command
      New message indications +CNMI
        Set command
        Read command
        Test command
      Send message, PDU mode + CMGS
        Set command
        Read command
        Test command
      Received SMS notification in PDU mode +CMT
      Delivery status notification in PDU mode +CDS
      New message ACK, PDU mode +CNMA
        Set command
        Read command
        Test command
      New message ACK, text mode +CNMA
        Set command
        Read command
        Test command
      Preferred message storage +CPMS
        Set command
        Read command
        Test command
      Message service failure result code +CMS ERROR
      Select SMS service +CGSMS
        Set command
        Read command
        Test command
      Short message memory available %XSMMA
        Set command
        Read command
        Test command
    Authenticating AT command usage
    Glossary
      16-state Quadrature Amplitude Modulation (16-QAM)
      Access Point Name (APN)
      Binary Phase-Shift Keying (BPSK)
      Carrier Wave (CW)
      Cat-M1
      Cat-NB1
      Check Digit (CD)
      Classless Inter-domain Routing (CIDR)
      CS/PS Mode of Operation
      Discontinuous Reception (DRX)
      Dynamic Host Configuration Protocol (DHCP)
      Electronic Serial Number (ESN)
      EPS Mobility Management (EMM)
      E-UTRA Absolute Radio Frequency Channel Number (EARFCN)
      Evolved Packet System (EPS)
      Extended Discontinuous Reception (eDRX)
      Global Navigation Satellite System (GNSS)
      International Mobile (Station) Equipment Identity (IMEI)
      International Mobile (Station) Equipment Identity, Software Version (IMEISV)
      International Mobile Subscriber Identity (IMSI)
      International Reference Alphabet (IRA)
      Low-Noise Amplifier (LNA)
      Maximum Transmission Unit (MTU)
      MIPI RF Front-End Control Interface (RFFE)
      Mobile Country Code (MCC)
      Mobile Equipment (ME)
      Mobile Network Code (MNC)
      Mobile Station International Subscriber Directory Number (MSISDN)
      Mobile Termination (MT)
      Non-access Stratum (NAS)
      Non-access Stratum (NAS) Signalling Low Priority Indication (NSLPI)
      Non-volatile Memory (NVM)
      Packet Data Network (PDN)
      Packet Data Protocol (PDP)
      Packet Data Protocol (PDP) Context
      Paging Time Window (PTW)
      Personal Identification Number (PIN)
      Personal Unblocking Key (PUK)
      Power Saving Mode (PSM)
      Pre-shared Key (PSK)
      Privacy Enhanced Mail (PEM)
      Protocol Configuration Options (PCO)
      Protocol Data Unit (PDU)
      PS Mode of Operation
      Public Land Mobile Network (PLMN)
      Quadrature Phase-Shift Keying (QPSK)
      Quality of Service (QoS)
      Reference Signal Received Power (RSRP)
      Resource Block (RB)
      RP-SMMA
      Serial Number (SNR)
      Signal-to-Noise Ratio (SNR)
      Software Version Number (SVN)
      Subscriber Identity Module (SIM)
      System in Package (SiP)
      Terminal Adapter (TA)
      Terminal Equipment (TE)
      Tracking Area Code (TAC)
      Tracking Area Update (TAU)
      Type Allocation Code (TAC)
      Universal Integrated Circuit Card (UICC)
      Unique Slave Identifier (USID)
      Universal Subscriber Identity Module (USIM)
      User Equipment (UE)
    Acronyms and abbreviations
    Legal notices
  Environmental Qualification Reports
    HSR nRF9160-SIxx (Qorvo) 2019-03
  nRF9160
    nRF9160 Product Specification
      Revision history
      About this document
        Document status
        Peripheral chapters
        Register tables
          Fields and values
          Permissions
        Registers
          DUMMY
      Product overview
        Introduction
        Block diagram
        Peripheral interface
          Peripheral ID
          Peripherals with shared ID
          Peripheral registers
          Bit set and clear
          Tasks
          Events
          Publish / Subscribe
          Shortcuts
          Interrupts
          Secure/non-secure peripherals
      Application core
        CPU
          CPU and support module configuration
          Electrical specification
            CPU performance
        Memory
          Memory map
          Instantiation
          Peripheral access control capabilities
        VMC — Volatile memory controller
          Registers
            RAM[n].POWER
            RAM[n].POWERSET
            RAM[n].POWERCLR
        NVMC — Non-volatile memory controller
          Writing to flash
          Erasing a secure page in flash
          Erasing a non-secure page in flash
          Writing to user information configuration registers (UICR)
          Erase all
          NVMC protection mechanisms
            NVMC blocking
            NVMC power failure protection
          Cache
          Registers
            READY
            READYNEXT
            CONFIG
            ERASEALL
            ERASEPAGEPARTIALCFG
            ICACHECNF
            IHIT
            IMISS
            CONFIGNS
            WRITEUICRNS
          Electrical specification
            Flash programming
            Cache size
        FICR — Factory information configuration registers
          Registers
            INFO.DEVICEID[n]
            INFO.PART
            INFO.VARIANT
            INFO.PACKAGE
            INFO.RAM
            INFO.FLASH
            INFO.CODEPAGESIZE
            INFO.CODESIZE
            INFO.DEVICETYPE
            TRIMCNF[n].ADDR
            TRIMCNF[n].DATA
            TRNG90B.BYTES
            TRNG90B.RCCUTOFF
            TRNG90B.APCUTOFF
            TRNG90B.STARTUP
            TRNG90B.ROSC1
            TRNG90B.ROSC2
            TRNG90B.ROSC3
            TRNG90B.ROSC4
        UICR — User information configuration registers
          Registers
            APPROTECT
            XOSC32M
            HFXOSRC
            HFXOCNT
            SECUREAPPROTECT
            ERASEPROTECT
            OTP[n]
            KEYSLOT.CONFIG[n].DEST
            KEYSLOT.CONFIG[n].PERM
            KEYSLOT.KEY[n].VALUE[o]
        EasyDMA
          EasyDMA error handling
          EasyDMA array list
        AHB multilayer interconnect
      Power and clock management
        Functional description
          Power management
            System ON mode
            System OFF mode
              Emulated System OFF mode
          Power supply
            General purpose I/O supply
          Power supply monitoring
            Power supply supervisor
            Battery monitoring on VDD
            Electrical specification
              Device startup times
              Power supply supervisor
          Clock management
            HFCLK clock controller
            LFCLK clock controller
              32.768 kHz RC oscillator (LFRC)
            Electrical specification
              64 MHz internal oscillator (HFINT)
               64 MHz high accuracy oscillator (HFXO)
              32.768 kHz high accuracy oscillator (LFXO)
              32.768 kHz RC oscillator (LFRC)
          Reset
            Power-on reset
            Pin reset
            Wakeup from System OFF mode reset
            Soft reset
            Watchdog reset
            Brownout reset
            Retained registers
            Reset behavior
            Electrical specification
              Pin reset
        Current consumption
          Electrical specification
            Sleep
            Application CPU active current consumption
            I2S
            PDM
            PWM
            SAADC
            TIMER
            SPIM
            SPIS
            TWIM
            TWIS
            UARTE
            WDT
            Modem current consumption
            GPS current consumption
        Register description
          POWER — Power control
            Registers
              TASKS_CONSTLAT
              TASKS_LOWPWR
              SUBSCRIBE_CONSTLAT
              SUBSCRIBE_LOWPWR
              EVENTS_POFWARN
              EVENTS_SLEEPENTER
              EVENTS_SLEEPEXIT
              PUBLISH_POFWARN
              PUBLISH_SLEEPENTER
              PUBLISH_SLEEPEXIT
              INTEN
              INTENSET
              INTENCLR
              RESETREAS
              POWERSTATUS
              GPREGRET[n]
          CLOCK — Clock control
            Registers
              TASKS_HFCLKSTART
              TASKS_HFCLKSTOP
              TASKS_LFCLKSTART
              TASKS_LFCLKSTOP
              SUBSCRIBE_HFCLKSTART
              SUBSCRIBE_HFCLKSTOP
              SUBSCRIBE_LFCLKSTART
              SUBSCRIBE_LFCLKSTOP
              EVENTS_HFCLKSTARTED
              EVENTS_LFCLKSTARTED
              PUBLISH_HFCLKSTARTED
              PUBLISH_LFCLKSTARTED
              INTEN
              INTENSET
              INTENCLR
              INTPEND
              HFCLKRUN
              HFCLKSTAT
              LFCLKRUN
              LFCLKSTAT
              LFCLKSRCCOPY
              LFCLKSRC
          REGULATORS — Voltage regulators control
            Registers
              SYSTEMOFF
              DCDCEN
      Peripherals
        CRYPTOCELL — ARM TrustZone CryptoCell 310
          Usage
          Always-on (AO) power domain
          Lifecycle state (LCS)
          Cryptographic key selection
            RTL key
            Device root key
          Direct memory access (DMA)
          Standards
          Registers
            ENABLE
          Host interface
            HOST_RGF block
              Registers
                HOST_CRYPTOKEY_SEL
                HOST_IOT_KPRTL_LOCK
                HOST_IOT_KDR0
                HOST_IOT_KDR1
                HOST_IOT_KDR2
                HOST_IOT_KDR3
                HOST_IOT_LCS
        DPPI - Distributed programmable peripheral interconnect
          Subscribing to and publishing on channels
          DPPI configuration (DPPIC)
          Connection examples
          Special considerations for a system implementing TrustZone for Cortex-M processors
          Registers
            TASKS_CHG[n].EN
            TASKS_CHG[n].DIS
            SUBSCRIBE_CHG[n].EN
            SUBSCRIBE_CHG[n].DIS
            CHEN
            CHENSET
            CHENCLR
            CHG[n]
        EGU — Event generator unit
          Registers
            TASKS_TRIGGER[n]
            SUBSCRIBE_TRIGGER[n]
            EVENTS_TRIGGERED[n]
            PUBLISH_TRIGGERED[n]
            INTEN
            INTENSET
            INTENCLR
          Electrical specification
            EGU Electrical Specification
        GPIO — General purpose input/output
          Pin configuration
          Pin sense mechanism
          GPIO security
          Registers
            OUT ( Retained )
            OUTSET
            OUTCLR
            IN
            DIR ( Retained )
            DIRSET
            DIRCLR
            LATCH ( Retained )
            DETECTMODE ( Retained )
            DETECTMODE_SEC ( Retained )
            PIN_CNF[n]
          Electrical specification
            GPIO Electrical Specification
        GPIOTE — GPIO tasks and events
          Pin events and tasks
          Port event
          Tasks and events pin configuration
          Registers
            TASKS_OUT[n]
            TASKS_SET[n]
            TASKS_CLR[n]
            SUBSCRIBE_OUT[n]
            SUBSCRIBE_SET[n]
            SUBSCRIBE_CLR[n]
            EVENTS_IN[n]
            EVENTS_PORT
            PUBLISH_IN[n]
            PUBLISH_PORT
            INTENSET
            INTENCLR
            CONFIG[n]
          Electrical specification
        IPC — Interprocessor communication
          IPC and PPI connections
          Registers
            TASKS_SEND[n]
            SUBSCRIBE_SEND[n]
            EVENTS_RECEIVE[n]
            PUBLISH_RECEIVE[n]
            INTEN
            INTENSET
            INTENCLR
            INTPEND
            SEND_CNF[n]
            RECEIVE_CNF[n]
            GPMEM[n]
          Electrical specification
            IPC Electrical Specification
        I2S — Inter-IC sound interface
          Mode
          Transmitting and receiving
          Left right clock (LRCK)
          Serial clock (SCK)
          Master clock (MCK)
          Width, alignment and format
          EasyDMA
          Module operation
          Pin configuration
          Registers
            TASKS_START
            TASKS_STOP
            SUBSCRIBE_START
            SUBSCRIBE_STOP
            EVENTS_RXPTRUPD
            EVENTS_STOPPED
            EVENTS_TXPTRUPD
            PUBLISH_RXPTRUPD
            PUBLISH_STOPPED
            PUBLISH_TXPTRUPD
            INTEN
            INTENSET
            INTENCLR
            ENABLE
            CONFIG.MODE
            CONFIG.RXEN
            CONFIG.TXEN
            CONFIG.MCKEN
            CONFIG.MCKFREQ
            CONFIG.RATIO
            CONFIG.SWIDTH
            CONFIG.ALIGN
            CONFIG.FORMAT
            CONFIG.CHANNELS
            RXD.PTR
            TXD.PTR
            RXTXD.MAXCNT
            PSEL.MCK
            PSEL.SCK
            PSEL.LRCK
            PSEL.SDIN
            PSEL.SDOUT
          Electrical specification
            I2S timing specification
        KMU — Key management unit
          Functional view
          Access control
          Protecting the UICR content
          Usage
            OTP
            Key storage
              Selecting a key slot
              Writing to a key slot
              Reading a key value
              Push over secure APB
              Revoking the key slots
            STATUS register
          Registers
            TASKS_PUSH_KEYSLOT
            EVENTS_KEYSLOT_PUSHED
            EVENTS_KEYSLOT_REVOKED
            EVENTS_KEYSLOT_ERROR
            INTEN
            INTENSET
            INTENCLR
            INTPEND
            STATUS
            SELECTKEYSLOT
        PDM — Pulse density modulation interface
          Master clock generator
          Module operation
          Decimation filter
          EasyDMA
          Hardware example
          Pin configuration
          Registers
            TASKS_START
            TASKS_STOP
            SUBSCRIBE_START
            SUBSCRIBE_STOP
            EVENTS_STARTED
            EVENTS_STOPPED
            EVENTS_END
            PUBLISH_STARTED
            PUBLISH_STOPPED
            PUBLISH_END
            INTEN
            INTENSET
            INTENCLR
            ENABLE
            PDMCLKCTRL
            MODE
            GAINL
            GAINR
            RATIO
            PSEL.CLK
            PSEL.DIN
            SAMPLE.PTR
            SAMPLE.MAXCNT
          Electrical specification
            PDM Electrical Specification
        PWM — Pulse width modulation
          Wave counter
          Decoder with EasyDMA
          Limitations
          Pin configuration
          Registers
            TASKS_STOP
            TASKS_SEQSTART[n]
            TASKS_NEXTSTEP
            SUBSCRIBE_STOP
            SUBSCRIBE_SEQSTART[n]
            SUBSCRIBE_NEXTSTEP
            EVENTS_STOPPED
            EVENTS_SEQSTARTED[n]
            EVENTS_SEQEND[n]
            EVENTS_PWMPERIODEND
            EVENTS_LOOPSDONE
            PUBLISH_STOPPED
            PUBLISH_SEQSTARTED[n]
            PUBLISH_SEQEND[n]
            PUBLISH_PWMPERIODEND
            PUBLISH_LOOPSDONE
            SHORTS
            INTEN
            INTENSET
            INTENCLR
            ENABLE
            MODE
            COUNTERTOP
            PRESCALER
            DECODER
            LOOP
            SEQ[n].PTR
            SEQ[n].CNT
            SEQ[n].REFRESH
            SEQ[n].ENDDELAY
            PSEL.OUT[n]
        RTC — Real-time counter
          Clock source
          Resolution versus overflow and the prescaler
          Counter register
          Overflow
          Tick event
          Event control
          Compare
          Task and event jitter/delay
          Reading the counter register
          Registers
            TASKS_START
            TASKS_STOP
            TASKS_CLEAR
            TASKS_TRIGOVRFLW
            SUBSCRIBE_START
            SUBSCRIBE_STOP
            SUBSCRIBE_CLEAR
            SUBSCRIBE_TRIGOVRFLW
            EVENTS_TICK
            EVENTS_OVRFLW
            EVENTS_COMPARE[n]
            PUBLISH_TICK
            PUBLISH_OVRFLW
            PUBLISH_COMPARE[n]
            INTENSET
            INTENCLR
            EVTEN
            EVTENSET
            EVTENCLR
            COUNTER
            PRESCALER
            CC[n]
          Electrical specification
        SAADC — Successive approximation analog-to-digital converter
          Overview
          Digital output
          Analog inputs and channels
          Operation modes
            One-shot mode
            Continuous mode
            Oversampling
            Scan mode
          EasyDMA
          Resistor ladder
          Reference
          Acquisition time
          Limits event monitoring
          Registers
            TASKS_START
            TASKS_SAMPLE
            TASKS_STOP
            TASKS_CALIBRATEOFFSET
            SUBSCRIBE_START
            SUBSCRIBE_SAMPLE
            SUBSCRIBE_STOP
            SUBSCRIBE_CALIBRATEOFFSET
            EVENTS_STARTED
            EVENTS_END
            EVENTS_DONE
            EVENTS_RESULTDONE
            EVENTS_CALIBRATEDONE
            EVENTS_STOPPED
            EVENTS_CH[n].LIMITH
            EVENTS_CH[n].LIMITL
            PUBLISH_STARTED
            PUBLISH_END
            PUBLISH_DONE
            PUBLISH_RESULTDONE
            PUBLISH_CALIBRATEDONE
            PUBLISH_STOPPED
            PUBLISH_CH[n].LIMITH
            PUBLISH_CH[n].LIMITL
            INTEN
            INTENSET
            INTENCLR
            STATUS
            ENABLE
            CH[n].PSELP
            CH[n].PSELN
            CH[n].CONFIG
            CH[n].LIMIT
            RESOLUTION
            OVERSAMPLE
            SAMPLERATE
            RESULT.PTR
            RESULT.MAXCNT
            RESULT.AMOUNT
          Electrical specification
            SAADC Electrical Specification
          Performance factors
        SPIM — Serial peripheral interface master with EasyDMA
          SPI master transaction sequence
          Master mode pin configuration
          Shared resources
          EasyDMA
          Low power
          Registers
            TASKS_START
            TASKS_STOP
            TASKS_SUSPEND
            TASKS_RESUME
            SUBSCRIBE_START
            SUBSCRIBE_STOP
            SUBSCRIBE_SUSPEND
            SUBSCRIBE_RESUME
            EVENTS_STOPPED
            EVENTS_ENDRX
            EVENTS_END
            EVENTS_ENDTX
            EVENTS_STARTED
            PUBLISH_STOPPED
            PUBLISH_ENDRX
            PUBLISH_END
            PUBLISH_ENDTX
            PUBLISH_STARTED
            SHORTS
            INTENSET
            INTENCLR
            ENABLE
            PSEL.SCK
            PSEL.MOSI
            PSEL.MISO
            FREQUENCY
            RXD.PTR
            RXD.MAXCNT
            RXD.AMOUNT
            RXD.LIST
            TXD.PTR
            TXD.MAXCNT
            TXD.AMOUNT
            TXD.LIST
            CONFIG
            ORC
          Electrical specification
            SPIM master interface electrical specifications
            Serial Peripheral Interface Master (SPIM) timing specifications
        SPIS — Serial peripheral interface slave with EasyDMA
          Shared resources
          EasyDMA
          SPI slave operation
          Semaphore operation
          Pin configuration
          Registers
            TASKS_ACQUIRE
            TASKS_RELEASE
            SUBSCRIBE_ACQUIRE
            SUBSCRIBE_RELEASE
            EVENTS_END
            EVENTS_ENDRX
            EVENTS_ACQUIRED
            PUBLISH_END
            PUBLISH_ENDRX
            PUBLISH_ACQUIRED
            SHORTS
            INTENSET
            INTENCLR
            SEMSTAT
            STATUS
            ENABLE
            PSEL.SCK
            PSEL.MISO
            PSEL.MOSI
            PSEL.CSN
            PSELSCK ( Deprecated )
            PSELMISO ( Deprecated )
            PSELMOSI ( Deprecated )
            PSELCSN ( Deprecated )
            RXDPTR ( Deprecated )
            MAXRX ( Deprecated )
            AMOUNTRX ( Deprecated )
            RXD.PTR
            RXD.MAXCNT
            RXD.AMOUNT
            RXD.LIST
            TXDPTR ( Deprecated )
            MAXTX ( Deprecated )
            AMOUNTTX ( Deprecated )
            TXD.PTR
            TXD.MAXCNT
            TXD.AMOUNT
            TXD.LIST
            CONFIG
            DEF
            ORC
          Electrical specification
            SPIS slave interface electrical specifications
            Serial Peripheral Interface Slave (SPIS) timing specifications
        SPU - System protection unit
          General concepts
            Special considerations for ARM TrustZone for Cortex-M enabled system
          Flash access control
            Non-secure callable (NSC) region definition in flash
            Flash access error reporting
            UICR and FICR protections
          RAM access control
            Non-secure callable (NSC) region definition in RAM
            RAM access error reporting
          Peripheral access control
            Peripherals with split security
            Peripheral address mapping
            Special considerations for peripherals with DMA master
            Peripheral access error reporting
          Pin access control
            Direct pin control through the GPIO peripheral
          DPPI access control
            Special considerations regarding the DPPIC configuration registers
          External domain access control
          TrustZone for Cortex-M ID allocation
          Registers
            EVENTS_RAMACCERR
            EVENTS_FLASHACCERR
            EVENTS_PERIPHACCERR
            PUBLISH_RAMACCERR
            PUBLISH_FLASHACCERR
            PUBLISH_PERIPHACCERR
            INTEN
            INTENSET
            INTENCLR
            CAP
            EXTDOMAIN[n].PERM
            DPPI[n].PERM
            DPPI[n].LOCK
            GPIOPORT[n].PERM
            GPIOPORT[n].LOCK
            FLASHNSC[n].REGION
            FLASHNSC[n].SIZE
            RAMNSC[n].REGION
            RAMNSC[n].SIZE
            FLASHREGION[n].PERM
            RAMREGION[n].PERM
            PERIPHID[n].PERM
        TIMER — Timer/counter
          Capture
          Compare
          Task delays
          Task priority
          Registers
            TASKS_START
            TASKS_STOP
            TASKS_COUNT
            TASKS_CLEAR
            TASKS_SHUTDOWN ( Deprecated )
            TASKS_CAPTURE[n]
            SUBSCRIBE_START
            SUBSCRIBE_STOP
            SUBSCRIBE_COUNT
            SUBSCRIBE_CLEAR
            SUBSCRIBE_SHUTDOWN ( Deprecated )
            SUBSCRIBE_CAPTURE[n]
            EVENTS_COMPARE[n]
            PUBLISH_COMPARE[n]
            SHORTS
            INTENSET
            INTENCLR
            MODE
            BITMODE
            PRESCALER
            ONESHOTEN[n]
            CC[n]
          Electrical specification
        TWIM — I2C compatible two-wire interface master with EasyDMA
          Shared resources
          EasyDMA
          Master write sequence
          Master read sequence
          Master repeated start sequence
          Low power
          Master mode pin configuration
          Registers
            TASKS_STARTRX
            TASKS_STARTTX
            TASKS_STOP
            TASKS_SUSPEND
            TASKS_RESUME
            SUBSCRIBE_STARTRX
            SUBSCRIBE_STARTTX
            SUBSCRIBE_STOP
            SUBSCRIBE_SUSPEND
            SUBSCRIBE_RESUME
            EVENTS_STOPPED
            EVENTS_ERROR
            EVENTS_SUSPENDED
            EVENTS_RXSTARTED
            EVENTS_TXSTARTED
            EVENTS_LASTRX
            EVENTS_LASTTX
            PUBLISH_STOPPED
            PUBLISH_ERROR
            PUBLISH_SUSPENDED
            PUBLISH_RXSTARTED
            PUBLISH_TXSTARTED
            PUBLISH_LASTRX
            PUBLISH_LASTTX
            SHORTS
            INTEN
            INTENSET
            INTENCLR
            ERRORSRC
            ENABLE
            PSEL.SCL
            PSEL.SDA
            FREQUENCY
            RXD.PTR
            RXD.MAXCNT
            RXD.AMOUNT
            RXD.LIST
            TXD.PTR
            TXD.MAXCNT
            TXD.AMOUNT
            TXD.LIST
            ADDRESS
          Electrical specification
            TWIM interface electrical specifications
            Two Wire Interface Master (TWIM) timing specifications
          Pullup resistor
        TWIS — I2C compatible two-wire interface slave with EasyDMA
          Shared resources
          EasyDMA
          TWI slave responding to a read command
          TWI slave responding to a write command
          Master repeated start sequence
          Terminating an ongoing TWI transaction
          Low power
          Slave mode pin configuration
          Registers
            TASKS_STOP
            TASKS_SUSPEND
            TASKS_RESUME
            TASKS_PREPARERX
            TASKS_PREPARETX
            SUBSCRIBE_STOP
            SUBSCRIBE_SUSPEND
            SUBSCRIBE_RESUME
            SUBSCRIBE_PREPARERX
            SUBSCRIBE_PREPARETX
            EVENTS_STOPPED
            EVENTS_ERROR
            EVENTS_RXSTARTED
            EVENTS_TXSTARTED
            EVENTS_WRITE
            EVENTS_READ
            PUBLISH_STOPPED
            PUBLISH_ERROR
            PUBLISH_RXSTARTED
            PUBLISH_TXSTARTED
            PUBLISH_WRITE
            PUBLISH_READ
            SHORTS
            INTEN
            INTENSET
            INTENCLR
            ERRORSRC
            MATCH
            ENABLE
            PSEL.SCL
            PSEL.SDA
            RXD.PTR
            RXD.MAXCNT
            RXD.AMOUNT
            RXD.LIST
            TXD.PTR
            TXD.MAXCNT
            TXD.AMOUNT
            TXD.LIST
            ADDRESS[n]
            CONFIG
            ORC
          Electrical specification
            TWIS slave timing specifications
        UARTE — Universal asynchronous receiver/transmitter with EasyDMA
          EasyDMA
          Transmission
          Reception
          Error conditions
          Using the UARTE without flow control
          Parity and stop bit configuration
          Low power
          Pin configuration
          Registers
            TASKS_STARTRX
            TASKS_STOPRX
            TASKS_STARTTX
            TASKS_STOPTX
            TASKS_FLUSHRX
            SUBSCRIBE_STARTRX
            SUBSCRIBE_STOPRX
            SUBSCRIBE_STARTTX
            SUBSCRIBE_STOPTX
            SUBSCRIBE_FLUSHRX
            EVENTS_CTS
            EVENTS_NCTS
            EVENTS_RXDRDY
            EVENTS_ENDRX
            EVENTS_TXDRDY
            EVENTS_ENDTX
            EVENTS_ERROR
            EVENTS_RXTO
            EVENTS_RXSTARTED
            EVENTS_TXSTARTED
            EVENTS_TXSTOPPED
            PUBLISH_CTS
            PUBLISH_NCTS
            PUBLISH_RXDRDY
            PUBLISH_ENDRX
            PUBLISH_TXDRDY
            PUBLISH_ENDTX
            PUBLISH_ERROR
            PUBLISH_RXTO
            PUBLISH_RXSTARTED
            PUBLISH_TXSTARTED
            PUBLISH_TXSTOPPED
            SHORTS
            INTEN
            INTENSET
            INTENCLR
            ERRORSRC
            ENABLE
            PSEL.RTS
            PSEL.TXD
            PSEL.CTS
            PSEL.RXD
            BAUDRATE
            RXD.PTR
            RXD.MAXCNT
            RXD.AMOUNT
            TXD.PTR
            TXD.MAXCNT
            TXD.AMOUNT
            CONFIG
          Electrical specification
            UARTE electrical specification
        WDT — Watchdog timer
          Reload criteria
          Temporarily pausing the watchdog
          Watchdog reset
          Registers
            TASKS_START
            SUBSCRIBE_START
            EVENTS_TIMEOUT
            PUBLISH_TIMEOUT
            INTENSET
            INTENCLR
            RUNSTATUS
            REQSTATUS
            CRV
            RREN
            CONFIG
            RR[n]
          Electrical specification
            Watchdog Timer Electrical Specification
      LTE modem
        Introduction
        SIM card interface
        LTE modem coexistence interface
        LTE modem RF control external interface
        RF front-end interface
        Electrical specification
          Key RF parameters for Cat-M1
          Key RF parameters for Cat-NB1 and Cat-NB2
          Receiver parameters for Cat-M1
          Receiver parameters for Cat-NB1 and Cat-NB2
          Transmitter parameters for Cat-M1
          Transmitter parameters for Cat-NB1 and Cat-NB2
      GPS receiver
        Electrical specification
      Debug and trace
        Overview
          Special consideration regarding debugger access
          DAP - Debug access port
          Debug interface mode
          Real-time debug
          Trace
          Registers
            TARGETID
          Electrical specification
            Trace port
        CTRL-AP - Control access port
          Reset request
          Erase all
          Mailbox interface
          Disabling erase protection
          Registers
            RESET
            ERASEALL
            ERASEALLSTATUS
            APPROTECT.STATUS
            ERASEPROTECT.STATUS
            ERASEPROTECT.DISABLE
            MAILBOX.TXDATA
            MAILBOX.TXSTATUS
            MAILBOX.RXDATA
            MAILBOX.RXSTATUS
            IDR
          Registers
            MAILBOX.RXDATA
            MAILBOX.RXSTATUS
            MAILBOX.TXDATA
            MAILBOX.TXSTATUS
            ERASEPROTECT.LOCK
            ERASEPROTECT.DISABLE
        TAD - Trace and debug control
          Registers
            CLOCKSTART
            CLOCKSTOP
            ENABLE
            PSEL.TRACECLK
            PSEL.TRACEDATA0
            PSEL.TRACEDATA1
            PSEL.TRACEDATA2
            PSEL.TRACEDATA3
            TRACEPORTSPEED ( Retained )
      Hardware and layout
        Pin assignments
          Pin assignments
        Mechanical specifications
          16.00 x 10.50 mm package
      Recommended operating conditions
        VDD_GPIO considerations
      Absolute maximum ratings
      Ordering information
        IC marking
        Box labels
        Order code
        Code ranges and values
        Product options
      Regulatory information
      Legal notices
        Liability disclaimer
        Life support applications
        RoHS and REACH statement
        Trademarks
        Copyright notice
    Errata
      nRF9160 Revision 1 Errata
        Change log
        New and inherited anomalies
          [1] I2S: Excessive power consumption after using STOP task
          [2] NVMC: CPU code execution from RAM halted during flash page erase operation
          [4] GPIO: Bits in GPIO LATCH register are incorrectly set to 1
          [6] POWER: SLEEPENTER and SLEEPEXIT events asserted after pin reset
          [7] KMU: Subsequent accesses between info_mem and main_mem of the flash may not work properly
          [9] SAADC: Reduced SFDR
          [15] REGULATORS: Supply regulators default to LDO mode after reset
          [21] NVMC: Disabling instruction cache causes skip of next instruction
        Fixed anomalies
      nRF9160 Engineering A Errata
        Change log
        New and inherited anomalies
          [1] I2S: Excessive power consumption after using STOP task
          [2] NVMC: CPU code execution from RAM halted during flash page erase operation
          [4] GPIO: Bits in GPIO LATCH register are incorrectly set to 1
          [6] POWER: SLEEPENTER and SLEEPEXIT events asserted after pin reset
          [7] KMU: Subsequent accesses between info_mem and main_mem of the flash may not work properly
          [8] SAADC: Reduced SFDR
          [10] LTE Modem: MAGPIO and MIPI RFFE - high initial voltage
          [12] Debug and Trace: SWD debugger scan
          [14] REGULATORS: Supply regulators default to LDO mode after reset
          [16] SAADC: SAADC result
          [17] Debug and Trace: LTE modem stops when debugging through SWD interface
          [20] RAM: RAM content cannot be trusted upon waking up from System ON IDLE or System OFF mode
          [21] NVMC: Disabling instruction cache causes skip of next instruction
    Compatibility Matrix
      IC revisions and variants
      Documentation and reference design files
      nRF Connect SDK
      Development HW
      Revision history
    nRF9160 DK
      Revision history
      Kit content
        Hardware content
        Related documentation
      Getting started
      Operating modes
        Default mode: Interface MCU
          Device programming
          Virtual COM port
          MSD
          Reset
        nRF ONLY mode
          USB detect
      Hardware description
        Block diagram
        Hardware figures
        Power supply
          nRF9160 supply
          VDD supply rail
          Other power domains
        Antenna interfaces
        GPS
        GPIO interfaces
        nRF52840
          nRF9160 DK board control
          Bluetooth/IEEE 802.15.4 network processor
        Buttons, slide switches, and LEDs
        Debug input and trace options
          Debug output
        Signal routing switches
          Switches for buttons and LEDs
        SIM and eSIM
        Additional nRF9160 interfaces
        SiP enable
        Solder bridge configuration
      Measuring current
        Preparing the development kit for current measurements
        Using an oscilloscope for current profile measurement
        Using a current meter for current measurement
      RF measurements
      Radiated performance of nRF9160 DK
      Glossary
        Band-Pass Filter (BPF)
        Cat-M1
        Cat-NB1
        Clear to Send (CTS)
        DK (Development Kit)
        Fast Identity Online (FIDO)
        Global Positioning System (GPS)
        Hardware Flow Control (HWFC)
        Inter-integrated Circuit (I2C)
        Low-Dropout Regulator (LDO)
        Low-Noise Amplifier (LNA)
        nRF Cloud
        Operational Amplifier (op-amp)
        Receive Data (RXD)
        Request to Send (RTS)
        SAW filter
        Surface Acoustic Wave (SAW)
        System in Package (SiP)
        System on Chip (SoC)
        Transmit Data (TXD)
      Acronyms and abbreviations
      Legal notices
    nRF9160 DK Errata v0.7
  nRF91 AT Commands
    Revision history
    AT command syntax
      Set command <CMD>[=...]
      Read command <CMD>?
      Test command <CMD>=?
      Response
    General
      Request manufacturer identification +CGMI
        Set command
        Read command
        Test command
      Request model identification +CGMM
        Set command
        Read command
        Test command
      Request revision identification +CGMR
        Set command
        Read command
        Test command
      Request product serial number identification +CGSN
        Set command
        Read command
        Test command
      Request IMSI +CIMI
        Set command
        Read command
        Test command
    Mobile termination control and status commands
      Functional mode +CFUN
        Set command
        Read command
        Test command
      PIN code +CPIN
        Set command
        Read command
        Test command
      Remaining PIN retries +CPINR
        Set command
        Read command
        Test command
      List all available AT commands +CLAC
        Set command
        Read command
        Test command
      Extended signal quality +CESQ
        Set command
        Read command
        Test command
      Signal quality notification %CESQ
        Set command
        Read command
        Test command
      SNR signal quality notification %XSNRSQ
        Set command
        Read command
        Test command
      Restricted SIM access +CRSM
        Set command
        Read command
        Test command
      Generic SIM access +CSIM
        Set command
        Read command
        Test command
      Device activity status +CPAS
        Set command
        Read command
        Test command
      Indicator control +CIND
        Set command
        Read command
        Test command
      IP address format +CGPIAF
        Set command
        Read command
        Test command
      Current band %XCBAND
        Set command
        Read command
        Test command
      Read neighbor cells %NBRGRSRP
        Set command
        Read command
        Test command
      Mode of operation (CS/PS) +CEMODE
        Set command
        Read command
        Test command
      UICC state %XSIM
        Set command
        Read command
        Test command
      Authenticated access %XSUDO
        Set command
        Read command
        Test command
      Public key storage management %XPMNG
        Set command
        Read command
        Test command
      RF test execution %XRFTEST
        Set command
          RX testing
          TX testing
          GPS SNR testing
          RX SNR testing
        Read command
        Test command
      Band lock %XBANDLOCK
        Set command
        Read command
        Test command
      Data profile %XDATAPRFL
        Set command
        Read command
        Test command
      Connectivity statistics %XCONNSTAT
        Set command
        Read command
        Test command
      Battery voltage %XVBAT
        Set command
        Read command
        Test command
      Customer production done %XPRODDONE
        Set command
        Read command
        Test command
      Credential storage management %CMNG
        Set command
        Read command
        Test command
      Internal temperature %XTEMP
        Set command
        Read command
        Test command
      High level for internal temperature %XTEMPHIGHLVL
        Set command
        Read command
        Test command
      Clock +CCLK
        Set command
        Read command
        Test command
      Modem trace activation %XMODEMTRACE
        Set command
        Read command
        Test command
      System mode %XSYSTEMMODE
        Set command
        Read command
        Test command
      PTW setting %XPTW
        Set command
        Read command
        Test command
    SiP pin configuration
      COEX0 pin control configuration %XCOEX0
        Set command
        Read command
        Test command
      MAGPIO configuration %XMAGPIO
        Set command
        Read command
        Test command
      SiP-external MIPIRFFE device introduction %XMIPIRFFEDEV
        Set command
        Read command
        Delete configuration
      SiP-external MIPIRFFE device control configuration %XMIPIRFFECTRL
        Set command
        Use cases INIT(0), OFF(2), and PWROFF(3)
        Use case ON(1)
        Delete configuration
    Packet domain commands
      Define PDP Context +CGDCONT
        Set command
        Read command
        Test command
      Packet domain event reporting +CGEREP
        Set command
        Read command
        Test command
      Packet domain event unsolicited result codes +CGEV
      PDP context activate +CGACT
        Set command
        Read command
        Test command
      Allocate new CID %XNEWCID
        Set command
        Read command
        Test command
      Map CID to PDN ID %XGETPDNID
        Set command
        Read command
        Test command
      QoS dynamic params +CGEQOSRDP
        Set command
        Read command
        Test command
      Show PDP address(es) +CGPADDR
        Set command
        Read command
        Test command
      PDN connection dynamic parameters +CGCONTRDP
        Set command
        Read command
        Test command
      PS attach or detach +CGATT
        Set command
        Read command
        Test command
      Power preference indication for EPS +CEPPI
        Set command
        Read command
        Test command
      Protocol configuration options notification %XPCO
        Set command
        Read command
        Test command
      Usage of ePCO/PCO in PDN connection establishment %XEPCO
        Set command
        Read command
        Test command
      APN class access %XAPNCLASS
        Set command
        Read command
        Test command
      External IP stack IPv6 address resolution/refresh failure %XIPV6FAIL
        Set command
        Read command
        Test command
      Define PDN connection authentication parameters +CGAUTH
        Set command
        Read command
        Test command
    Network service related commands
      PLMN selection +COPS
        Set command
        Read command
        Test command
      Power saving mode setting +CPSMS
        Set command
        Read command
        Test command
      eDRX setting +CEDRXS
        Set command
        Read command
        Test command
      Read EDRX dynamic parameters +CEDRXRDP
        Set command
        Read command
        Test command
      Subscriber number +CNUM
        Set command
        Read command
        Test command
      Read operator name +COPN
        Set command
        Read command
        Test command
      Facility lock +CLCK
        Set command
        Read command
        Test command
      Change password +CPWD
        Set command
        Read command
        Test command
      Network registration status +CEREG
        Set command
        Read command
        Test command
      Subscribe unsolicited operator name indications %XOPNAME
        Set command
        Read command
        Test command
      Subscribe unsolicited network time notifications %XTIME
        Set command
        Read command
        Test command
      Set release assistance information %XRAI
        Set command
        Read command
        Test command
      Operator ID %XOPERID
        Set command
        Read command
        Test command
      Read modem parameters %XMONITOR
        Set command
        Read command
        Test command
    Mobile termination errors
      Report mobile termination errors +CMEE
        Set command
        Read command
        Test command
      Report network error codes +CNEC
        Set command
        Read command
        Test command
      Extended error report +CEER
        Set command
        Read command
        Test command
    SMS commands
      Message format +CMGF
        Set command
        Read command
        Test command
      New message indications +CNMI
        Set command
        Read command
        Test command
      Send message, PDU mode + CMGS
        Set command
        Read command
        Test command
      Received SMS notification in PDU mode +CMT
      Delivery status notification in PDU mode +CDS
      New message ACK, PDU mode +CNMA
        Set command
        Read command
        Test command
      New message ACK, text mode +CNMA
        Set command
        Read command
        Test command
      Preferred message storage +CPMS
        Set command
        Read command
        Test command
      Message service failure result code +CMS ERROR
      Select SMS service +CGSMS
        Set command
        Read command
        Test command
      Short message memory available %XSMMA
        Set command
        Read command
        Test command
    Authenticating AT command usage
    Glossary
      16-state Quadrature Amplitude Modulation (16-QAM)
      Access Point Name (APN)
      Binary Phase-Shift Keying (BPSK)
      Carrier Wave (CW)
      Cat-M1
      Cat-NB1
      Check Digit (CD)
      Classless Inter-domain Routing (CIDR)
      CS/PS Mode of Operation
      Discontinuous Reception (DRX)
      Dynamic Host Configuration Protocol (DHCP)
      Electronic Serial Number (ESN)
      EPS Mobility Management (EMM)
      E-UTRA Absolute Radio Frequency Channel Number (EARFCN)
      Evolved Packet System (EPS)
      Extended Discontinuous Reception (eDRX)
      Global Navigation Satellite System (GNSS)
      International Mobile (Station) Equipment Identity (IMEI)
      International Mobile (Station) Equipment Identity, Software Version (IMEISV)
      International Mobile Subscriber Identity (IMSI)
      International Reference Alphabet (IRA)
      Low-Noise Amplifier (LNA)
      Maximum Transmission Unit (MTU)
      MIPI RF Front-End Control Interface (RFFE)
      Mobile Country Code (MCC)
      Mobile Equipment (ME)
      Mobile Network Code (MNC)
      Mobile Station International Subscriber Directory Number (MSISDN)
      Mobile Termination (MT)
      Non-access Stratum (NAS)
      Non-access Stratum (NAS) Signalling Low Priority Indication (NSLPI)
      Non-volatile Memory (NVM)
      Packet Data Network (PDN)
      Packet Data Protocol (PDP)
      Packet Data Protocol (PDP) Context
      Paging Time Window (PTW)
      Personal Identification Number (PIN)
      Personal Unblocking Key (PUK)
      Power Saving Mode (PSM)
      Pre-shared Key (PSK)
      Privacy Enhanced Mail (PEM)
      Protocol Configuration Options (PCO)
      Protocol Data Unit (PDU)
      PS Mode of Operation
      Public Land Mobile Network (PLMN)
      Quadrature Phase-Shift Keying (QPSK)
      Quality of Service (QoS)
      Reference Signal Received Power (RSRP)
      Resource Block (RB)
      RP-SMMA
      Serial Number (SNR)
      Signal-to-Noise Ratio (SNR)
      Software Version Number (SVN)
      Subscriber Identity Module (SIM)
      System in Package (SiP)
      Terminal Adapter (TA)
      Terminal Equipment (TE)
      Tracking Area Code (TAC)
      Tracking Area Update (TAU)
      Type Allocation Code (TAC)
      Universal Integrated Circuit Card (UICC)
      Unique Slave Identifier (USID)
      Universal Subscriber Identity Module (USIM)
      User Equipment (UE)
    Acronyms and abbreviations
    Legal notices
  Environmental Qualification Reports
    HSR nRF9160-SIxx (Qorvo) 2019-03
nRF52 Series
  nRF52840
    nRF52840 Product Specification
      Revision history
      About this document
        Document naming and status
        Peripheral naming and abbreviations
        Register tables
          Fields and values
        Registers
          DUMMY
      Block diagram
      Core components
        CPU
          Floating point interrupt
          CPU and support module configuration
          Electrical specification
            CPU performance
        Memory
          RAM - Random access memory
          Flash - Non-volatile memory
          Memory map
          Instantiation
        NVMC — Non-volatile memory controller
          Writing to flash
          Erasing a page in flash
          Writing to user information configuration registers (UICR)
          Erasing user information configuration registers (UICR)
          Erase all
          Access port protection behavior
          Partial erase of a page in flash
          Cache
          Registers
            READY
            READYNEXT
            CONFIG
            ERASEPAGE
            ERASEPCR1 ( Deprecated )
            ERASEALL
            ERASEPCR0 ( Deprecated )
            ERASEUICR
            ERASEPAGEPARTIAL
            ERASEPAGEPARTIALCFG
            ICACHECNF
            IHIT
            IMISS
          Electrical specification
            Flash programming
            Cache size
        FICR — Factory information configuration registers
          Registers
            CODEPAGESIZE
            CODESIZE
            DEVICEID[n]
            ER[n]
            IR[n]
            DEVICEADDRTYPE
            DEVICEADDR[n]
            INFO.PART
            INFO.VARIANT
            INFO.PACKAGE
            INFO.RAM
            INFO.FLASH
            PRODTEST[n]
            TEMP.A0
            TEMP.A1
            TEMP.A2
            TEMP.A3
            TEMP.A4
            TEMP.A5
            TEMP.B0
            TEMP.B1
            TEMP.B2
            TEMP.B3
            TEMP.B4
            TEMP.B5
            TEMP.T0
            TEMP.T1
            TEMP.T2
            TEMP.T3
            TEMP.T4
            NFC.TAGHEADER0
            NFC.TAGHEADER1
            NFC.TAGHEADER2
            NFC.TAGHEADER3
            TRNG90B.BYTES
            TRNG90B.RCCUTOFF
            TRNG90B.APCUTOFF
            TRNG90B.STARTUP
            TRNG90B.ROSC1
            TRNG90B.ROSC2
            TRNG90B.ROSC3
            TRNG90B.ROSC4
        UICR — User information configuration registers
          Registers
            NRFFW[n]
            NRFHW[n]
            CUSTOMER[n]
            PSELRESET[n]
            APPROTECT
            NFCPINS
            DEBUGCTRL
            REGOUT0
        EasyDMA
          EasyDMA error handling
          EasyDMA array list
        AHB multilayer
        Debug and trace
          DAP - Debug access port
          CTRL-AP - Control access port
            Registers
              RESET
              ERASEALL
              ERASEALLSTATUS
              APPROTECTSTATUS
              IDR
            Electrical specification
              Control access port
          Debug interface mode
          Real-time debug
          Trace
            Electrical specification
              Trace port
      Power and clock management
        Power management unit (PMU)
        Current consumption
          Electrical specification
            Sleep
            COMP active
            CPU running
            NFCT active
            Radio transmitting/receiving
            RNG active
            SAADC active
            TEMP active
            TIMER running
            WDT active
            Compounded
        POWER — Power supply
          Main supply
            Main voltage regulators
            GPIO levels
            External circuitry supply
            Regulator configuration examples
            Power supply supervisor
            Power-fail comparator
          USB supply
          System OFF mode
            Emulated System OFF mode
          System ON mode
            Sub power modes
          RAM power control
          Reset
            Power-on reset
            Pin reset
            Wakeup from System OFF mode reset
            Soft reset
            Watchdog reset
            Brownout reset
            Retained registers
            Reset behavior
          Registers
            TASKS_CONSTLAT
            TASKS_LOWPWR
            EVENTS_POFWARN
            EVENTS_SLEEPENTER
            EVENTS_SLEEPEXIT
            EVENTS_USBDETECTED
            EVENTS_USBREMOVED
            EVENTS_USBPWRRDY
            INTENSET
            INTENCLR
            RESETREAS
            RAMSTATUS ( Deprecated )
            USBREGSTATUS
            SYSTEMOFF
            POFCON
            GPREGRET
            GPREGRET2
            DCDCEN
            DCDCEN0
            MAINREGSTATUS
            RAM[n].POWER
            RAM[n].POWERSET
            RAM[n].POWERCLR
          Electrical specification
            Regulator operating conditions
            Regulator specifications, REG0 stage
            Device startup times
            Power fail comparator
            USB operating conditions
            USB regulator specifications
            VBUS detection specifications
        CLOCK — Clock control
          HFCLK controller
            64 MHz crystal oscillator (HFXO)
          LFCLK controller
            32.768 kHz RC oscillator (LFRC)
            Calibrating the 32.768 kHz RC oscillator
            Calibration timer
            32.768 kHz crystal oscillator (LFXO)
            32.768 kHz synthesized from HFCLK (LFSYNT)
          Registers
            TASKS_HFCLKSTART
            TASKS_HFCLKSTOP
            TASKS_LFCLKSTART
            TASKS_LFCLKSTOP
            TASKS_CAL
            TASKS_CTSTART
            TASKS_CTSTOP
            EVENTS_HFCLKSTARTED
            EVENTS_LFCLKSTARTED
            EVENTS_DONE
            EVENTS_CTTO
            EVENTS_CTSTARTED
            EVENTS_CTSTOPPED
            INTENSET
            INTENCLR
            HFCLKRUN
            HFCLKSTAT
            LFCLKRUN
            LFCLKSTAT
            LFCLKSRCCOPY
            LFCLKSRC
            HFXODEBOUNCE
            CTIV ( Retained )
            TRACECONFIG
            LFRCMODE
          Electrical specification
            64 MHz internal oscillator (HFINT)
            64 MHz crystal oscillator (HFXO)
            Low frequency crystal oscillator (LFXO)
            Low frequency RC oscillator (LFRC), Normal mode
            Low frequency RC oscillator (LFRC), Ultra-low power mode (ULP)
            Synthesized low frequency clock (LFSYNT)
      Peripherals
        Peripheral interface
          Peripheral ID
          Peripherals with shared ID
          Peripheral registers
          Bit set and clear
          Tasks
          Events
          Shortcuts
          Interrupts
        AAR — Accelerated address resolver
          EasyDMA
          Resolving a resolvable address
          Use case example for chaining RADIO packet reception with address resolution using AAR
          IRK data structure
          Registers
            TASKS_START
            TASKS_STOP
            EVENTS_END
            EVENTS_RESOLVED
            EVENTS_NOTRESOLVED
            INTENSET
            INTENCLR
            STATUS
            ENABLE
            NIRK
            IRKPTR
            ADDRPTR
            SCRATCHPTR
          Electrical specification
            AAR Electrical Specification
        ACL — Access control lists
          Registers
            ACL[n].ADDR
            ACL[n].SIZE
            ACL[n].PERM
        CCM — AES CCM mode encryption
          Key-steam generation
          Encryption
          Decryption
          AES CCM and RADIO concurrent operation
          Encrypting packets on-the-fly in radio transmit mode
          Decrypting packets on-the-fly in radio receive mode
          CCM data structure
          EasyDMA and ERROR event
          Registers
            TASKS_KSGEN
            TASKS_CRYPT
            TASKS_STOP
            TASKS_RATEOVERRIDE
            EVENTS_ENDKSGEN
            EVENTS_ENDCRYPT
            EVENTS_ERROR ( Deprecated )
            SHORTS
            INTENSET
            INTENCLR
            MICSTATUS
            ENABLE
            MODE
            CNFPTR
            INPTR
            OUTPTR
            SCRATCHPTR
            MAXPACKETSIZE
            RATEOVERRIDE
          Electrical specification
            Timing specification
        COMP — Comparator
          Differential mode
          Single-ended mode
          Registers
            TASKS_START
            TASKS_STOP
            TASKS_SAMPLE
            EVENTS_READY
            EVENTS_DOWN
            EVENTS_UP
            EVENTS_CROSS
            SHORTS
            INTEN
            INTENSET
            INTENCLR
            RESULT
            ENABLE
            PSEL
            REFSEL
            EXTREFSEL
            TH
            MODE
            HYST
          Electrical specification
            COMP Electrical Specification
        CRYPTOCELL — ARM TrustZone CryptoCell 310
          Usage
          Always-on (AO) power domain
          Lifecycle state (LCS)
          Cryptographic key selection
            RTL key
            Device root key
          Direct memory access (DMA)
          Standards
          Registers
            ENABLE
          Host interface
            HOST_RGF block
              Registers
                HOST_CRYPTOKEY_SEL
                HOST_IOT_KPRTL_LOCK
                HOST_IOT_KDR0
                HOST_IOT_KDR1
                HOST_IOT_KDR2
                HOST_IOT_KDR3
                HOST_IOT_LCS
        ECB — AES electronic codebook mode encryption
          Shared resources
          EasyDMA
          ECB data structure
          Registers
            TASKS_STARTECB
            TASKS_STOPECB
            EVENTS_ENDECB
            EVENTS_ERRORECB
            INTENSET
            INTENCLR
            ECBDATAPTR
          Electrical specification
            ECB Electrical Specification
        EGU — Event generator unit
          Registers
            TASKS_TRIGGER[n]
            EVENTS_TRIGGERED[n]
            INTEN
            INTENSET
            INTENCLR
          Electrical specification
            EGU Electrical Specification
        GPIO — General purpose input/output
          Pin configuration
          Registers
            OUT
            OUTSET
            OUTCLR
            IN
            DIR
            DIRSET
            DIRCLR
            LATCH
            DETECTMODE
            PIN_CNF[n]
          Electrical specification
            GPIO Electrical Specification
        GPIOTE — GPIO tasks and events
          Pin events and tasks
          Port event
          Tasks and events pin configuration
          Registers
            TASKS_OUT[n]
            TASKS_SET[n]
            TASKS_CLR[n]
            EVENTS_IN[n]
            EVENTS_PORT
            INTENSET
            INTENCLR
            CONFIG[n]
          Electrical specification
        I2S — Inter-IC sound interface
          Mode
          Transmitting and receiving
          Left right clock (LRCK)
          Serial clock (SCK)
          Master clock (MCK)
          Width, alignment and format
          EasyDMA
          Module operation
          Pin configuration
          Registers
            TASKS_START
            TASKS_STOP
            EVENTS_RXPTRUPD
            EVENTS_STOPPED
            EVENTS_TXPTRUPD
            INTEN
            INTENSET
            INTENCLR
            ENABLE
            CONFIG.MODE
            CONFIG.RXEN
            CONFIG.TXEN
            CONFIG.MCKEN
            CONFIG.MCKFREQ
            CONFIG.RATIO
            CONFIG.SWIDTH
            CONFIG.ALIGN
            CONFIG.FORMAT
            CONFIG.CHANNELS
            RXD.PTR
            TXD.PTR
            RXTXD.MAXCNT
            PSEL.MCK
            PSEL.SCK
            PSEL.LRCK
            PSEL.SDIN
            PSEL.SDOUT
          Electrical specification
            I2S timing specification
        LPCOMP — Low power comparator
          Shared resources
          Pin configuration
          Registers
            TASKS_START
            TASKS_STOP
            TASKS_SAMPLE
            EVENTS_READY
            EVENTS_DOWN
            EVENTS_UP
            EVENTS_CROSS
            SHORTS
            INTENSET
            INTENCLR
            RESULT
            ENABLE
            PSEL
            REFSEL
            EXTREFSEL
            ANADETECT
            HYST
          Electrical specification
            LPCOMP Electrical Specification
        MWU — Memory watch unit
          Registers
            EVENTS_REGION[n].WA
            EVENTS_REGION[n].RA
            EVENTS_PREGION[n].WA
            EVENTS_PREGION[n].RA
            INTEN
            INTENSET
            INTENCLR
            NMIEN
            NMIENSET
            NMIENCLR
            PERREGION[n].SUBSTATWA
            PERREGION[n].SUBSTATRA
            REGIONEN
            REGIONENSET
            REGIONENCLR
            REGION[n].START
            REGION[n].END
            PREGION[n].START
            PREGION[n].END
            PREGION[n].SUBS
        NFCT — Near field communication tag
          Overview
          Operating states
          Pin configuration
          EasyDMA
          Frame assembler
          Frame disassembler
          Frame timing controller
          Collision resolution
          Antenna interface
          NFCT antenna recommendations
          Battery protection
           References
          Registers
            TASKS_ACTIVATE
            TASKS_DISABLE
            TASKS_SENSE
            TASKS_STARTTX
            TASKS_ENABLERXDATA
            TASKS_GOIDLE
            TASKS_GOSLEEP
            EVENTS_READY
            EVENTS_FIELDDETECTED
            EVENTS_FIELDLOST
            EVENTS_TXFRAMESTART
            EVENTS_TXFRAMEEND
            EVENTS_RXFRAMESTART
            EVENTS_RXFRAMEEND
            EVENTS_ERROR
            EVENTS_RXERROR
            EVENTS_ENDRX
            EVENTS_ENDTX
            EVENTS_AUTOCOLRESSTARTED
            EVENTS_COLLISION
            EVENTS_SELECTED
            EVENTS_STARTED
            SHORTS
            INTEN
            INTENSET
            INTENCLR
            ERRORSTATUS
            FRAMESTATUS.RX
            NFCTAGSTATE
            SLEEPSTATE
            FIELDPRESENT
            FRAMEDELAYMIN
            FRAMEDELAYMAX
            FRAMEDELAYMODE
            PACKETPTR
            MAXLEN
            TXD.FRAMECONFIG
            TXD.AMOUNT
            RXD.FRAMECONFIG
            RXD.AMOUNT
            NFCID1_LAST
            NFCID1_2ND_LAST
            NFCID1_3RD_LAST
            AUTOCOLRESCONFIG
            SENSRES
            SELRES
          Electrical specification
            NFCT Electrical Specification
            NFCT Timing Parameters
        PDM — Pulse density modulation interface
          Master clock generator
          Module operation
          Decimation filter
          EasyDMA
          Hardware example
          Pin configuration
          Registers
            TASKS_START
            TASKS_STOP
            EVENTS_STARTED
            EVENTS_STOPPED
            EVENTS_END
            INTEN
            INTENSET
            INTENCLR
            ENABLE
            PDMCLKCTRL
            MODE
            GAINL
            GAINR
            RATIO
            PSEL.CLK
            PSEL.DIN
            SAMPLE.PTR
            SAMPLE.MAXCNT
          Electrical specification
            PDM Electrical Specification
        PPI — Programmable peripheral interconnect
          Pre-programmed channels
          Registers
            TASKS_CHG[n].EN
            TASKS_CHG[n].DIS
            CHEN
            CHENSET
            CHENCLR
            CH[n].EEP
            CH[n].TEP
            CHG[n]
            FORK[n].TEP
        PWM — Pulse width modulation
          Wave counter
          Decoder with EasyDMA
          Limitations
          Pin configuration
          Registers
            TASKS_STOP
            TASKS_SEQSTART[n]
            TASKS_NEXTSTEP
            EVENTS_STOPPED
            EVENTS_SEQSTARTED[n]
            EVENTS_SEQEND[n]
            EVENTS_PWMPERIODEND
            EVENTS_LOOPSDONE
            SHORTS
            INTEN
            INTENSET
            INTENCLR
            ENABLE
            MODE
            COUNTERTOP
            PRESCALER
            DECODER
            LOOP
            SEQ[n].PTR
            SEQ[n].CNT
            SEQ[n].REFRESH
            SEQ[n].ENDDELAY
            PSEL.OUT[n]
        QDEC — Quadrature decoder
          Sampling and decoding
          LED output
          Debounce filters
          Accumulators
          Output/input pins
          Pin configuration
          Registers
            TASKS_START
            TASKS_STOP
            TASKS_READCLRACC
            TASKS_RDCLRACC
            TASKS_RDCLRDBL
            EVENTS_SAMPLERDY
            EVENTS_REPORTRDY
            EVENTS_ACCOF
            EVENTS_DBLRDY
            EVENTS_STOPPED
            SHORTS
            INTENSET
            INTENCLR
            ENABLE
            LEDPOL
            SAMPLEPER
            SAMPLE
            REPORTPER
            ACC
            ACCREAD
            PSEL.LED
            PSEL.A
            PSEL.B
            DBFEN
            LEDPRE
            ACCDBL
            ACCDBLREAD
          Electrical specification
            QDEC Electrical Specification
        QSPI — Quad serial peripheral interface
          Configuring peripheral
          Write operation
          Read operation
          Erase operation
          Execute in place
          Sending custom instructions
            Long frame mode
          Deep power-down mode
          Instruction set
          Interface description
          Registers
            TASKS_ACTIVATE
            TASKS_READSTART
            TASKS_WRITESTART
            TASKS_ERASESTART
            TASKS_DEACTIVATE
            EVENTS_READY
            INTEN
            INTENSET
            INTENCLR
            ENABLE
            READ.SRC
            READ.DST
            READ.CNT
            WRITE.DST
            WRITE.SRC
            WRITE.CNT
            ERASE.PTR
            ERASE.LEN
            PSEL.SCK
            PSEL.CSN
            PSEL.IO0
            PSEL.IO1
            PSEL.IO2
            PSEL.IO3
            XIPOFFSET
            IFCONFIG0
            IFCONFIG1
            STATUS
            DPMDUR
            ADDRCONF
            CINSTRCONF
            CINSTRDAT0
            CINSTRDAT1
            IFTIMING
          Electrical specification
            Timing specification
        RADIO — 2.4 GHz radio
          Packet configuration
          Address configuration
          Data whitening
          CRC
          Radio states
          Transmit sequence
          Receive sequence
          Received signal strength indicator (RSSI)
          Interframe spacing
          Device address match
          Bit counter
          IEEE 802.15.4 operation
            Packet structure
            Operating frequencies
            Energy detection (ED)
            Clear channel assessment (CCA)
            Cyclic redundancy check (CRC)
            Transmit sequence
            Receive sequence
            Interframe spacing (IFS)
          EasyDMA
          Registers
            TASKS_TXEN
            TASKS_RXEN
            TASKS_START
            TASKS_STOP
            TASKS_DISABLE
            TASKS_RSSISTART
            TASKS_RSSISTOP
            TASKS_BCSTART
            TASKS_BCSTOP
            TASKS_EDSTART
            TASKS_EDSTOP
            TASKS_CCASTART
            TASKS_CCASTOP
            EVENTS_READY
            EVENTS_ADDRESS
            EVENTS_PAYLOAD
            EVENTS_END
            EVENTS_DISABLED
            EVENTS_DEVMATCH
            EVENTS_DEVMISS
            EVENTS_RSSIEND
            EVENTS_BCMATCH
            EVENTS_CRCOK
            EVENTS_CRCERROR
            EVENTS_FRAMESTART
            EVENTS_EDEND
            EVENTS_EDSTOPPED
            EVENTS_CCAIDLE
            EVENTS_CCABUSY
            EVENTS_CCASTOPPED
            EVENTS_RATEBOOST
            EVENTS_TXREADY
            EVENTS_RXREADY
            EVENTS_MHRMATCH
            EVENTS_PHYEND
            SHORTS
            INTENSET
            INTENCLR
            CRCSTATUS
            RXMATCH
            RXCRC
            DAI
            PDUSTAT
            PACKETPTR
            FREQUENCY
            TXPOWER
            MODE
            PCNF0
            PCNF1
            BASE0
            BASE1
            PREFIX0
            PREFIX1
            TXADDRESS
            RXADDRESSES
            CRCCNF
            CRCPOLY
            CRCINIT
            TIFS
            RSSISAMPLE
            STATE
            DATAWHITEIV
            BCC
            DAB[n]
            DAP[n]
            DACNF
            MHRMATCHCONF
            MHRMATCHMAS
            MODECNF0
            SFD
            EDCNT
            EDSAMPLE
            CCACTRL
            POWER
          Electrical specification
            General radio characteristics
            Radio current consumption (transmitter)
            Radio current consumption (Receiver)
            Transmitter specification
            Receiver operation
            RX selectivity
            RX intermodulation
            Radio timing
            Received signal strength indicator (RSSI) specifications
            Jitter
            IEEE 802.15.4 energy detection constants
        RNG — Random number generator
          Bias correction
          Speed
          Registers
            TASKS_START
            TASKS_STOP
            EVENTS_VALRDY
            SHORTS
            INTENSET
            INTENCLR
            CONFIG
            VALUE
          Electrical specification
            RNG Electrical Specification
        RTC — Real-time counter
          Clock source
          Resolution versus overflow and the PRESCALER
          COUNTER register
          Overflow features
          TICK event
          Event control feature
          Compare feature
          TASK and EVENT jitter/delay
          Reading the COUNTER register
          Registers
            TASKS_START
            TASKS_STOP
            TASKS_CLEAR
            TASKS_TRIGOVRFLW
            EVENTS_TICK
            EVENTS_OVRFLW
            EVENTS_COMPARE[n]
            INTENSET
            INTENCLR
            EVTEN
            EVTENSET
            EVTENCLR
            COUNTER
            PRESCALER
            CC[n]
          Electrical specification
        SAADC — Successive approximation analog-to-digital converter
          Input configuration
            Acquisition time
            Internal resistor string (resistor ladder)
          Reference voltage and gain settings
          Digital output
          EasyDMA
          Continuous sampling
          Oversampling
          Event monitoring using limits
          Calibration
          Registers
            TASKS_START
            TASKS_SAMPLE
            TASKS_STOP
            TASKS_CALIBRATEOFFSET
            EVENTS_STARTED
            EVENTS_END
            EVENTS_DONE
            EVENTS_RESULTDONE
            EVENTS_CALIBRATEDONE
            EVENTS_STOPPED
            EVENTS_CH[n].LIMITH
            EVENTS_CH[n].LIMITL
            INTEN
            INTENSET
            INTENCLR
            STATUS
            ENABLE
            CH[n].PSELP
            CH[n].PSELN
            CH[n].CONFIG
            CH[n].LIMIT
            RESOLUTION
            OVERSAMPLE
            SAMPLERATE
            RESULT.PTR
            RESULT.MAXCNT
            RESULT.AMOUNT
          Electrical specification
            SAADC electrical specification
        SPI — Serial peripheral interface master
          Functional description
            SPI master mode pin configuration
            Shared resources
            SPI master transaction sequence
          Registers
            EVENTS_READY
            INTENSET
            INTENCLR
            ENABLE
            PSEL.SCK
            PSEL.MOSI
            PSEL.MISO
            RXD
            TXD
            FREQUENCY
            CONFIG
          Electrical specification
            SPI master interface electrical specifications
            Serial Peripheral Interface (SPI) Master timing specifications
        SPIM — Serial peripheral interface master with EasyDMA
          SPI master transaction sequence
          D/CX functionality
          Pin configuration
          EasyDMA
          Low power
          Registers
            TASKS_START
            TASKS_STOP
            TASKS_SUSPEND
            TASKS_RESUME
            EVENTS_STOPPED
            EVENTS_ENDRX
            EVENTS_END
            EVENTS_ENDTX
            EVENTS_STARTED
            SHORTS
            INTENSET
            INTENCLR
            STALLSTAT
            ENABLE
            PSEL.SCK
            PSEL.MOSI
            PSEL.MISO
            PSEL.CSN
            FREQUENCY
            RXD.PTR
            RXD.MAXCNT
            RXD.AMOUNT
            RXD.LIST
            TXD.PTR
            TXD.MAXCNT
            TXD.AMOUNT
            TXD.LIST
            CONFIG
            IFTIMING.RXDELAY
            IFTIMING.CSNDUR
            CSNPOL
            PSELDCX
            DCXCNT
            ORC
          Electrical specification
            Timing specifications
        SPIS — Serial peripheral interface slave with EasyDMA
          Shared resources
          EasyDMA
          SPI slave operation
          Pin configuration
          Registers
            TASKS_ACQUIRE
            TASKS_RELEASE
            EVENTS_END
            EVENTS_ENDRX
            EVENTS_ACQUIRED
            SHORTS
            INTENSET
            INTENCLR
            SEMSTAT
            STATUS
            ENABLE
            PSEL.SCK
            PSEL.MISO
            PSEL.MOSI
            PSEL.CSN
            PSELSCK ( Deprecated )
            PSELMISO ( Deprecated )
            PSELMOSI ( Deprecated )
            PSELCSN ( Deprecated )
            RXDPTR ( Deprecated )
            MAXRX ( Deprecated )
            AMOUNTRX ( Deprecated )
            RXD.PTR
            RXD.MAXCNT
            RXD.AMOUNT
            RXD.LIST
            TXDPTR ( Deprecated )
            MAXTX ( Deprecated )
            AMOUNTTX ( Deprecated )
            TXD.PTR
            TXD.MAXCNT
            TXD.AMOUNT
            TXD.LIST
            CONFIG
            DEF
            ORC
          Electrical specification
            SPIS slave interface electrical specifications
            Serial Peripheral Interface Slave (SPIS) timing specifications
        SWI — Software interrupts
          Registers
        TEMP — Temperature sensor
          Registers
            TASKS_START
            TASKS_STOP
            EVENTS_DATARDY
            INTENSET
            INTENCLR
            TEMP
            A0
            A1
            A2
            A3
            A4
            A5
            B0
            B1
            B2
            B3
            B4
            B5
            T0
            T1
            T2
            T3
            T4
          Electrical specification
            Temperature Sensor Electrical Specification
        TWI — I2C compatible two-wire interface
          Functional description
          Master mode pin configuration
          Shared resources
          Master write sequence
          Master read sequence
          Master repeated start sequence
          Low power
          Registers
            TASKS_STARTRX
            TASKS_STARTTX
            TASKS_STOP
            TASKS_SUSPEND
            TASKS_RESUME
            EVENTS_STOPPED
            EVENTS_RXDREADY
            EVENTS_TXDSENT
            EVENTS_ERROR
            EVENTS_BB
            EVENTS_SUSPENDED
            SHORTS
            INTENSET
            INTENCLR
            ERRORSRC
            ENABLE
            PSEL.SCL
            PSEL.SDA
            RXD
            TXD
            FREQUENCY
            ADDRESS
          Electrical specification
            TWI interface electrical specifications
            Two Wire Interface (TWI) timing specifications
        TIMER — Timer/counter
          Capture
          Compare
          Task delays
          Task priority
          Registers
            TASKS_START
            TASKS_STOP
            TASKS_COUNT
            TASKS_CLEAR
            TASKS_SHUTDOWN ( Deprecated )
            TASKS_CAPTURE[n]
            EVENTS_COMPARE[n]
            SHORTS
            INTENSET
            INTENCLR
            MODE
            BITMODE
            PRESCALER
            CC[n]
        TWIM — I2C compatible two-wire interface master with EasyDMA
          EasyDMA
          Master write sequence
          Master read sequence
          Master repeated start sequence
          Low power
          Master mode pin configuration
          Registers
            TASKS_STARTRX
            TASKS_STARTTX
            TASKS_STOP
            TASKS_SUSPEND
            TASKS_RESUME
            EVENTS_STOPPED
            EVENTS_ERROR
            EVENTS_SUSPENDED
            EVENTS_RXSTARTED
            EVENTS_TXSTARTED
            EVENTS_LASTRX
            EVENTS_LASTTX
            SHORTS
            INTEN
            INTENSET
            INTENCLR
            ERRORSRC
            ENABLE
            PSEL.SCL
            PSEL.SDA
            FREQUENCY
            RXD.PTR
            RXD.MAXCNT
            RXD.AMOUNT
            RXD.LIST
            TXD.PTR
            TXD.MAXCNT
            TXD.AMOUNT
            TXD.LIST
            ADDRESS
          Electrical specification
            TWIM interface electrical specifications
            Two Wire Interface Master (TWIM) timing specifications
          Pullup resistor
        TWIS — I2C compatible two-wire interface slave with EasyDMA
          EasyDMA
          TWI slave responding to a read command
          TWI slave responding to a write command
          Master repeated start sequence
          Terminating an ongoing TWI transaction
          Low power
          Slave mode pin configuration
          Registers
            TASKS_STOP
            TASKS_SUSPEND
            TASKS_RESUME
            TASKS_PREPARERX
            TASKS_PREPARETX
            EVENTS_STOPPED
            EVENTS_ERROR
            EVENTS_RXSTARTED
            EVENTS_TXSTARTED
            EVENTS_WRITE
            EVENTS_READ
            SHORTS
            INTEN
            INTENSET
            INTENCLR
            ERRORSRC
            MATCH
            ENABLE
            PSEL.SCL
            PSEL.SDA
            RXD.PTR
            RXD.MAXCNT
            RXD.AMOUNT
            RXD.LIST
            TXD.PTR
            TXD.MAXCNT
            TXD.AMOUNT
            TXD.LIST
            ADDRESS[n]
            CONFIG
            ORC
          Electrical specification
            TWIS slave timing specifications
        UART — Universal asynchronous receiver/transmitter
          Functional description
          Pin configuration
          Shared resources
          Transmission
          Reception
          Suspending the UART
          Error conditions
          Using the UART without flow control
          Parity and stop bit configuration
          Registers
            TASKS_STARTRX
            TASKS_STOPRX
            TASKS_STARTTX
            TASKS_STOPTX
            TASKS_SUSPEND
            EVENTS_CTS
            EVENTS_NCTS
            EVENTS_RXDRDY
            EVENTS_TXDRDY
            EVENTS_ERROR
            EVENTS_RXTO
            SHORTS
            INTENSET
            INTENCLR
            ERRORSRC
            ENABLE
            PSEL.RTS
            PSEL.TXD
            PSEL.CTS
            PSEL.RXD
            RXD
            TXD
            BAUDRATE
            CONFIG
          Electrical specification
            UART electrical specification
        UARTE — Universal asynchronous receiver/transmitter with EasyDMA
          EasyDMA
          Transmission
          Reception
          Error conditions
          Using the UARTE without flow control
          Parity and stop bit configuration
          Low power
          Pin configuration
          Registers
            TASKS_STARTRX
            TASKS_STOPRX
            TASKS_STARTTX
            TASKS_STOPTX
            TASKS_FLUSHRX
            EVENTS_CTS
            EVENTS_NCTS
            EVENTS_RXDRDY
            EVENTS_ENDRX
            EVENTS_TXDRDY
            EVENTS_ENDTX
            EVENTS_ERROR
            EVENTS_RXTO
            EVENTS_RXSTARTED
            EVENTS_TXSTARTED
            EVENTS_TXSTOPPED
            SHORTS
            INTEN
            INTENSET
            INTENCLR
            ERRORSRC
            ENABLE
            PSEL.RTS
            PSEL.TXD
            PSEL.CTS
            PSEL.RXD
            BAUDRATE
            RXD.PTR
            RXD.MAXCNT
            RXD.AMOUNT
            TXD.PTR
            TXD.MAXCNT
            TXD.AMOUNT
            CONFIG
          Electrical specification
            UARTE electrical specification
        USBD — Universal serial bus device
          USB device states
          USB terminology
          USB pins
          USBD power-up sequence
          USB pull-up
          USB reset
          USB suspend and resume
            Entering suspend
            Host-initiated resume
            Device-initiated remote wake-up
          EasyDMA
          Control transfers
            Control read transfer
            Control write transfer
          Bulk and interrupt transactions
            Bulk and interrupt IN transaction
            Bulk and interrupt OUT transaction
          Isochronous transactions
            Isochronous IN transaction
            Isochronous OUT transaction
          USB register access limitations
          Registers
            TASKS_STARTEPIN[n]
            TASKS_STARTISOIN
            TASKS_STARTEPOUT[n]
            TASKS_STARTISOOUT
            TASKS_EP0RCVOUT
            TASKS_EP0STATUS
            TASKS_EP0STALL
            TASKS_DPDMDRIVE
            TASKS_DPDMNODRIVE
            EVENTS_USBRESET
            EVENTS_STARTED
            EVENTS_ENDEPIN[n]
            EVENTS_EP0DATADONE
            EVENTS_ENDISOIN
            EVENTS_ENDEPOUT[n]
            EVENTS_ENDISOOUT
            EVENTS_SOF
            EVENTS_USBEVENT
            EVENTS_EP0SETUP
            EVENTS_EPDATA
            SHORTS
            INTEN
            INTENSET
            INTENCLR
            EVENTCAUSE
            HALTED.EPIN[n]
            HALTED.EPOUT[n]
            EPSTATUS
            EPDATASTATUS
            USBADDR
            BMREQUESTTYPE
            BREQUEST
            WVALUEL
            WVALUEH
            WINDEXL
            WINDEXH
            WLENGTHL
            WLENGTHH
            SIZE.EPOUT[n]
            SIZE.ISOOUT
            ENABLE
            USBPULLUP
            DPDMVALUE
            DTOGGLE
            EPINEN
            EPOUTEN
            EPSTALL
            ISOSPLIT
            FRAMECNTR
            LOWPOWER
            ISOINCONFIG
            EPIN[n].PTR
            EPIN[n].MAXCNT
            EPIN[n].AMOUNT
            ISOIN.PTR
            ISOIN.MAXCNT
            ISOIN.AMOUNT
            EPOUT[n].PTR
            EPOUT[n].MAXCNT
            EPOUT[n].AMOUNT
            ISOOUT.PTR
            ISOOUT.MAXCNT
            ISOOUT.AMOUNT
          Electrical specification
            USB Electrical Specification
        WDT — Watchdog timer
          Reload criteria
          Temporarily pausing the watchdog
          Watchdog reset
          Registers
            TASKS_START
            EVENTS_TIMEOUT
            INTENSET
            INTENCLR
            RUNSTATUS
            REQSTATUS
            CRV
            RREN
            CONFIG
            RR[n]
          Electrical specification
            Watchdog Timer Electrical Specification
      Hardware and layout
        Pin assignments
          aQFN73 ball assignments
          WLCSP ball assignments
        Mechanical specifications
          aQFN73 7 x 7 mm package
          WLCSP 3.544 x 3.607 mm package
        Reference circuitry
          Circuit configuration no. 1
          Circuit configuration no. 2
          Circuit configuration no. 3
          Circuit configuration no. 4
          Circuit configuration no. 5
          Circuit configuration no. 6
          Circuit configuration no. 1 for CKAA WLCSP
          Circuit configuration no. 2 for CKAA WLCSP
          Circuit configuration no. 3 for CKAA WLCSP
          Circuit configuration no. 4 for CKAA WLCSP
          Circuit configuration no. 5 for CKAA WLCSP
          Circuit configuration no. 6 for CKAA WLCSP
          PCB guidelines
          PCB layout example
      Recommended operating conditions
      Absolute maximum ratings
      Ordering information
        Package marking
        Box labels
        Order code
        Code ranges and values
        Product options
      Legal notices
        Liability disclaimer
        Life support applications
        RoHS and REACH statement
        Trademarks
        Copyright notice
    Errata
      nRF52840 Rev 2 Errata
        Change log
        New and inherited anomalies
          [20] RTC: Register values are invalid
          [36] CLOCK: Some registers are not reset when expected
          [55] I2S: RXPTRUPD and TXPTRUPD events asserted after STOP
          [66] TEMP: Linearity specification not met with default settings
          [78] TIMER: High current consumption when using timer STOP task only
          [81] GPIO: PIN_CNF is not retained when in debug interface mode
          [87] CPU: Unexpected wake from System ON Idle when using FPU
          [122] QSPI: QSPI uses current after being disabled
          [136] System: Bits in RESETREAS are set when they should not be
          [153] RADIO: RSSI parameter adjustment
          [155] GPIOTE: IN event may occur more than once on input edge
          [166] USBD: ISO double buffering not functional
          [170] I2S: NRF_I2S->PSEL CONNECT fields are not readable
          [171] USB,USBD: USB might not power up
          [172] RADIO: BLE long range co-channel performance
          [173] GPIO: Writes to LATCH register take several CPU cycles to take effect
          [174] SPIM: SPIM3 events incorrectly connected to the PPI
          [176] System: Flash erase through CTRL-AP fails due to watchdog time-out
          [179] RTC: COMPARE event is generated twice from a single RTC compare match
          [183] PWM: False SEQEND[0] and SEQEND[1] events
          [184] NVMC: Erase or write operations from the external debugger fail when CPU is not halted
          [187] USBD: USB cannot be enabled
          [190] NFCT: Event FIELDDETECTED may be generated too early
          [191] RADIO: High packet error rate in BLE Long Range mode
          [193] SPIM: SPIM3 does not generate EVENTS_END and halts if suspended during last byte
          [194] I2S: STOP task does not switch off all resources
          [195] SPIM: SPIM3 continues to draw current after disable
          [196] I2S: PSEL acquires GPIOs regardless of ENABLE
          [198] SPIM: SPIM3 transmit data might be corrupted
          [199] USBD: USBD cannot receive tasks during DMA
          [204] RADIO: Switching beween TX and RX causes unwanted emissions
          [208] QSPI: PPI Deactivate task does not switch off all resources
          [209] CLOCK: LFRC ULP mode calibration not functional
          [210] GPIO: Bits in GPIO LATCH register are incorrectly set to 1
      nRF52840 Engineering D Errata
        Change log
        New and inherited anomalies
          [20] RTC: Register values are invalid
          [36] CLOCK: Some registers are not reset when expected
          [55] I2S: RXPTRUPD and TXPTRUPD events asserted after STOP
          [66] TEMP: Linearity specification not met with default settings
          [78] TIMER: High current consumption when using timer STOP task only
          [81] GPIO: PIN_CNF is not retained when in debug interface mode
          [87] CPU: Unexpected wake from System ON Idle when using FPU
          [122] QSPI: QSPI uses current after being disabled
          [136] System: Bits in RESETREAS are set when they should not be
          [153] RADIO: RSSI parameter adjustment
          [155] GPIOTE: IN event may occur more than once on input edge
          [166] USBD: ISO double buffering not functional
          [170] I2S: NRF_I2S->PSEL CONNECT fields are not readable
          [171] USB,USBD: USB might not power up
          [172] RADIO: BLE long range co-channel performance
          [173] GPIO: Writes to LATCH register take several CPU cycles to take effect
          [174] SPIM: SPIM3 events incorrectly connected to the PPI
          [176] System: Flash erase through CTRL-AP fails due to watchdog time-out
          [179] RTC: COMPARE event is generated twice from a single RTC compare match
          [183] PWM: False SEQEND[0] and SEQEND[1] events
          [184] NVMC: Erase or write operations from the external debugger fail when CPU is not halted
          [187] USBD: USB cannot be enabled
          [190] NFCT: Event FIELDDETECTED may be generated too early
          [191] RADIO: High packet error rate in BLE Long Range mode
          [193] SPIM: SPIM3 does not generate EVENTS_END and halts if suspended during last byte
          [194] I2S: STOP task does not switch off all resources
          [195] SPIM: SPIM3 continues to draw current after disable
          [196] I2S: PSEL acquires GPIOs regardless of ENABLE
          [198] SPIM: SPIM3 transmit data might be corrupted
          [199] USBD: USBD cannot receive tasks during DMA
          [204] RADIO: Switching beween TX and RX causes unwanted emissions
          [208] QSPI: PPI Deactivate task does not switch off all resources
          [209] CLOCK: LFRC ULP mode calibration not functional
          [210] GPIO: Bits in GPIO LATCH register are incorrectly set to 1
        Fixed anomalies
      nRF52840 Rev 1 Errata
        Change log
        New and inherited anomalies
          [20] RTC: Register values are invalid
          [36] CLOCK: Some registers are not reset when expected
          [55] I2S: RXPTRUPD and TXPTRUPD events asserted after STOP
          [66] TEMP: Linearity specification not met with default settings
          [78] TIMER: High current consumption when using timer STOP task only
          [81] GPIO: PIN_CNF is not retained when in debug interface mode
          [87] CPU: Unexpected wake from System ON Idle when using FPU
          [122] QSPI: QSPI uses current after being disabled
          [136] System: Bits in RESETREAS are set when they should not be
          [153] RADIO: RSSI parameter adjustment
          [155] GPIOTE: IN event may occur more than once on input edge
          [166] USBD: ISO double buffering not functional
          [170] I2S: NRF_I2S->PSEL CONNECT fields are not readable
          [171] USB,USBD: USB might not power up
          [172] RADIO: BLE long range co-channel performance
          [173] GPIO: Writes to LATCH register take several CPU cycles to take effect
          [174] SPIM: SPIM3 events incorrectly connected to the PPI
          [176] System: Flash erase through CTRL-AP fails due to watchdog time-out
          [179] RTC: COMPARE event is generated twice from a single RTC compare match
          [183] PWM: False SEQEND[0] and SEQEND[1] events
          [184] NVMC: Erase or write operations from the external debugger fail when CPU is not halted
          [187] USBD: USB cannot be enabled
          [190] NFCT: Event FIELDDETECTED may be generated too early
          [191] RADIO: High packet error rate in BLE Long Range mode
          [192] CLOCK: LFRC frequency offset after calibration
          [193] SPIM: SPIM3 does not generate EVENTS_END and halts if suspended during last byte
          [194] I2S: STOP task does not switch off all resources
          [195] SPIM: SPIM3 continues to draw current after disable
          [196] I2S: PSEL acquires GPIOs regardless of ENABLE
          [197] POWER: DCDC of REG0 not functional
          [198] SPIM: SPIM3 transmit data might be corrupted
          [199] USBD: USBD cannot receive tasks during DMA
          [201] CLOCK: EVENTS_HFCLKSTARTED might be generated twice
          [202] POWER: Device does not start up in high voltage mode
          [204] RADIO: Switching beween TX and RX causes unwanted emissions
          [208] QSPI: PPI Deactivate task does not switch off all resources
          [209] CLOCK: LFRC ULP mode calibration not functional
          [210] GPIO: Bits in GPIO LATCH register are incorrectly set to 1
      nRF52840 Engineering C Errata
        Change log
        New and inherited anomalies
          [20] RTC: Register values are invalid
          [36] CLOCK: Some registers are not reset when expected
          [55] I2S: RXPTRUPD and TXPTRUPD events asserted after STOP
          [66] TEMP: Linearity specification not met with default settings
          [78] TIMER: High current consumption when using timer STOP task only
          [81] GPIO: PIN_CNF is not retained when in debug interface mode
          [87] CPU: Unexpected wake from System ON Idle when using FPU
          [122] QSPI: QSPI uses current after being disabled
          [136] System: Bits in RESETREAS are set when they should not be
          [153] RADIO: RSSI parameter adjustment
          [155] GPIOTE: IN event may occur more than once on input edge
          [166] USBD: ISO double buffering not functional
          [170] I2S: NRF_I2S->PSEL CONNECT fields are not readable
          [171] USB,USBD: USB might not power up
          [173] GPIO: Writes to LATCH register take several CPU cycles to take effect
          [174] SPIM: SPIM3 events incorrectly connected to the PPI
          [176] System: Flash erase through CTRL-AP fails due to watchdog time-out
          [179] RTC: COMPARE event is generated twice from a single RTC compare match
          [183] PWM: False SEQEND[0] and SEQEND[1] events
          [184] NVMC: Erase or write operations from the external debugger fail when CPU is not halted
          [187] USBD: USB cannot be enabled
          [190] NFCT: Event FIELDDETECTED may be generated too early
          [191] RADIO: High packet error rate in BLE Long Range mode
          [192] CLOCK: LFRC frequency offset after calibration
          [193] SPIM: SPIM3 does not generate EVENTS_END and halts if suspended during last byte
          [194] I2S: STOP task does not switch off all resources
          [195] SPIM: SPIM3 continues to draw current after disable
          [196] I2S: PSEL acquires GPIOs regardless of ENABLE
          [197] POWER: DCDC of REG0 not functional
          [198] nRF52840: SPIM3 transmit data might be corrupted
          [201] CLOCK: EVENTS_HFCLKSTARTED might be generated twice
          [202] POWER: Device does not start up in high voltage mode
        Fixed anomalies
      nRF52840 Engineering B Errata
        Change log
        New and inherited anomalies
          [20] RTC: Register values are invalid
          [36] CLOCK: Some registers are not reset when expected
          [55] I2S: RXPTRUPD and TXPTRUPD events asserted after STOP
          [66] TEMP: Linearity specification not met with default settings
          [78] TIMER: High current consumption when using timer STOP task only
          [81] GPIO: PIN_CNF is not retained when in debug interface mode
          [87] CPU: Unexpected wake from System ON Idle when using FPU
          [94] USBD: BUSSTATE register is not functional
          [122] QSPI: QSPI uses current after being disabled
          [136] System: Bits in RESETREAS are set when they should not be
          [153] RADIO: RSSI parameter adjustment
          [155] GPIOTE: IN event may occur more than once on input edge
          [166] USBD: ISO double buffering not functional
          [170] I2S: NRF_I2S->PSEL CONNECT fields are not readable
          [171] USB,USBD: USB might not power up
          [173] GPIO: Writes to LATCH register take several CPU cycles to take effect
          [174] SPIM: SPIM3 events incorrectly connected to the PPI
          [176] System: Flash erase through CTRL-AP fails due to watchdog time-out
          [179] RTC: COMPARE event is generated twice from a single RTC compare match
          [183] PWM: False SEQEND[0] and SEQEND[1] events
          [184] NVMC: Erase or write operations from the external debugger fail when CPU is not halted
          [186] POWER: High current consumption in System ON Idle, using High Voltage mode
          [187] USBD: USB cannot be enabled
          [189] SPIM: RX buffer error at 32 MHz operation
          [190] NFCT: Event FIELDDETECTED may be generated too early
          [191] RADIO: High packet error rate in BLE Long Range mode
          [192] CLOCK: LFRC frequency offset after calibration
          [193] SPIM: SPIM3 does not generate EVENTS_END and halts if suspended during last byte
          [194] I2S: STOP task does not switch off all resources
          [195] SPIM: SPIM3 continues to draw current after disable
          [196] I2S: PSEL acquires GPIOs regardless of ENABLE
          [198] nRF52840: SPIM3 transmit data might be corrupted
          [201] CLOCK: EVENTS_HFCLKSTARTED might be generated twice
          [202] POWER: Device does not start up in high voltage mode
        Fixed anomalies
      nRF52840 Engineering A Errata
        Change log
        New and inherited anomalies
          [15] POWER: RAM[x].POWERSET/CLR read as zero
          [20] RTC: Register values are invalid
          [36] CLOCK: Some registers are not reset when expected
          [54] I2S: Wrong LRCK polarity in Aligned mode
          [55] I2S: RXPTRUPD and TXPTRUPD events asserted after STOP
          [58] SPIM: An additional byte is clocked out when RXD.MAXCNT = 1
          [66] TEMP: Linearity specification not met with default settings
          [68] CLOCK: EVENTS_HFCLKSTARTED can be generated before HFCLK is stable
          [78] TIMER: High current consumption when using timer STOP task only
          [81] GPIO: PIN_CNF is not retained when in debug interface mode
          [83] TWIS: STOPPED event occurs twice if the STOP task is triggered during a transaction
          [87] CPU: Unexpected wake from System ON Idle when using FPU
          [89] GPIOTE: Static 400 µA current while using GPIOTE
          [94] USBD: BUSSTATE register is not functional
          [96] I2S: DMA buffers can only be located in the first 64 kB of data RAM
          [97] GPIOTE: High current consumption in System ON Idle mode
          [98] NFCT: Not able to communicate with the peer
          [103] CCM: Reset value of CCM.MAXPACKETSIZE causes encryption, decryption, and MIC failures
          [104] USBD: EPDATA event is not always generated
          [110] RADIO: Packet loss or degraded sensitivity
          [111] RAM: Retention in OFF mode is not controlled by RAM[n].POWER->SxRETENTION, but by RAM[n].POWER->SxPOWER
          [112] RADIO: False SFD field matches in IEEE 802.15.4 mode RX
          [113] COMP: Single-ended mode with external reference is not functional
          [115] RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode
          [116] NFCT: HFCLK not stopped when entering into SENSE_FIELD state
          [117] System: Reading address 0x40029618 blocks the device
          [118] QSPI: Reading halfwords or bytes from the XIP region is not supported
          [119] POWER: Wake up from System OFF on VBUS detect is not functional
          [121] QSPI: Second read and long read commands fail
          [122] QSPI: QSPI uses current after being disabled
          [127] UARTE: Two stop bit setting is not functional
          [128] PDM: RATIO register is not functional
          [131] UARTE: EasyDMA transfer size is limited to 255 bytes
          [133] CLOCK,RADIO: NRF_RADIO->EVENTS_BCMATCH event might trigger twice
          [134] USBD: ISOINCONFIG register is not functional
          [135] USBD: SIZE.ISOOUT register does not report empty incoming packets
          [136] System: Bits in RESETREAS are set when they should not be
          [140] POWER: REG0 External circuitry supply in LDO mode is not functional in System ON IDLE
          [142] RADIO: Sensitivity not according to specification
          [143] RADIO: False CRC failures on specific addresses
          [144] NFCT: Not optimal NFC performance
          [145] SPIM: SPIM3 not functional
          [147] CLOCK: LFRC ULP mode not calibrated in production
          [150] SAADC: EVENT_STARTED does not fire
          [151] NVMC: Access to protected memory through Cache
          [153] RADIO: RSSI parameter adjustment
          [154] USBD: USBD acknowledges setup stage without STATUS task
          [155] GPIOTE: IN event may occur more than once on input edge
          [156] GPIOTE: Some CLR tasks give unintentional behavior
          [158] RADIO: High power consumption in DISABLED state
          [160] SAADC: VDDHDIV5 not functional
          [162] USBD: Writing to registers with offset address 0x52C causes USB to halt
          [164] RADIO: Low selectivity in long range mode
          [166] USBD: ISO double buffering not functional
          [170] I2S: NRF_I2S->PSEL CONNECT fields are not readable
          [171] USB,USBD: USB might not power up
          [173] GPIO: Writes to LATCH register take several CPU cycles to take effect
          [176] System: Flash erase through CTRL-AP fails due to watchdog time-out
          [179] RTC: COMPARE event is generated twice from a single RTC compare match
          [180] USBD: Wrong PLL calibration in production
          [181] NFCT: Invalid value in FICR for double-size NFCID1
          [183] PWM: False SEQEND[0] and SEQEND[1] events
          [184] NVMC: Erase or write operations from the external debugger fail when CPU is not halted
          [192] CLOCK: LFRC frequency offset after calibration
          [194] I2S: STOP task does not switch off all resources
          [196] I2S: PSEL acquires GPIOs regardless of ENABLE
          [200] USBD: Cannot write to SIZE.EPOUT register
          [201] CLOCK: EVENTS_HFCLKSTARTED might be generated twice
    PCN and IN
      PCN111 Product Change Notification v1.0
    Compatibility Matrix
      IC revisions and variants
      Documentation and reference design files
      SDKs and SoftDevices
      Development HW
      Bluetooth Low Energy QDIDs
      Revision history
    nRF52840 Development Kit
      Revision history
      Minimum requirements
      Kit content
        Hardware content
        Downloadable content
        Related documentation
      Getting started
      Nordic tools and downloads
      Start developing
      Interface MCU
        IF Boot/Reset button
        Virtual COM port
          Dynamic HWFC handling
        MSD
      Hardware description
        Hardware drawings
        Block diagram
        Power supply
          5 V power sources
          VDD power sources
          Interface MCU power
          nRF52840 power source
          nRF52840 direct supply
        Operating modes
          USB detect
          nRF only mode
          Signal switches
        External memory
        Connector interface
          Mapping of analog pins
        Buttons and LEDs
        32.768 kHz crystal
        Debug input and trace
        Debug output
        NFC antenna interface
        Extra op-amp
        Solder bridge configuration
      Measuring current
        Preparing the development kit board
        Using an oscilloscope for current profile measurement
        Using an ampere-meter for current measurement
      RF measurements
      Glossary
        Clear to Send (CTS)
        Data Terminal Ready (DTR)
        DK (Development Kit)
        Hardware Flow Control (HWFC)
        Integrated Development Environment (IDE)
        Mass Storage Device (MSD)
        Near Field Communication (NFC)
        NFC-A Listen Mode
        Operational Amplifier (op-amp)
        Receive Data (RXD)
        Request to Send (RTS)
        Root Mean Square (RMS)
        SubMiniature Version A (SMA) Connector
        System on Chip (SoC)
        Transmit Data (TXD)
      Acronyms and abbreviations
      Legal notices
    nRF52840 Dongle
      Revision history
      Minimum requirements
      Kit content
        Hardware content
        Downloadable content
        Related documentation
      Getting started
      Programming
      Hardware description
        Hardware drawings
        Block diagram
        Power supply
          Internal regulator
          External regulated source
        Buttons and LEDs
        32.768 kHz crystal
        USB
        SWD interface
        External connections
      Legal notices
  nRF52832
    nRF52832 Product Specification
      Revision history
      About this document
        Document naming and status
        Peripheral naming and abbreviations
        Register tables
          Fields and values
         Registers
           DUMMY
      Block diagram
      Pin assignments
        QFN48 pin assignments
        WLCSP ball assignments
        GPIO usage restrictions
          GPIO located near the radio
          NFC antenna pins
      Absolute maximum ratings
      Recommended operating conditions
        WLCSP light sensitivity
      CPU
        Floating point interrupt
         Electrical specification
           CPU performance
        CPU and support module configuration
      Memory
        RAM - Random access memory
        Flash - Non-volatile memory
        Memory map
         Instantiation
      AHB multilayer
        AHB multilayer priorities
      EasyDMA
        EasyDMA array list
      NVMC — Non-volatile memory controller
        Writing to Flash
        Erasing a page in Flash
        Writing to user information configuration registers (UICR)
        Erasing user information configuration registers (UICR)
        Erase all
        Cache
         Registers
           READY
           CONFIG
           ERASEPAGE
           ERASEPCR1 ( Deprecated )
           ERASEALL
           ERASEPCR0 ( Deprecated )
           ERASEUICR
           ICACHECNF
           IHIT
           IMISS
         Electrical specification
           Flash programming
           Cache size
      BPROT — Block protection
         Registers
           CONFIG0
           CONFIG1
           DISABLEINDEBUG
           CONFIG2
           CONFIG3
      FICR — Factory information configuration registers
         Registers
           CODEPAGESIZE
           CODESIZE
           DEVICEID[0]
           DEVICEID[1]
           ER[0]
           ER[1]
           ER[2]
           ER[3]
           IR[0]
           IR[1]
           IR[2]
           IR[3]
           DEVICEADDRTYPE
           DEVICEADDR[0]
           DEVICEADDR[1]
           INFO.PART
           INFO.VARIANT
           INFO.PACKAGE
           INFO.RAM
           INFO.FLASH
           TEMP.A0
           TEMP.A1
           TEMP.A2
           TEMP.A3
           TEMP.A4
           TEMP.A5
           TEMP.B0
           TEMP.B1
           TEMP.B2
           TEMP.B3
           TEMP.B4
           TEMP.B5
           TEMP.T0
           TEMP.T1
           TEMP.T2
           TEMP.T3
           TEMP.T4
           NFC.TAGHEADER0
           NFC.TAGHEADER1
           NFC.TAGHEADER2
           NFC.TAGHEADER3
      UICR — User information configuration registers
         Registers
           NRFFW[0]
           NRFFW[1]
           NRFFW[2]
           NRFFW[3]
           NRFFW[4]
           NRFFW[5]
           NRFFW[6]
           NRFFW[7]
           NRFFW[8]
           NRFFW[9]
           NRFFW[10]
           NRFFW[11]
           NRFFW[12]
           NRFFW[13]
           NRFFW[14]
           NRFHW[0]
           NRFHW[1]
           NRFHW[2]
           NRFHW[3]
           NRFHW[4]
           NRFHW[5]
           NRFHW[6]
           NRFHW[7]
           NRFHW[8]
           NRFHW[9]
           NRFHW[10]
           NRFHW[11]
           CUSTOMER[0]
           CUSTOMER[1]
           CUSTOMER[2]
           CUSTOMER[3]
           CUSTOMER[4]
           CUSTOMER[5]
           CUSTOMER[6]
           CUSTOMER[7]
           CUSTOMER[8]
           CUSTOMER[9]
           CUSTOMER[10]
           CUSTOMER[11]
           CUSTOMER[12]
           CUSTOMER[13]
           CUSTOMER[14]
           CUSTOMER[15]
           CUSTOMER[16]
           CUSTOMER[17]
           CUSTOMER[18]
           CUSTOMER[19]
           CUSTOMER[20]
           CUSTOMER[21]
           CUSTOMER[22]
           CUSTOMER[23]
           CUSTOMER[24]
           CUSTOMER[25]
           CUSTOMER[26]
           CUSTOMER[27]
           CUSTOMER[28]
           CUSTOMER[29]
           CUSTOMER[30]
           CUSTOMER[31]
           PSELRESET[0]
           PSELRESET[1]
           APPROTECT
           NFCPINS
      Peripheral interface
        Peripheral ID
        Peripherals with shared ID
        Peripheral registers
        Bit set and clear
        Tasks
        Events
        Shortcuts
        Interrupts
      Debug and trace
        DAP - Debug Access Port
        CTRL-AP - Control Access Port
           Registers
             RESET
             ERASEALL
             ERASEALLSTATUS
             APPROTECTSTATUS
             IDR
        Debug interface mode
        Real-time debug
        Trace
           Electrical specification
             Trace port
      Power and clock management
        Current consumption scenarios
           Electrical specification
             Current consumption: Radio
             Current consumption: Radio protocol configurations
             Current consumption: Ultra-low power
      POWER — Power supply
        Regulators
        System OFF mode
          Emulated System OFF mode
        System ON mode
          Sub power modes
        Power supply supervisor
          Power-fail comparator
        RAM sections
        Reset
          Power-on reset
          Pin reset
          Wakeup from System OFF mode reset
          Soft reset
          Watchdog reset
          Brown-out reset
        Retained registers
        Reset behavior
         Registers
           INTENSET
           INTENCLR
           RESETREAS
           RAMSTATUS ( Deprecated )
           SYSTEMOFF
           POFCON
           GPREGRET
           GPREGRET2
           RAMON ( Deprecated )
           RAMONB ( Deprecated )
           DCDCEN
           RAM[0].POWER
           RAM[0].POWERSET
           RAM[0].POWERCLR
           RAM[1].POWER
           RAM[1].POWERSET
           RAM[1].POWERCLR
           RAM[2].POWER
           RAM[2].POWERSET
           RAM[2].POWERCLR
           RAM[3].POWER
           RAM[3].POWERSET
           RAM[3].POWERCLR
           RAM[4].POWER
           RAM[4].POWERSET
           RAM[4].POWERCLR
           RAM[5].POWER
           RAM[5].POWERSET
           RAM[5].POWERCLR
           RAM[6].POWER
           RAM[6].POWERSET
           RAM[6].POWERCLR
           RAM[7].POWER
           RAM[7].POWERSET
           RAM[7].POWERCLR
         Electrical specification
           Current consumption, sleep
           Device startup times
           Power fail comparator
      CLOCK — Clock control
        HFCLK clock controller
          64 MHz crystal oscillator (HFXO)
        LFCLK clock controller
          32.768 kHz RC oscillator (LFRC)
          Calibrating the 32.768 kHz RC oscillator
          Calibration timer
          32.768 kHz crystal oscillator (LFXO)
          32.768 kHz synthesized from HFCLK (LFSYNT)
         Registers
           INTENSET
           INTENCLR
           HFCLKRUN
           HFCLKSTAT
           LFCLKRUN
           LFCLKSTAT
           LFCLKSRCCOPY
           LFCLKSRC
           CTIV ( Retained )
           TRACECONFIG
         Electrical specification
           64 MHz internal oscillator (HFINT)
           64 MHz crystal oscillator (HFXO)
           32.768 kHz RC oscillator (LFRC)
           32.768 kHz crystal oscillator (LFXO)
           32.768 kHz synthesized from HFCLK (LFSYNT)
      GPIO — General purpose input/output
        Pin configuration
        GPIO located near the RADIO
         Registers
           OUT
           OUTSET
           OUTCLR
           IN
           DIR
           DIRSET
           DIRCLR
           LATCH
           DETECTMODE
           PIN_CNF[0]
           PIN_CNF[1]
           PIN_CNF[2]
           PIN_CNF[3]
           PIN_CNF[4]
           PIN_CNF[5]
           PIN_CNF[6]
           PIN_CNF[7]
           PIN_CNF[8]
           PIN_CNF[9]
           PIN_CNF[10]
           PIN_CNF[11]
           PIN_CNF[12]
           PIN_CNF[13]
           PIN_CNF[14]
           PIN_CNF[15]
           PIN_CNF[16]
           PIN_CNF[17]
           PIN_CNF[18]
           PIN_CNF[19]
           PIN_CNF[20]
           PIN_CNF[21]
           PIN_CNF[22]
           PIN_CNF[23]
           PIN_CNF[24]
           PIN_CNF[25]
           PIN_CNF[26]
           PIN_CNF[27]
           PIN_CNF[28]
           PIN_CNF[29]
           PIN_CNF[30]
           PIN_CNF[31]
         Electrical specification
           GPIO Electrical Specification
      GPIOTE — GPIO tasks and events
        Pin events and tasks
        Port event
        Tasks and events pin configuration
         Registers
           INTENSET
           INTENCLR
           CONFIG[0]
           CONFIG[1]
           CONFIG[2]
           CONFIG[3]
           CONFIG[4]
           CONFIG[5]
           CONFIG[6]
           CONFIG[7]
         Electrical specification
           GPIOTE Electrical Specification
      PPI — Programmable peripheral interconnect
        Pre-programmed channels
         Registers
           CHEN
           CHENSET
           CHENCLR
           CH[0].EEP
           CH[0].TEP
           CH[1].EEP
           CH[1].TEP
           CH[2].EEP
           CH[2].TEP
           CH[3].EEP
           CH[3].TEP
           CH[4].EEP
           CH[4].TEP
           CH[5].EEP
           CH[5].TEP
           CH[6].EEP
           CH[6].TEP
           CH[7].EEP
           CH[7].TEP
           CH[8].EEP
           CH[8].TEP
           CH[9].EEP
           CH[9].TEP
           CH[10].EEP
           CH[10].TEP
           CH[11].EEP
           CH[11].TEP
           CH[12].EEP
           CH[12].TEP
           CH[13].EEP
           CH[13].TEP
           CH[14].EEP
           CH[14].TEP
           CH[15].EEP
           CH[15].TEP
           CH[16].EEP
           CH[16].TEP
           CH[17].EEP
           CH[17].TEP
           CH[18].EEP
           CH[18].TEP
           CH[19].EEP
           CH[19].TEP
           CHG[0]
           CHG[1]
           CHG[2]
           CHG[3]
           CHG[4]
           CHG[5]
           FORK[0].TEP
           FORK[1].TEP
           FORK[2].TEP
           FORK[3].TEP
           FORK[4].TEP
           FORK[5].TEP
           FORK[6].TEP
           FORK[7].TEP
           FORK[8].TEP
           FORK[9].TEP
           FORK[10].TEP
           FORK[11].TEP
           FORK[12].TEP
           FORK[13].TEP
           FORK[14].TEP
           FORK[15].TEP
           FORK[16].TEP
           FORK[17].TEP
           FORK[18].TEP
           FORK[19].TEP
           FORK[20].TEP
           FORK[21].TEP
           FORK[22].TEP
           FORK[23].TEP
           FORK[24].TEP
           FORK[25].TEP
           FORK[26].TEP
           FORK[27].TEP
           FORK[28].TEP
           FORK[29].TEP
           FORK[30].TEP
           FORK[31].TEP
      RADIO — 2.4 GHz Radio
        EasyDMA
        Packet configuration
        Maximum packet length
        Address configuration
        Data whitening
        CRC
        Radio states
        Transmit sequence
        Receive sequence
        Received Signal Strength Indicator (RSSI)
        Interframe spacing
        Device address match
        Bit counter
         Registers
           SHORTS
           INTENSET
           INTENCLR
           CRCSTATUS
           RXMATCH
           RXCRC
           DAI
           PACKETPTR
           FREQUENCY
           TXPOWER
           MODE
           PCNF0
           PCNF1
           BASE0
           BASE1
           PREFIX0
           PREFIX1
           TXADDRESS
           RXADDRESSES
           CRCCNF
           CRCPOLY
           CRCINIT
           TIFS
           RSSISAMPLE
           STATE
           DATAWHITEIV
           BCC
           DAB[0]
           DAB[1]
           DAB[2]
           DAB[3]
           DAB[4]
           DAB[5]
           DAB[6]
           DAB[7]
           DAP[0]
           DAP[1]
           DAP[2]
           DAP[3]
           DAP[4]
           DAP[5]
           DAP[6]
           DAP[7]
           DACNF
           MODECNF0
           POWER
         Electrical specification
           General Radio Characteristics
           Radio current consumption (Transmitter)
           Radio current consumption (Receiver)
           Transmitter specification
           Receiver operation
           RX selectivity
           RX intermodulation
           Radio timing
           Received Signal Strength Indicator (RSSI) specifications
           Jitter
           Delay when disabling the RADIO
      TIMER — Timer/counter
        Capture
        Compare
        Task delays
        Task priority
         Registers
           SHORTS
           INTENSET
           INTENCLR
           MODE
           BITMODE
           PRESCALER
           CC[0]
           CC[1]
           CC[2]
           CC[3]
           CC[4]
           CC[5]
         Electrical specification
           Timers Electrical Specification
      RTC — Real-time counter
        Clock source
        Resolution versus overflow and the PRESCALER
        COUNTER register
        Overflow features
        TICK event
        Event control feature
        Compare feature
        TASK and EVENT jitter/delay
        Reading the COUNTER register
         Registers
           INTENSET
           INTENCLR
           EVTEN
           EVTENSET
           EVTENCLR
           COUNTER
           PRESCALER
           CC[0]
           CC[1]
           CC[2]
           CC[3]
         Electrical specification
           RTC Electrical Specification
      RNG — Random number generator
        Bias correction
        Speed
         Registers
           SHORTS
           INTENSET
           INTENCLR
           CONFIG
           VALUE
         Electrical specification
           RNG Electrical Specification
      TEMP — Temperature sensor
         Registers
           INTENSET
           INTENCLR
           TEMP
           A0
           A1
           A2
           A3
           A4
           A5
           B0
           B1
           B2
           B3
           B4
           B5
           T0
           T1
           T2
           T3
           T4
         Electrical specification
           Temperature Sensor Electrical Specification
      ECB — AES electronic codebook mode encryption
        Shared resources
        EasyDMA
        ECB data structure
         Registers
           INTENSET
           INTENCLR
           ECBDATAPTR
         Electrical specification
           ECB Electrical Specification
      CCM — AES CCM mode encryption
        Shared resources
        Encryption
        Decryption
        AES CCM and RADIO concurrent operation
        Encrypting packets on-the-fly in radio transmit mode
        Decrypting packets on-the-fly in radio receive mode
        CCM data structure
        EasyDMA and ERROR event
         Registers
           SHORTS
           INTENSET
           INTENCLR
           MICSTATUS
           ENABLE
           MODE
           CNFPTR
           INPTR
           OUTPTR
           SCRATCHPTR
      AAR — Accelerated address resolver
        Shared resources
        EasyDMA
        Resolving a resolvable address
        Use case example for chaining RADIO packet reception with address resolution using AAR
        IRK data structure
         Registers
           INTENSET
           INTENCLR
           STATUS
           ENABLE
           NIRK
           IRKPTR
           ADDRPTR
           SCRATCHPTR
         Electrical specification
           AAR Electrical Specification
      SPIM — Serial peripheral interface master with EasyDMA
        Shared resources
        EasyDMA
          EasyDMA list
            EasyDMA array list
        SPI master transaction sequence
        Low power
        Master mode pin configuration
         Registers
           SHORTS
           INTENSET
           INTENCLR
           ENABLE
           PSEL.SCK
           PSEL.MOSI
           PSEL.MISO
           FREQUENCY
           RXD.PTR
           RXD.MAXCNT
           RXD.AMOUNT
           RXD.LIST
           TXD.PTR
           TXD.MAXCNT
           TXD.AMOUNT
           TXD.LIST
           CONFIG
           ORC
         Electrical specification
           SPIM master interface electrical specifications
           Serial Peripheral Interface Master (SPIM) timing specifications
      SPIS — Serial peripheral interface slave with EasyDMA
        Shared resources
        EasyDMA
        SPI slave operation
        Pin configuration
         Registers
           SHORTS
           INTENSET
           INTENCLR
           SEMSTAT
           STATUS
           ENABLE
           PSELSCK ( Deprecated )
           PSELMISO ( Deprecated )
           PSELMOSI ( Deprecated )
           PSELCSN ( Deprecated )
           PSEL.SCK
           PSEL.MISO
           PSEL.MOSI
           PSEL.CSN
           RXDPTR ( Deprecated )
           MAXRX ( Deprecated )
           AMOUNTRX ( Deprecated )
           RXD.PTR
           RXD.MAXCNT
           RXD.AMOUNT
           TXDPTR ( Deprecated )
           MAXTX ( Deprecated )
           AMOUNTTX ( Deprecated )
           TXD.PTR
           TXD.MAXCNT
           TXD.AMOUNT
           CONFIG
           DEF
           ORC
         Electrical specification
           SPIS slave interface electrical specifications
           Serial Peripheral Interface Slave (SPIS) timing specifications
      TWIM — I2C compatible two-wire interface master with EasyDMA
        Shared resources
        EasyDMA
          EasyDMA list
            EasyDMA array list
        Master write sequence
        Master read sequence
        Master repeated start sequence
        Low power
        Master mode pin configuration
         Registers
           SHORTS
           INTEN
           INTENSET
           INTENCLR
           ERRORSRC
           ENABLE
           PSEL.SCL
           PSEL.SDA
           FREQUENCY
           RXD.PTR
           RXD.MAXCNT
           RXD.AMOUNT
           RXD.LIST
           TXD.PTR
           TXD.MAXCNT
           TXD.AMOUNT
           TXD.LIST
           ADDRESS
         Electrical specification
           TWIM interface electrical specifications
           Two Wire Interface Master (TWIM) timing specifications
      TWIS — I2C compatible two-wire interface slave with EasyDMA
        Shared resources
        EasyDMA
        TWI slave responding to a read command
        TWI slave responding to a write command
        Master repeated start sequence
        Terminating an ongoing TWI transaction
        Low power
        Slave mode pin configuration
         Registers
           SHORTS
           INTEN
           INTENSET
           INTENCLR
           ERRORSRC
           MATCH
           ENABLE
           PSEL.SCL
           PSEL.SDA
           RXD.PTR
           RXD.MAXCNT
           RXD.AMOUNT
           TXD.PTR
           TXD.MAXCNT
           TXD.AMOUNT
           ADDRESS[0]
           ADDRESS[1]
           CONFIG
           ORC
         Electrical specification
           TWIS slave interface electrical specifications
           TWIS slave timing specifications
      UARTE — Universal asynchronous receiver/transmitter with EasyDMA
        Shared resources
        EasyDMA
        Transmission
        Reception
        Error conditions
        Using the UARTE without flow control
        Parity configuration
        Low power
        Pin configuration
         Registers
           SHORTS
           INTEN
           INTENSET
           INTENCLR
           ERRORSRC
           ENABLE
           PSEL.RTS
           PSEL.TXD
           PSEL.CTS
           PSEL.RXD
           BAUDRATE
           RXD.PTR
           RXD.MAXCNT
           RXD.AMOUNT
           TXD.PTR
           TXD.MAXCNT
           TXD.AMOUNT
           CONFIG
         Electrical specification
           UARTE electrical specification
      QDEC — Quadrature decoder
        Sampling and decoding
        LED output
        Debounce filters
        Accumulators
        Output/input pins
        Pin configuration
         Registers
           SHORTS
           INTENSET
           INTENCLR
           ENABLE
           LEDPOL
           SAMPLEPER
           SAMPLE
           REPORTPER
           ACC
           ACCREAD
           PSEL.LED
           PSEL.A
           PSEL.B
           DBFEN
           LEDPRE
           ACCDBL
           ACCDBLREAD
         Electrical specification
           QDEC Electrical Specification
      SAADC — Successive approximation analog-to-digital converter
        Shared resources
        Overview
        Digital output
        Analog inputs and channels
        Operation modes
          One-shot mode
          Continuous mode
          Oversampling
          Scan mode
        EasyDMA
        Resistor ladder
        Reference
        Acquisition time
        Limits event monitoring
         Registers
           INTEN
           INTENSET
           INTENCLR
           STATUS
           ENABLE
           CH[0].PSELP
           CH[0].PSELN
           CH[0].CONFIG
           CH[0].LIMIT
           CH[1].PSELP
           CH[1].PSELN
           CH[1].CONFIG
           CH[1].LIMIT
           CH[2].PSELP
           CH[2].PSELN
           CH[2].CONFIG
           CH[2].LIMIT
           CH[3].PSELP
           CH[3].PSELN
           CH[3].CONFIG
           CH[3].LIMIT
           CH[4].PSELP
           CH[4].PSELN
           CH[4].CONFIG
           CH[4].LIMIT
           CH[5].PSELP
           CH[5].PSELN
           CH[5].CONFIG
           CH[5].LIMIT
           CH[6].PSELP
           CH[6].PSELN
           CH[6].CONFIG
           CH[6].LIMIT
           CH[7].PSELP
           CH[7].PSELN
           CH[7].CONFIG
           CH[7].LIMIT
           RESOLUTION
           OVERSAMPLE
           SAMPLERATE
           RESULT.PTR
           RESULT.MAXCNT
           RESULT.AMOUNT
         Electrical specification
           SAADC Electrical Specification
        Performance factors
      COMP — Comparator
        Differential mode
        Single-ended mode
         Registers
           SHORTS
           INTEN
           INTENSET
           INTENCLR
           RESULT
           ENABLE
           PSEL
           REFSEL
           EXTREFSEL
           TH
           MODE
           HYST
           ISOURCE
         Electrical specification
           COMP Electrical Specification
      LPCOMP — Low power comparator
        Shared resources
        Pin configuration
         Registers
           SHORTS
           INTENSET
           INTENCLR
           RESULT
           ENABLE
           PSEL
           REFSEL
           EXTREFSEL
           ANADETECT
           HYST
         Electrical specification
           LPCOMP Electrical Specification
      WDT — Watchdog timer
        Reload criteria
        Temporarily pausing the watchdog
        Watchdog reset
         Registers
           INTENSET
           INTENCLR
           RUNSTATUS
           REQSTATUS
           CRV
           RREN
           CONFIG
           RR[0]
           RR[1]
           RR[2]
           RR[3]
           RR[4]
           RR[5]
           RR[6]
           RR[7]
         Electrical specification
           Watchdog Timer Electrical Specification
      SWI — Software interrupts
         Registers
      NFCT — Near field communication tag
        Overview
        Pin configuration
        EasyDMA
        Collision resolution
        Frame timing controller
        Frame assembler
        Frame disassembler
        Antenna interface
        NFCT antenna recommendations
        Battery protection
         References
         Registers
           SHORTS
           INTEN
           INTENSET
           INTENCLR
           ERRORSTATUS
           FRAMESTATUS.RX
           CURRENTLOADCTRL
           FIELDPRESENT
           FRAMEDELAYMIN
           FRAMEDELAYMAX
           FRAMEDELAYMODE
           PACKETPTR
           MAXLEN
           TXD.FRAMECONFIG
           TXD.AMOUNT
           RXD.FRAMECONFIG
           RXD.AMOUNT
           NFCID1_LAST
           NFCID1_2ND_LAST
           NFCID1_3RD_LAST
           SENSRES
           SELRES
         Electrical specification
           NFCT Electrical Specification
           NFCT Timing Parameters
      PDM — Pulse density modulation interface
        Master clock generator
        Module operation
        Decimation filter
        EasyDMA
        Hardware example
        Pin configuration
         Registers
           INTEN
           INTENSET
           INTENCLR
           ENABLE
           PDMCLKCTRL
           MODE
           GAINL
           GAINR
           PSEL.CLK
           PSEL.DIN
           SAMPLE.PTR
           SAMPLE.MAXCNT
         Electrical specification
           PDM Electrical Specification
      I2S — Inter-IC sound interface
        Mode
        Transmitting and receiving
        Left right clock (LRCK)
        Serial clock (SCK)
        Master clock (MCK)
        Width, alignment and format
        EasyDMA
        Module operation
        Pin configuration
         Registers
           INTEN
           INTENSET
           INTENCLR
           ENABLE
           CONFIG.MODE
           CONFIG.RXEN
           CONFIG.TXEN
           CONFIG.MCKEN
           CONFIG.MCKFREQ
           CONFIG.RATIO
           CONFIG.SWIDTH
           CONFIG.ALIGN
           CONFIG.FORMAT
           CONFIG.CHANNELS
           RXD.PTR
           TXD.PTR
           RXTXD.MAXCNT
           PSEL.MCK
           PSEL.SCK
           PSEL.LRCK
           PSEL.SDIN
           PSEL.SDOUT
         Electrical specification
           I2S timing specification
      MWU — Memory watch unit
         Registers
           INTEN
           INTENSET
           INTENCLR
           NMIEN
           NMIENSET
           NMIENCLR
           PERREGION[0].SUBSTATWA
           PERREGION[0].SUBSTATRA
           PERREGION[1].SUBSTATWA
           PERREGION[1].SUBSTATRA
           REGIONEN
           REGIONENSET
           REGIONENCLR
           REGION[0].START
           REGION[0].END
           REGION[1].START
           REGION[1].END
           REGION[2].START
           REGION[2].END
           REGION[3].START
           REGION[3].END
           PREGION[0].START
           PREGION[0].END
           PREGION[0].SUBS
           PREGION[1].START
           PREGION[1].END
           PREGION[1].SUBS
      EGU — Event generator unit
         Registers
           INTEN
           INTENSET
           INTENCLR
         Electrical specification
           EGU Electrical Specification
      PWM — Pulse width modulation
        Wave counter
        Decoder with EasyDMA
        Limitations
        Pin configuration
         Registers
           SHORTS
           INTEN
           INTENSET
           INTENCLR
           ENABLE
           MODE
           COUNTERTOP
           PRESCALER
           DECODER
           LOOP
           SEQ[0].PTR
           SEQ[0].CNT
           SEQ[0].REFRESH
           SEQ[0].ENDDELAY
           SEQ[1].PTR
           SEQ[1].CNT
           SEQ[1].REFRESH
           SEQ[1].ENDDELAY
           PSEL.OUT[0]
           PSEL.OUT[1]
           PSEL.OUT[2]
           PSEL.OUT[3]
         Electrical specification
           PWM Electrical Specification
      SPI — Serial peripheral interface master
        Functional description
          SPI master mode pin configuration
          Shared resources
          SPI master transaction sequence
         Registers
           INTENSET
           INTENCLR
           ENABLE
           PSELSCK ( Deprecated )
           PSELMOSI ( Deprecated )
           PSELMISO ( Deprecated )
           PSEL.SCK
           PSEL.MOSI
           PSEL.MISO
           RXD
           TXD
           FREQUENCY
           CONFIG
         Electrical specification
           SPI master interface
           Serial Peripheral Interface (SPI) Master timing specifications
      TWI — I2C compatible two-wire interface
        Functional description
        Master mode pin configuration
        Shared resources
        Master write sequence
        Master read sequence
        Master repeated start sequence
        Low power
         Registers
           SHORTS
           INTENSET
           INTENCLR
           ERRORSRC
           ENABLE
           PSELSCL
           PSELSDA
           RXD
           TXD
           FREQUENCY
           ADDRESS
         Electrical specification
           TWI interface electrical specifications
           Two Wire Interface (TWI) timing specifications
      UART — Universal asynchronous receiver/transmitter
        Functional description
        Pin configuration
        Shared resources
        Transmission
        Reception
        Suspending the UART
        Error conditions
        Using the UART without flow control
        Parity configuration
         Registers
           SHORTS
           INTENSET
           INTENCLR
           ERRORSRC
           ENABLE
           PSELRTS
           PSELTXD
           PSELCTS
           PSELRXD
           RXD
           TXD
           BAUDRATE
           CONFIG
         Electrical specification
           UART electrical specification
      Mechanical specifications
        QFN48 6 x 6 mm package
        WLCSP package
      Ordering information
        IC marking
        Box labels
        Order code
        Code ranges and values
        Product options
      Reference circuitry
        Schematic QFAA and QFAB QFN48 with internal LDO setup
        Schematic QFAA and QFAB QFN48 with DC/DC regulator setup
        Schematic QFAA and QFAB QFN48 with DC/DC regulator and NFC setup
        Schematic CIAA WLCSP with internal LDO setup
        Schematic CIAA WLCSP with DC/DC regulator setup
        Schematic CIAA WLCSP with DC/DC regulator and NFC setup
        PCB guidelines
        PCB layout example
      Liability disclaimer
        RoHS and REACH statement
        Life support applications
    Errata
      nRF52832 Rev 2 Errata
        Change log
        New and inherited anomalies
          [12] COMP: Reference ladder is not correctly calibrated
          [15] POWER: RAM[x].POWERSET/CLR read as zero
          [20] RTC: Register values are invalid
          [31] CLOCK: Calibration values are not correctly loaded from FICR at reset
          [36] CLOCK: Some registers are not reset when expected
          [51] I2S: Aligned stereo slave mode does not work
          [54] I2S: Wrong LRCK polarity in Aligned mode
          [55] I2S: RXPTRUPD and TXPTRUPD events asserted after STOP
          [58] SPIM: An additional byte is clocked out when RXD.MAXCNT = 1
          [64] NFCT: Only full bytes can be received or transmitted, but supports 4-bit frame transmit
          [66] TEMP: Linearity specification not met with default settings
          [67] NFCT,PPI: Some events cannot be used with the PPI
          [68] CLOCK: EVENTS_HFCLKSTARTED can be generated before HFCLK is stable
          [72] NFCT,PPI: TASKS_ACTIVATE cannot be used with the PPI
          [74] SAADC: Started events fires prematurely
          [75] MWU: Increased current consumption
          [76] LPCOMP: READY event is set sooner than it should
          [77] CLOCK: RC oscillator is not calibrated when first started
          [78] TIMER: High current consumption when using timer STOP task only
          [79] NFCT: A false EVENTS_FIELDDETECTED event occurs after the field is lost
          [81] GPIO: PIN_CNF is not retained when in debug interface mode
          [83] TWIS: STOPPED event occurs twice if the STOP task is triggered during a transaction
          [84] COMP: ISOURCE not functional
          [86] SAADC: Triggering START task after offset calibration may write a sample to RAM
          [87] CPU: Unexpected wake from System ON Idle when using FPU
          [88] WDT: Increased current consumption when configured to pause in System ON idle
          [89] GPIOTE: Static 400 µA current while using GPIOTE
          [91] RADIO: Radio performance using CSP package version
          [97] GPIOTE: High current consumption in System ON Idle mode
          [101] CLOCK: Sleep current increases after soft reset
          [108] RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode
          [109] DMA: DMA access transfers might be corrupted
          [113] COMP: Single-ended mode with external reference is not functional
          [132] CLOCK: The LFRC oscillator might not start
          [136] System: Bits in RESETREAS are set when they should not be
          [138] RADIO: Spurious emission on GPIO exceeds limits in radiated tests
          [141] NFCT: HFCLK not stopped when entering SENSE mode
          [143] RADIO: False CRC failures on specific addresses
          [146] CLOCK: LFRC frequency deviation
          [149] TWIM: First clock pulse after clock stretching may be too long or too short
          [150] SAADC: EVENT_STARTED does not fire
          [155] GPIOTE: IN event may occur more than once on input edge
          [156] GPIOTE: Some CLR tasks give unintentional behavior
          [173] GPIO: Writes to LATCH register take several CPU cycles to take effect
          [176] System: Flash erase through CTRL-AP fails due to watchdog time-out
          [178] SAADC: END event firing too early
          [179] RTC: COMPARE event is generated twice from a single RTC compare match
          [182] RADIO: Fixes for anomalies #102, #106, and #107 do not take effect
          [183] PWM: False SEQEND[0] and SEQEND[1] events
          [192] CLOCK: LFRC frequency offset after calibration
          [194] I2S: STOP task does not switch off all resources
          [196] I2S: PSEL acquires GPIOs regardless of ENABLE
          [201] CLOCK: EVENTS_HFCLKSTARTED might be generated twice
          [204] RADIO: Switching beween TX and RX causes unwanted emissions
          [210] GPIO: Bits in GPIO LATCH register are incorrectly set to 1
        Fixed anomalies
      nRF52832 Rev 1 Errata
        Change log
        New and inherited anomalies
          [12] COMP: Reference ladder is not correctly calibrated
          [15] POWER: RAM[x].POWERSET/CLR read as zero
          [20] RTC: Register values are invalid
          [31] CLOCK: Calibration values are not correctly loaded from FICR at reset
          [36] CLOCK: Some registers are not reset when expected
          [51] I2S: Aligned stereo slave mode does not work
          [54] I2S: Wrong LRCK polarity in Aligned mode
          [55] I2S: RXPTRUPD and TXPTRUPD events asserted after STOP
          [58] SPIM: An additional byte is clocked out when RXD.MAXCNT = 1
          [64] NFCT: Only full bytes can be received or transmitted, but supports 4-bit frame transmit
          [66] TEMP: Linearity specification not met with default settings
          [67] NFCT,PPI: Some events cannot be used with the PPI
          [68] CLOCK: EVENTS_HFCLKSTARTED can be generated before HFCLK is stable
          [72] NFCT,PPI: TASKS_ACTIVATE cannot be used with the PPI
          [74] SAADC: Started events fires prematurely
          [75] MWU: Increased current consumption
          [76] LPCOMP: READY event is set sooner than it should
          [77] CLOCK: RC oscillator is not calibrated when first started
          [78] TIMER: High current consumption when using timer STOP task only
          [79] NFCT: A false EVENTS_FIELDDETECTED event occurs after the field is lost
          [81] GPIO: PIN_CNF is not retained when in debug interface mode
          [83] TWIS: STOPPED event occurs twice if the STOP task is triggered during a transaction
          [84] COMP: ISOURCE not functional
          [86] SAADC: Triggering START task after offset calibration may write a sample to RAM
          [87] CPU: Unexpected wake from System ON Idle when using FPU
          [88] WDT: Increased current consumption when configured to pause in System ON idle
          [89] GPIOTE: Static 400 µA current while using GPIOTE
          [91] RADIO: Radio performance using CSP package version
          [97] GPIOTE: High current consumption in System ON Idle mode
          [101] CLOCK: Sleep current increases after soft reset
          [102] RADIO: PAYLOAD/END events delayed or not triggered after ADDRESS
          [106] RADIO: Higher CRC error rates for some access addresses
          [107] RADIO: Immediate address match for access addresses containing MSBs 0x00
          [108] RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode
          [109] DMA: DMA access transfers might be corrupted
          [113] COMP: Single-ended mode with external reference is not functional
          [132] CLOCK: The LFRC oscillator might not start
          [136] System: Bits in RESETREAS are set when they should not be
          [138] RADIO: Spurious emission on GPIO exceeds limits in radiated tests
          [141] NFCT: HFCLK not stopped when entering SENSE mode
          [143] RADIO: False CRC failures on specific addresses
          [146] CLOCK: LFRC frequency deviation
          [149] TWIM: First clock pulse after clock stretching may be too long or too short
          [150] SAADC: EVENT_STARTED does not fire
          [155] GPIOTE: IN event may occur more than once on input edge
          [156] GPIOTE: Some CLR tasks give unintentional behavior
          [163] FICR: Code and RAM size fields do not match chip specification
          [173] GPIO: Writes to LATCH register take several CPU cycles to take effect
          [176] System: Flash erase through CTRL-AP fails due to watchdog time-out
          [178] SAADC: END event firing too early
          [179] RTC: COMPARE event is generated twice from a single RTC compare match
          [181] NFCT: Invalid value in FICR for double-size NFCID1
          [183] PWM: False SEQEND[0] and SEQEND[1] events
          [192] CLOCK: LFRC frequency offset after calibration
          [194] I2S: STOP task does not switch off all resources
          [196] I2S: PSEL acquires GPIOs regardless of ENABLE
          [201] CLOCK: EVENTS_HFCLKSTARTED might be generated twice
          [204] RADIO: Switching beween TX and RX causes unwanted emissions
          [210] GPIO: Bits in GPIO LATCH register are incorrectly set to 1
      nRF52832 Engineering C Errata
        Change log
        New and inherited anomalies
          [12] COMP: Reference ladder is not correctly calibrated
          [15] POWER: RAM[x].POWERSET/CLR read as zero
          [20] RTC: Register values are invalid
          [31] CLOCK: Calibration values are not correctly loaded from FICR at reset
          [36] CLOCK: Some registers are not reset when expected
          [51] I2S: Aligned stereo slave mode does not work
          [54] I2S: Wrong LRCK polarity in Aligned mode
          [55] I2S: RXPTRUPD and TXPTRUPD events asserted after STOP
          [58] SPIM: An additional byte is clocked out when RXD.MAXCNT = 1
          [64] NFCT: Only full bytes can be received or transmitted, but supports 4-bit frame transmit
          [66] TEMP: Linearity specification not met with default settings
          [67] NFCT,PPI: Some events cannot be used with the PPI
          [68] CLOCK: EVENTS_HFCLKSTARTED can be generated before HFCLK is stable
          [72] NFCT,PPI: TASKS_ACTIVATE cannot be used with the PPI
          [74] SAADC: Started events fires prematurely
          [75] MWU: Increased current consumption
          [76] LPCOMP: READY event is set sooner than it should
          [77] CLOCK: RC oscillator is not calibrated when first started
          [78] TIMER: High current consumption when using timer STOP task only
          [79] NFCT: A false EVENTS_FIELDDETECTED event occurs after the field is lost
          [81] GPIO: PIN_CNF is not retained when in debug interface mode
          [83] TWIS: STOPPED event occurs twice if the STOP task is triggered during a transaction
          [84] COMP: ISOURCE not functional
          [86] SAADC: Triggering START task after offset calibration may write a sample to RAM
          [87] CPU: Unexpected wake from System ON Idle when using FPU
          [88] WDT: Increased current consumption when configured to pause in System ON idle
          [89] GPIOTE: Static 400 µA current while using GPIOTE
          [91] RADIO: Radio performance using CSP package version
          [97] GPIOTE: High current consumption in System ON Idle mode
          [101] CLOCK: Sleep current increases after soft reset
          [102] RADIO: PAYLOAD/END events delayed or not triggered after ADDRESS
          [106] RADIO: Higher CRC error rates for some access addresses
          [107] RADIO: Immediate address match for access addresses containing MSBs 0x00
          [108] RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode
          [109] DMA: DMA access transfers might be corrupted
          [113] COMP: Single-ended mode with external reference is not functional
          [132] CLOCK: The LFRC oscillator might not start
          [136] System: Bits in RESETREAS are set when they should not be
          [138] RADIO: Spurious emission on GPIO exceeds limits in radiated tests
          [141] NFCT: HFCLK not stopped when entering SENSE mode
          [143] RADIO: False CRC failures on specific addresses
          [146] CLOCK: LFRC frequency deviation
          [149] TWIM: First clock pulse after clock stretching may be too long or too short
          [150] SAADC: EVENT_STARTED does not fire
          [155] GPIOTE: IN event may occur more than once on input edge
          [156] GPIOTE: Some CLR tasks give unintentional behavior
          [173] GPIO: Writes to LATCH register take several CPU cycles to take effect
          [176] System: Flash erase through CTRL-AP fails due to watchdog time-out
          [178] SAADC: END event firing too early
          [179] RTC: COMPARE event is generated twice from a single RTC compare match
          [183] PWM: False SEQEND[0] and SEQEND[1] events
          [192] CLOCK: LFRC frequency offset after calibration
          [194] I2S: STOP task does not switch off all resources
          [196] I2S: PSEL acquires GPIOs regardless of ENABLE
          [201] CLOCK: EVENTS_HFCLKSTARTED might be generated twice
        Fixed anomalies
      nRF52832 Engineering B Errata
        Change log
        New and inherited anomalies
          [12] COMP: Reference ladder is not correctly calibrated
          [15] POWER: RAM[x].POWERSET/CLR read as zero
          [20] RTC: Register values are invalid
          [31] CLOCK: Calibration values are not correctly loaded from FICR at reset
          [36] CLOCK: Some registers are not reset when expected
          [51] I2S: Aligned stereo slave mode does not work
          [54] I2S: Wrong LRCK polarity in Aligned mode
          [55] I2S: RXPTRUPD and TXPTRUPD events asserted after STOP
          [58] SPIM: An additional byte is clocked out when RXD.MAXCNT = 1
          [62] NFCT: Can draw current when not enabled
          [63] POWER: DC/DC does not automatically switch off in System ON IDLE
          [64] NFCT: Only full bytes can be received or transmitted, but supports 4-bit frame transmit
          [67] NFCT,PPI: Some events cannot be used with the PPI
          [68] CLOCK: EVENTS_HFCLKSTARTED can be generated before HFCLK is stable
          [70] COMP: Not able to wake CPU from System ON IDLE
          [71] CLOCK: RCOSC calibration
          [72] NFCT,PPI: TASKS_ACTIVATE cannot be used with the PPI
          [73] TIMER: Event lost
          [74] SAADC: Started events fires prematurely
          [75] MWU: Increased current consumption
          [76] LPCOMP: READY event is set sooner than it should
          [77] CLOCK: RC oscillator is not calibrated when first started
          [78] TIMER: High current consumption when using timer STOP task only
          [79] NFCT: A false EVENTS_FIELDDETECTED event occurs after the field is lost
          [81] GPIO: PIN_CNF is not retained when in debug interface mode
          [83] TWIS: STOPPED event occurs twice if the STOP task is triggered during a transaction
          [84] COMP: ISOURCE not functional
          [86] SAADC: Triggering START task after offset calibration may write a sample to RAM
          [87] CPU: Unexpected wake from System ON Idle when using FPU
          [88] WDT: Increased current consumption when configured to pause in System ON idle
          [89] TWI: Static 400 µA current while using GPIOTE
          [97] GPIOTE: High current consumption in System ON Idle mode
          [108] RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode
        Fixed anomalies
      nRF52832 Engineering A Errata
        Change log
        New and inherited anomalies
          [1] I2S: I2S not functional
          [2] PWM: PWM not functional
          [3] PDM: PDM not functional
          [4] MWU: MWU not functional
          [7] NVMC,System: Cache is not functional
          [8] SAADC: Increased current consumption in system ON-IDLE
          [9] QDEC: Some features are not functional
          [10] RTC: RTC2 is not functional
          [11] System: Device is unable to stay in System OFF mode
          [12] COMP: Reference ladder is not correctly calibrated
          [15] POWER: RAM[x].POWERSET/CLR read as zero
          [16] System: RAM may be corrupt on wakeup from CPU IDLE
          [17] NFCT: The EVENTS_FIELDLOST is not generated
          [20] RTC: Register values are invalid
          [23] SPIM: END event is generated before ENDTX
          [24] NFCT: The FIELDPRESENT register read is not reliable
          [25] NFCT: Reset value of SENSRES register is incorrect
          [26] NFCT: NFC field does not wakeup the device from emulated system OFF
          [27] NFCT: Triggering NFCT ACTIVATE task also activates the Rx easyDMA
          [28] SAADC: Scan mode is not functional for some analog inputs
          [29] TWIS: Incorrect bits in ERRORSRC
          [30] TWIS: STOP Task is not functional
          [31] CLOCK: Calibration values are not correctly loaded from FICR at reset
          [32] DIF: Debug session automatically enables TracePort pins
          [33] System: Code RAM is located at wrong address
          [34] System: Code and Data RAM are not mapped from the same physical RAM
          [35] CLOCK: HFCLK can draw current when not requested
          [36] CLOCK: Some registers are not reset when expected
          [37] RADIO: Encryption engine is slow by default.
          [38] PPI: Enable/disable tasks for channel group 4 and 5 cannot be triggered through PPI
          [39] NFCT: The automatic collision resolution does not handle CRC and parity errors
          [40] NFCT: The FRAMEDELAYMODE = WindowGrid is not supported
          [41] GPIO: PIN_CNF[x] registers not reset after pin reset
          [42] PPI: FORK on the fixed channels is not functional
          [43] SPIS: SPIS0 is not functional
          [44] NVMC: Read after flash erase is unpredictable
          [46] SPIM,TWIM: EasyDMA list not functional
          [47] DIF: Trace is not functional
          [48] DIF: SWO only works if Trace is enabled.
          [49] RTC: RTC is not functional after LFCLK is restarted
          [57] NFCT: NFC Modulation amplitude
          [58] SPIM: An additional byte is clocked out when RXD.MAXCNT = 1
          [63] POWER: DC/DC does not automatically switch off in System ON IDLE
          [64] NFCT: Only full bytes can be received or transmitted, but supports 4-bit frame transmit
          [65] POWER: RAM[] registers mapping of RAM block and sections is wrong
          [67] NFCT,PPI: Some events cannot be used with the PPI
          [68] CLOCK: EVENTS_HFCLKSTARTED can be generated before HFCLK is stable
          [70] COMP: Not able to wake CPU from System ON IDLE
          [71] CLOCK: RCOSC calibration
          [72] NFCT,PPI: TASKS_ACTIVATE cannot be used with the PPI
          [73] TIMER: Event lost
          [74] SAADC: Started events fires prematurely
          [77] CLOCK: RC oscillator is not calibrated when first started
          [78] TIMER: High current consumption when using timer STOP task only
          [84] COMP: ISOURCE not functional
          [86] SAADC: Triggering START task after offset calibration may write a sample to RAM
          [87] CPU: Unexpected wake from System ON Idle when using FPU
          [88] WDT: Increased current consumption when configured to pause in System ON idle
          [97] GPIOTE: High current consumption in System ON Idle mode
    Compatibility Matrix
      IC revisions and variants
      Documentation and reference design files
      SDKs and SoftDevices
      Development HW
      Bluetooth Low Energy QDIDs
      Revision history
    PCN and IN
      IN119 Informational Notice Security Vulnerability v1.0
      PCN106 Product Change Notification v1.0
      IN105 Informational Notice v1.0
      PCN104 Product Change Notification v1.0
      PCN103 Product Change Notification v1.0
    nRF52 Development Kit (for nRF52832 and nRF52810)
      Revision history
      Setting up the development kit
      Software tools
      Start developing
      Interface MCU
        IF Boot/Reset button
        Virtual COM port
          Dynamic Hardware Flow Control (HWFC) handling
        Interface MCU firmware
        MSD
      Hardware description
        Hardware drawings
        Block diagram
        Power supply
        Connector interface
        Buttons and LEDs
          I/O expander for buttons and LEDs
        32.768 kHz crystal
        Measuring current
          Preparing the development kit board
          Using an oscilloscope for current profile measurement
          Using an ampere-meter for current measurement
        RF measurements
        Debug input
        Debug output
        NFC antenna interface
        Solder bridge configuration
      Legal notices
    nRF52 Preview Development Kit (for nRF52832)
      Revision history
      Setting up the development kit
      Software tools
      Start developing
      Interface MCU
        IF Boot/Reset button
        Virtual COM port
        Interface MCU firmware (FW)
        MSD
      Hardware description
        Hardware drawings
        Block diagram
        Power supply
        Connector interface
        Buttons and LEDs
          I/O expander for buttons and LEDs
        32.768 kHz crystal
        Measuring current
        RF measurements
        Debug input
        Debug output
        NFC antenna interface
      Legal notices
  nRF52811
    nRF52811 Product Specification
      Revision history
      About this document
        Document naming and status
        Peripheral naming and abbreviations
        Register tables
          Fields and values
        Registers
          DUMMY
      Block diagram
      Core components
        CPU
          Electrical specification
            CPU performance
          CPU and support module configuration
        Memory
          RAM - Random access memory
          Flash - Non-volatile memory
          Memory map
          Instantiation
        NVMC — Non-volatile memory controller
          Writing to flash
          Erasing a page in flash
          Writing to user information configuration registers (UICR)
          Erasing user information configuration registers (UICR)
          Erase all
          Partial erase of a page in flash
          Registers
            READY
            CONFIG
            ERASEPAGE
            ERASEPCR1 ( Deprecated )
            ERASEALL
            ERASEPCR0 ( Deprecated )
            ERASEUICR
            ERASEPAGEPARTIAL
            ERASEPAGEPARTIALCFG
          Electrical specification
            Flash programming
        FICR — Factory information configuration registers
          Registers
            CODEPAGESIZE
            CODESIZE
            DEVICEID[n]
            ER[n]
            IR[n]
            DEVICEADDRTYPE
            DEVICEADDR[n]
            INFO.PART
            INFO.VARIANT
            INFO.PACKAGE
            INFO.RAM
            INFO.FLASH
            TEMP.A0
            TEMP.A1
            TEMP.A2
            TEMP.A3
            TEMP.A4
            TEMP.A5
            TEMP.B0
            TEMP.B1
            TEMP.B2
            TEMP.B3
            TEMP.B4
            TEMP.B5
            TEMP.T0
            TEMP.T1
            TEMP.T2
            TEMP.T3
            TEMP.T4
        UICR — User information configuration registers
          Registers
            NRFFW[n]
            NRFHW[n]
            CUSTOMER[n]
            PSELRESET[n]
            APPROTECT
        EasyDMA
          EasyDMA error handling
          EasyDMA array list
        AHB multilayer
        Debug
          DAP - Debug access port
          CTRL-AP - Control access port
            Registers
              RESET
              ERASEALL
              ERASEALLSTATUS
              APPROTECTSTATUS
              IDR
            Electrical specification
              Control access port
          Debug interface mode
          Real-time debug
      Power and clock management
        Power management unit (PMU)
        Current consumption
          Electrical specification
            CPU running
            Radio transmitting/receiving
            Sleep
            Compounded
            TIMER running
            RNG active
            TEMP active
            SAADC active
            COMP active
            WDT active
        POWER — Power supply
          Regulators
          System OFF mode
            Emulated System OFF mode
          System ON mode
            Sub power modes
          Power supply supervisor
            Power-fail comparator