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nRF5 Getting Started
  Product development with nRF5 Series SoCs
    Available protocols
    Nordic tools and downloads
    Software development
    Hardware design
    Hardware testing
    Product certification
    Production programming and testing
  Software development Getting Started Guides
    nRF5 Series: Developing with SEGGER Embedded Studio
      Revision history
      Minimum requirements
      Related documentation
      Development kits, boards, and chips
      SoftDevices
      Running a first test
      Setting up your toolchain
        Nordic tools and downloads
        Setting up the nRF5 SDK
        Installing SEGGER tools
        Installing the nRF5x Command Line Tools
      Programming an application
        Erasing the board
        Importing Keil projects
        Compiling the application
        Configuring placement of the SoftDevice
        Programming the firmware
        Adding files
          Adding source files
          Including header files
      Communicating with the board
        Connecting via RTT
          Connecting via RTT on Windows
          Connecting via RTT on Linux
        Connecting via CDC-UART
      Testing the application
        Testing with a mobile device
        Testing with a computer
      Debugging
      Glossary
        DK (Development Kit)
        GNU Compiler Collection (GCC)
        Integrated Development Environment (IDE)
        Real Time Transfer (RTT)
        SEGGER Embedded Studio (SES)
        SoftDevice
        System on Chip (SoC)
        Target
        Universal Asynchronous Receiver/Transmitter (UART)
      Acronyms and abbreviations
      Legal notices
    nRF5 Series: Developing on Windows with ARM Keil MDK
      Revision history
      Minimum requirements
      Related documentation
      Development kits, boards, and chips
      SoftDevices
      Running a first test
      Setting up your toolchain
        Nordic tools and downloads
        Installing the ARM Keil MDK
        Setting up the nRF5 SDK
        Installing the nRF5x Command Line Tools
        Installing nRFgo Studio
      Programming an application
        Erasing the board
        Compiling the application
        Programming the SoftDevice
        Programming the application
      Communicating with the board
        Connecting via RTT
        Connecting via CDC-UART
      Testing the application
        Testing with a mobile device
        Testing with a computer
      Debugging
      Glossary
        DK (Development Kit)
        Device Family Pack
        GNU Compiler Collection (GCC)
        Integrated Development Environment (IDE)
        Real Time Transfer (RTT)
        SEGGER Embedded Studio (SES)
        SoftDevice
        System on Chip (SoC)
        Target
        Universal Asynchronous Receiver/Transmitter (UART)
      Acronyms and abbreviations
      Legal notices
     nRF53 Series: Developing with nRF Connect SDK
      Revision history
      Minimum requirements
      Related documentation
      Running a first test
      Setting up your toolchain
        Installing nRF Connect SDK
        Installing SEGGER Embedded Studio
        Installing nRF Command Line Tools
      Programming an application
      Communicating with the board
        Connecting via CDC-UART
      Testing the application
        Testing with a mobile device
        Testing with a computer
      Debugging
      Glossary
        Integrated Development Environment (IDE)
        Preview Development Kit (PDK)
        SEGGER Embedded Studio (SES)
        System on Chip (SoC)
        Universal Asynchronous Receiver/Transmitter (UART)
      Acronyms and abbreviations
      Legal notices
  Product development with nRF5 Series SoCs
    Available protocols
    Nordic tools and downloads
    Software development
    Hardware design
    Hardware testing
    Product certification
    Production programming and testing
  Software development Getting Started Guides
    nRF5 Series: Developing with SEGGER Embedded Studio
      Revision history
      Minimum requirements
      Related documentation
      Development kits, boards, and chips
      SoftDevices
      Running a first test
      Setting up your toolchain
        Nordic tools and downloads
        Setting up the nRF5 SDK
        Installing SEGGER tools
        Installing the nRF5x Command Line Tools
      Programming an application
        Erasing the board
        Importing Keil projects
        Compiling the application
        Configuring placement of the SoftDevice
        Programming the firmware
        Adding files
          Adding source files
          Including header files
      Communicating with the board
        Connecting via RTT
          Connecting via RTT on Windows
          Connecting via RTT on Linux
        Connecting via CDC-UART
      Testing the application
        Testing with a mobile device
        Testing with a computer
      Debugging
      Glossary
        DK (Development Kit)
        GNU Compiler Collection (GCC)
        Integrated Development Environment (IDE)
        Real Time Transfer (RTT)
        SEGGER Embedded Studio (SES)
        SoftDevice
        System on Chip (SoC)
        Target
        Universal Asynchronous Receiver/Transmitter (UART)
      Acronyms and abbreviations
      Legal notices
    nRF5 Series: Developing on Windows with ARM Keil MDK
      Revision history
      Minimum requirements
      Related documentation
      Development kits, boards, and chips
      SoftDevices
      Running a first test
      Setting up your toolchain
        Nordic tools and downloads
        Installing the ARM Keil MDK
        Setting up the nRF5 SDK
        Installing the nRF5x Command Line Tools
        Installing nRFgo Studio
      Programming an application
        Erasing the board
        Compiling the application
        Programming the SoftDevice
        Programming the application
      Communicating with the board
        Connecting via RTT
        Connecting via CDC-UART
      Testing the application
        Testing with a mobile device
        Testing with a computer
      Debugging
      Glossary
        DK (Development Kit)
        Device Family Pack
        GNU Compiler Collection (GCC)
        Integrated Development Environment (IDE)
        Real Time Transfer (RTT)
        SEGGER Embedded Studio (SES)
        SoftDevice
        System on Chip (SoC)
        Target
        Universal Asynchronous Receiver/Transmitter (UART)
      Acronyms and abbreviations
      Legal notices
     nRF53 Series: Developing with nRF Connect SDK
      Revision history
      Minimum requirements
      Related documentation
      Running a first test
      Setting up your toolchain
        Installing nRF Connect SDK
        Installing SEGGER Embedded Studio
        Installing nRF Command Line Tools
      Programming an application
      Communicating with the board
        Connecting via CDC-UART
      Testing the application
        Testing with a mobile device
        Testing with a computer
      Debugging
      Glossary
        Integrated Development Environment (IDE)
        Preview Development Kit (PDK)
        SEGGER Embedded Studio (SES)
        System on Chip (SoC)
        Universal Asynchronous Receiver/Transmitter (UART)
      Acronyms and abbreviations
      Legal notices
nRF91 Series
  nRF9160
    nRF9160 Product Specification
      Revision history
      About this document
        Document status
        Peripheral chapters
        Register tables
          Fields and values
          Permissions
        Registers
          DUMMY
      Product overview
        Introduction
        Block diagram
        Peripheral interface
          Peripheral ID
          Peripherals with shared ID
          Peripheral registers
          Bit set and clear
          Tasks
          Events
          Publish / Subscribe
          Shortcuts
          Interrupts
          Secure/non-secure peripherals
      Application core
        CPU
          CPU and support module configuration
          Electrical specification
            CPU performance
        Memory
          Memory map
          Instantiation
          Peripheral access control capabilities
        VMC — Volatile memory controller
          Registers
            RAM[n].POWER
            RAM[n].POWERSET
            RAM[n].POWERCLR
        NVMC — Non-volatile memory controller
          Writing to flash
          Erasing a secure page in flash
          Erasing a non-secure page in flash
          Writing to user information configuration registers (UICR)
          Erase all
          NVMC protection mechanisms
            NVMC blocking
            NVMC power failure protection
          Cache
          Registers
            READY
            READYNEXT
            CONFIG
            ERASEALL
            ERASEPAGEPARTIALCFG
            ICACHECNF
            IHIT
            IMISS
            CONFIGNS
            WRITEUICRNS
          Electrical specification
            Flash programming
            Cache size
        FICR — Factory information configuration registers
          Registers
            INFO.DEVICEID[n]
            INFO.PART
            INFO.VARIANT
            INFO.PACKAGE
            INFO.RAM
            INFO.FLASH
            INFO.CODEPAGESIZE
            INFO.CODESIZE
            INFO.DEVICETYPE
            TRIMCNF[n].ADDR
            TRIMCNF[n].DATA
            TRNG90B.BYTES
            TRNG90B.RCCUTOFF
            TRNG90B.APCUTOFF
            TRNG90B.STARTUP
            TRNG90B.ROSC1
            TRNG90B.ROSC2
            TRNG90B.ROSC3
            TRNG90B.ROSC4
        UICR — User information configuration registers
          Registers
            APPROTECT
            XOSC32M
            HFXOSRC
            HFXOCNT
            SECUREAPPROTECT
            ERASEPROTECT
            OTP[n]
            KEYSLOT.CONFIG[n].DEST
            KEYSLOT.CONFIG[n].PERM
            KEYSLOT.KEY[n].VALUE[o]
        EasyDMA
          EasyDMA error handling
          EasyDMA array list
        AHB multilayer interconnect
      Power and clock management
        Functional description
          Power management
            System ON mode
            System OFF mode
              Emulated System OFF mode
          Power supply
            General purpose I/O supply
          Power supply monitoring
            Power supply supervisor
            Battery monitoring on VDD
            Electrical specification
              Device startup times
              Power supply supervisor
          Clock management
            HFCLK clock controller
            LFCLK clock controller
              32.768 kHz RC oscillator (LFRC)
            Electrical specification
              64 MHz internal oscillator (HFINT)
               64 MHz high accuracy oscillator (HFXO)
              32.768 kHz high accuracy oscillator (LFXO)
              32.768 kHz RC oscillator (LFRC)
          Reset
            Power-on reset
            Pin reset
            Wakeup from System OFF mode reset
            Soft reset
            Watchdog reset
            Brownout reset
            Retained registers
            Reset behavior
            Electrical specification
              Pin reset
        Current consumption
          Electrical specification
            Sleep
            Application CPU active current consumption
            I2S
            PDM
            PWM
            SAADC
            TIMER
            SPIM
            SPIS
            TWIM
            TWIS
            UARTE
            WDT
            Modem current consumption
            GPS current consumption
        Register description
          POWER — Power control
            Registers
              TASKS_CONSTLAT
              TASKS_LOWPWR
              SUBSCRIBE_CONSTLAT
              SUBSCRIBE_LOWPWR
              EVENTS_POFWARN
              EVENTS_SLEEPENTER
              EVENTS_SLEEPEXIT
              PUBLISH_POFWARN
              PUBLISH_SLEEPENTER
              PUBLISH_SLEEPEXIT
              INTEN
              INTENSET
              INTENCLR
              RESETREAS
              POWERSTATUS
              GPREGRET[n]
          CLOCK — Clock control
            Registers
              TASKS_HFCLKSTART
              TASKS_HFCLKSTOP
              TASKS_LFCLKSTART
              TASKS_LFCLKSTOP
              SUBSCRIBE_HFCLKSTART
              SUBSCRIBE_HFCLKSTOP
              SUBSCRIBE_LFCLKSTART
              SUBSCRIBE_LFCLKSTOP
              EVENTS_HFCLKSTARTED
              EVENTS_LFCLKSTARTED
              PUBLISH_HFCLKSTARTED
              PUBLISH_LFCLKSTARTED
              INTEN
              INTENSET
              INTENCLR
              INTPEND
              HFCLKRUN
              HFCLKSTAT
              LFCLKRUN
              LFCLKSTAT
              LFCLKSRCCOPY
              LFCLKSRC
          REGULATORS — Voltage regulators control
            Registers
              SYSTEMOFF
              DCDCEN
      Peripherals
        CRYPTOCELL — ARM TrustZone CryptoCell 310
          Usage
          Always-on (AO) power domain
          Lifecycle state (LCS)
          Cryptographic key selection
            RTL key
            Device root key
          Direct memory access (DMA)
          Standards
          Registers
            ENABLE
          Host interface
            HOST_RGF block
              Registers
                HOST_CRYPTOKEY_SEL
                HOST_IOT_KPRTL_LOCK
                HOST_IOT_KDR0
                HOST_IOT_KDR1
                HOST_IOT_KDR2
                HOST_IOT_KDR3
                HOST_IOT_LCS
        DPPI - Distributed programmable peripheral interconnect
          Subscribing to and publishing on channels
          DPPI configuration (DPPIC)
          Connection examples
          Special considerations for a system implementing TrustZone for Cortex-M processors
          Registers
            TASKS_CHG[n].EN
            TASKS_CHG[n].DIS
            SUBSCRIBE_CHG[n].EN
            SUBSCRIBE_CHG[n].DIS
            CHEN
            CHENSET
            CHENCLR
            CHG[n]
        EGU — Event generator unit
          Registers
            TASKS_TRIGGER[n]
            SUBSCRIBE_TRIGGER[n]
            EVENTS_TRIGGERED[n]
            PUBLISH_TRIGGERED[n]
            INTEN
            INTENSET
            INTENCLR
          Electrical specification
            EGU Electrical Specification
        GPIO — General purpose input/output
          Pin configuration
          Pin sense mechanism
          GPIO security
          Registers
            OUT ( Retained )
            OUTSET
            OUTCLR
            IN
            DIR ( Retained )
            DIRSET
            DIRCLR
            LATCH ( Retained )
            DETECTMODE ( Retained )
            DETECTMODE_SEC ( Retained )
            PIN_CNF[n]
          Electrical specification
            GPIO Electrical Specification
        GPIOTE — GPIO tasks and events
          Pin events and tasks
          Port event
          Tasks and events pin configuration
          Registers
            TASKS_OUT[n]
            TASKS_SET[n]
            TASKS_CLR[n]
            SUBSCRIBE_OUT[n]
            SUBSCRIBE_SET[n]
            SUBSCRIBE_CLR[n]
            EVENTS_IN[n]
            EVENTS_PORT
            PUBLISH_IN[n]
            PUBLISH_PORT
            INTENSET
            INTENCLR
            CONFIG[n]
          Electrical specification
        IPC — Interprocessor communication
          IPC and PPI connections
          Registers
            TASKS_SEND[n]
            SUBSCRIBE_SEND[n]
            EVENTS_RECEIVE[n]
            PUBLISH_RECEIVE[n]
            INTEN
            INTENSET
            INTENCLR
            INTPEND
            SEND_CNF[n]
            RECEIVE_CNF[n]
            GPMEM[n]
          Electrical specification
            IPC Electrical Specification
        I2S — Inter-IC sound interface
          Mode
          Transmitting and receiving
          Left right clock (LRCK)
          Serial clock (SCK)
          Master clock (MCK)
          Width, alignment and format
          EasyDMA
          Module operation
          Pin configuration
          Registers
            TASKS_START
            TASKS_STOP
            SUBSCRIBE_START
            SUBSCRIBE_STOP
            EVENTS_RXPTRUPD
            EVENTS_STOPPED
            EVENTS_TXPTRUPD
            PUBLISH_RXPTRUPD
            PUBLISH_STOPPED
            PUBLISH_TXPTRUPD
            INTEN
            INTENSET
            INTENCLR
            ENABLE
            CONFIG.MODE
            CONFIG.RXEN
            CONFIG.TXEN
            CONFIG.MCKEN
            CONFIG.MCKFREQ
            CONFIG.RATIO
            CONFIG.SWIDTH
            CONFIG.ALIGN
            CONFIG.FORMAT
            CONFIG.CHANNELS
            RXD.PTR
            TXD.PTR
            RXTXD.MAXCNT
            PSEL.MCK
            PSEL.SCK
            PSEL.LRCK
            PSEL.SDIN
            PSEL.SDOUT
          Electrical specification
            I2S timing specification
        KMU — Key management unit
          Functional view
          Access control
          Protecting the UICR content
          Usage
            OTP
            Key storage
              Selecting a key slot
              Writing to a key slot
              Reading a key value
              Push over secure APB
              Revoking the key slots
            STATUS register
          Registers
            TASKS_PUSH_KEYSLOT
            EVENTS_KEYSLOT_PUSHED
            EVENTS_KEYSLOT_REVOKED
            EVENTS_KEYSLOT_ERROR
            INTEN
            INTENSET
            INTENCLR
            INTPEND
            STATUS
            SELECTKEYSLOT
        PDM — Pulse density modulation interface
          Master clock generator
          Module operation
          Decimation filter
          EasyDMA
          Hardware example
          Pin configuration
          Registers
            TASKS_START
            TASKS_STOP
            SUBSCRIBE_START
            SUBSCRIBE_STOP
            EVENTS_STARTED
            EVENTS_STOPPED
            EVENTS_END
            PUBLISH_STARTED
            PUBLISH_STOPPED
            PUBLISH_END
            INTEN
            INTENSET
            INTENCLR
            ENABLE
            PDMCLKCTRL
            MODE
            GAINL
            GAINR
            RATIO
            PSEL.CLK
            PSEL.DIN
            SAMPLE.PTR
            SAMPLE.MAXCNT
          Electrical specification
            PDM Electrical Specification
        PWM — Pulse width modulation
          Wave counter
          Decoder with EasyDMA
          Limitations
          Pin configuration
          Registers
            TASKS_STOP
            TASKS_SEQSTART[n]
            TASKS_NEXTSTEP
            SUBSCRIBE_STOP
            SUBSCRIBE_SEQSTART[n]
            SUBSCRIBE_NEXTSTEP
            EVENTS_STOPPED
            EVENTS_SEQSTARTED[n]
            EVENTS_SEQEND[n]
            EVENTS_PWMPERIODEND
            EVENTS_LOOPSDONE
            PUBLISH_STOPPED
            PUBLISH_SEQSTARTED[n]
            PUBLISH_SEQEND[n]
            PUBLISH_PWMPERIODEND
            PUBLISH_LOOPSDONE
            SHORTS
            INTEN
            INTENSET
            INTENCLR
            ENABLE
            MODE
            COUNTERTOP
            PRESCALER
            DECODER
            LOOP
            SEQ[n].PTR
            SEQ[n].CNT
            SEQ[n].REFRESH
            SEQ[n].ENDDELAY
            PSEL.OUT[n]
        RTC — Real-time counter
          Clock source
          Resolution versus overflow and the prescaler
          Counter register
          Overflow
          Tick event
          Event control
          Compare
          Task and event jitter/delay
          Reading the counter register
          Registers
            TASKS_START
            TASKS_STOP
            TASKS_CLEAR
            TASKS_TRIGOVRFLW
            SUBSCRIBE_START
            SUBSCRIBE_STOP
            SUBSCRIBE_CLEAR
            SUBSCRIBE_TRIGOVRFLW
            EVENTS_TICK
            EVENTS_OVRFLW
            EVENTS_COMPARE[n]
            PUBLISH_TICK
            PUBLISH_OVRFLW
            PUBLISH_COMPARE[n]
            INTENSET
            INTENCLR
            EVTEN
            EVTENSET
            EVTENCLR
            COUNTER
            PRESCALER
            CC[n]
          Electrical specification
        SAADC — Successive approximation analog-to-digital converter
          Overview
          Digital output
          Analog inputs and channels
          Operation modes
            One-shot mode
            Continuous mode
            Oversampling
            Scan mode
          EasyDMA
          Resistor ladder
          Reference
          Acquisition time
          Limits event monitoring
          Registers
            TASKS_START
            TASKS_SAMPLE
            TASKS_STOP
            TASKS_CALIBRATEOFFSET
            SUBSCRIBE_START
            SUBSCRIBE_SAMPLE
            SUBSCRIBE_STOP
            SUBSCRIBE_CALIBRATEOFFSET
            EVENTS_STARTED
            EVENTS_END
            EVENTS_DONE
            EVENTS_RESULTDONE
            EVENTS_CALIBRATEDONE
            EVENTS_STOPPED
            EVENTS_CH[n].LIMITH
            EVENTS_CH[n].LIMITL
            PUBLISH_STARTED
            PUBLISH_END
            PUBLISH_DONE
            PUBLISH_RESULTDONE
            PUBLISH_CALIBRATEDONE
            PUBLISH_STOPPED
            PUBLISH_CH[n].LIMITH
            PUBLISH_CH[n].LIMITL
            INTEN
            INTENSET
            INTENCLR
            STATUS
            ENABLE
            CH[n].PSELP
            CH[n].PSELN
            CH[n].CONFIG
            CH[n].LIMIT
            RESOLUTION
            OVERSAMPLE
            SAMPLERATE
            RESULT.PTR
            RESULT.MAXCNT
            RESULT.AMOUNT
          Electrical specification
            SAADC Electrical Specification
          Performance factors
        SPIM — Serial peripheral interface master with EasyDMA
          SPI master transaction sequence
          Master mode pin configuration
          Shared resources
          EasyDMA
          Low power
          Registers
            TASKS_START
            TASKS_STOP
            TASKS_SUSPEND
            TASKS_RESUME
            SUBSCRIBE_START
            SUBSCRIBE_STOP
            SUBSCRIBE_SUSPEND
            SUBSCRIBE_RESUME
            EVENTS_STOPPED
            EVENTS_ENDRX
            EVENTS_END
            EVENTS_ENDTX
            EVENTS_STARTED
            PUBLISH_STOPPED
            PUBLISH_ENDRX
            PUBLISH_END
            PUBLISH_ENDTX
            PUBLISH_STARTED
            SHORTS
            INTENSET
            INTENCLR
            ENABLE
            PSEL.SCK
            PSEL.MOSI
            PSEL.MISO
            FREQUENCY
            RXD.PTR
            RXD.MAXCNT
            RXD.AMOUNT
            RXD.LIST
            TXD.PTR
            TXD.MAXCNT
            TXD.AMOUNT
            TXD.LIST
            CONFIG
            ORC
          Electrical specification
            SPIM master interface electrical specifications
            Serial Peripheral Interface Master (SPIM) timing specifications
        SPIS — Serial peripheral interface slave with EasyDMA
          Shared resources
          EasyDMA
          SPI slave operation
          Semaphore operation
          Pin configuration
          Registers
            TASKS_ACQUIRE
            TASKS_RELEASE
            SUBSCRIBE_ACQUIRE
            SUBSCRIBE_RELEASE
            EVENTS_END
            EVENTS_ENDRX
            EVENTS_ACQUIRED
            PUBLISH_END
            PUBLISH_ENDRX
            PUBLISH_ACQUIRED
            SHORTS
            INTENSET
            INTENCLR
            SEMSTAT
            STATUS
            ENABLE
            PSEL.SCK
            PSEL.MISO
            PSEL.MOSI
            PSEL.CSN
            PSELSCK ( Deprecated )
            PSELMISO ( Deprecated )
            PSELMOSI ( Deprecated )
            PSELCSN ( Deprecated )
            RXDPTR ( Deprecated )
            MAXRX ( Deprecated )
            AMOUNTRX ( Deprecated )
            RXD.PTR
            RXD.MAXCNT
            RXD.AMOUNT
            RXD.LIST
            TXDPTR ( Deprecated )
            MAXTX ( Deprecated )
            AMOUNTTX ( Deprecated )
            TXD.PTR
            TXD.MAXCNT
            TXD.AMOUNT
            TXD.LIST
            CONFIG
            DEF
            ORC
          Electrical specification
            SPIS slave interface electrical specifications
            Serial Peripheral Interface Slave (SPIS) timing specifications
        SPU - System protection unit
          General concepts
            Special considerations for ARM TrustZone for Cortex-M enabled system
          Flash access control
            Non-secure callable (NSC) region definition in flash
            Flash access error reporting
            UICR and FICR protections
          RAM access control
            Non-secure callable (NSC) region definition in RAM
            RAM access error reporting
          Peripheral access control
            Peripherals with split security
            Peripheral address mapping
            Special considerations for peripherals with DMA master
            Peripheral access error reporting
          Pin access control
            Direct pin control through the GPIO peripheral
          DPPI access control
            Special considerations regarding the DPPIC configuration registers
          External domain access control
          TrustZone for Cortex-M ID allocation
          Registers
            EVENTS_RAMACCERR
            EVENTS_FLASHACCERR
            EVENTS_PERIPHACCERR
            PUBLISH_RAMACCERR
            PUBLISH_FLASHACCERR
            PUBLISH_PERIPHACCERR
            INTEN
            INTENSET
            INTENCLR
            CAP
            EXTDOMAIN[n].PERM
            DPPI[n].PERM
            DPPI[n].LOCK
            GPIOPORT[n].PERM
            GPIOPORT[n].LOCK
            FLASHNSC[n].REGION
            FLASHNSC[n].SIZE
            RAMNSC[n].REGION
            RAMNSC[n].SIZE
            FLASHREGION[n].PERM
            RAMREGION[n].PERM
            PERIPHID[n].PERM
        TIMER — Timer/counter
          Capture
          Compare
          Task delays
          Task priority
          Registers
            TASKS_START
            TASKS_STOP
            TASKS_COUNT
            TASKS_CLEAR
            TASKS_SHUTDOWN ( Deprecated )
            TASKS_CAPTURE[n]
            SUBSCRIBE_START
            SUBSCRIBE_STOP
            SUBSCRIBE_COUNT
            SUBSCRIBE_CLEAR
            SUBSCRIBE_SHUTDOWN ( Deprecated )
            SUBSCRIBE_CAPTURE[n]
            EVENTS_COMPARE[n]
            PUBLISH_COMPARE[n]
            SHORTS
            INTENSET
            INTENCLR
            MODE
            BITMODE
            PRESCALER
            ONESHOTEN[n]
            CC[n]
          Electrical specification
        TWIM — I2C compatible two-wire interface master with EasyDMA
          Shared resources
          EasyDMA
          Master write sequence
          Master read sequence
          Master repeated start sequence
          Low power
          Master mode pin configuration
          Registers
            TASKS_STARTRX
            TASKS_STARTTX
            TASKS_STOP
            TASKS_SUSPEND
            TASKS_RESUME
            SUBSCRIBE_STARTRX
            SUBSCRIBE_STARTTX
            SUBSCRIBE_STOP
            SUBSCRIBE_SUSPEND
            SUBSCRIBE_RESUME
            EVENTS_STOPPED
            EVENTS_ERROR
            EVENTS_SUSPENDED
            EVENTS_RXSTARTED
            EVENTS_TXSTARTED
            EVENTS_LASTRX
            EVENTS_LASTTX
            PUBLISH_STOPPED
            PUBLISH_ERROR
            PUBLISH_SUSPENDED
            PUBLISH_RXSTARTED
            PUBLISH_TXSTARTED
            PUBLISH_LASTRX
            PUBLISH_LASTTX
            SHORTS
            INTEN
            INTENSET
            INTENCLR
            ERRORSRC
            ENABLE
            PSEL.SCL
            PSEL.SDA
            FREQUENCY
            RXD.PTR
            RXD.MAXCNT
            RXD.AMOUNT
            RXD.LIST
            TXD.PTR
            TXD.MAXCNT
            TXD.AMOUNT
            TXD.LIST
            ADDRESS
          Electrical specification
            TWIM interface electrical specifications
            Two Wire Interface Master (TWIM) timing specifications
          Pullup resistor
        TWIS — I2C compatible two-wire interface slave with EasyDMA
          Shared resources
          EasyDMA
          TWI slave responding to a read command
          TWI slave responding to a write command
          Master repeated start sequence
          Terminating an ongoing TWI transaction
          Low power
          Slave mode pin configuration
          Registers
            TASKS_STOP
            TASKS_SUSPEND
            TASKS_RESUME
            TASKS_PREPARERX
            TASKS_PREPARETX
            SUBSCRIBE_STOP
            SUBSCRIBE_SUSPEND
            SUBSCRIBE_RESUME
            SUBSCRIBE_PREPARERX
            SUBSCRIBE_PREPARETX
            EVENTS_STOPPED
            EVENTS_ERROR
            EVENTS_RXSTARTED
            EVENTS_TXSTARTED
            EVENTS_WRITE
            EVENTS_READ
            PUBLISH_STOPPED
            PUBLISH_ERROR
            PUBLISH_RXSTARTED
            PUBLISH_TXSTARTED
            PUBLISH_WRITE
            PUBLISH_READ
            SHORTS
            INTEN
            INTENSET
            INTENCLR
            ERRORSRC
            MATCH
            ENABLE
            PSEL.SCL
            PSEL.SDA
            RXD.PTR
            RXD.MAXCNT
            RXD.AMOUNT
            RXD.LIST
            TXD.PTR
            TXD.MAXCNT
            TXD.AMOUNT
            TXD.LIST
            ADDRESS[n]
            CONFIG
            ORC
          Electrical specification
            TWIS slave timing specifications
        UARTE — Universal asynchronous receiver/transmitter with EasyDMA
          EasyDMA
          Transmission
          Reception
          Error conditions
          Using the UARTE without flow control
          Parity and stop bit configuration
          Low power
          Pin configuration
          Registers
            TASKS_STARTRX
            TASKS_STOPRX
            TASKS_STARTTX
            TASKS_STOPTX
            TASKS_FLUSHRX
            SUBSCRIBE_STARTRX
            SUBSCRIBE_STOPRX
            SUBSCRIBE_STARTTX
            SUBSCRIBE_STOPTX
            SUBSCRIBE_FLUSHRX
            EVENTS_CTS
            EVENTS_NCTS
            EVENTS_RXDRDY
            EVENTS_ENDRX
            EVENTS_TXDRDY
            EVENTS_ENDTX
            EVENTS_ERROR
            EVENTS_RXTO
            EVENTS_RXSTARTED
            EVENTS_TXSTARTED
            EVENTS_TXSTOPPED
            PUBLISH_CTS
            PUBLISH_NCTS
            PUBLISH_RXDRDY
            PUBLISH_ENDRX
            PUBLISH_TXDRDY
            PUBLISH_ENDTX
            PUBLISH_ERROR
            PUBLISH_RXTO
            PUBLISH_RXSTARTED
            PUBLISH_TXSTARTED
            PUBLISH_TXSTOPPED
            SHORTS
            INTEN
            INTENSET
            INTENCLR
            ERRORSRC
            ENABLE
            PSEL.RTS
            PSEL.TXD
            PSEL.CTS
            PSEL.RXD
            BAUDRATE
            RXD.PTR
            RXD.MAXCNT
            RXD.AMOUNT
            TXD.PTR
            TXD.MAXCNT
            TXD.AMOUNT
            CONFIG
          Electrical specification
            UARTE electrical specification
        WDT — Watchdog timer
          Reload criteria
          Temporarily pausing the watchdog
          Watchdog reset
          Registers
            TASKS_START
            SUBSCRIBE_START
            EVENTS_TIMEOUT
            PUBLISH_TIMEOUT
            INTENSET
            INTENCLR
            RUNSTATUS
            REQSTATUS
            CRV
            RREN
            CONFIG
            RR[n]
          Electrical specification
            Watchdog Timer Electrical Specification
      LTE modem
        Introduction
        SIM card interface
        LTE modem coexistence interface
        LTE modem RF control external interface
        RF front-end interface
        Electrical specification
          Key RF parameters for Cat-M1
          Key RF parameters for Cat-NB1 and Cat-NB2
          Receiver parameters for Cat-M1
          Receiver parameters for Cat-NB1 and Cat-NB2
          Transmitter parameters for Cat-M1
          Transmitter parameters for Cat-NB1 and Cat-NB2
      GPS receiver
        Electrical specification
      Debug and trace
        Overview
          Special consideration regarding debugger access
          DAP - Debug access port
          Debug interface mode
          Real-time debug
          Trace
          Registers
            TARGETID
          Electrical specification
            Trace port
        CTRL-AP - Control access port
          Reset request
          Erase all
          Mailbox interface
          Disabling erase protection
          Registers
            RESET
            ERASEALL
            ERASEALLSTATUS
            APPROTECT.STATUS
            ERASEPROTECT.STATUS
            ERASEPROTECT.DISABLE
            MAILBOX.TXDATA
            MAILBOX.TXSTATUS
            MAILBOX.RXDATA
            MAILBOX.RXSTATUS
            IDR
          Registers
            MAILBOX.RXDATA
            MAILBOX.RXSTATUS
            MAILBOX.TXDATA
            MAILBOX.TXSTATUS
            ERASEPROTECT.LOCK
            ERASEPROTECT.DISABLE
        TAD - Trace and debug control
          Registers
            CLOCKSTART
            CLOCKSTOP
            ENABLE
            PSEL.TRACECLK
            PSEL.TRACEDATA0
            PSEL.TRACEDATA1
            PSEL.TRACEDATA2
            PSEL.TRACEDATA3
            TRACEPORTSPEED ( Retained )
      Hardware and layout
        Pin assignments
          Pin assignments
        Mechanical specifications
          16.00 x 10.50 mm package
        Reference circuitry
          Schematic SIxA LGA127
      Operating conditions
        VDD_GPIO considerations
      Absolute maximum ratings
      Ordering information
        IC marking
        Box labels
        Order code
        Code ranges and values
        Product options
      Regulatory information
      Legal notices
    Errata
      nRF9160 Revision 1 Errata
        Change log
        New and inherited anomalies
          [1] I2S: Excessive power consumption after using STOP task
          [2] NVMC: CPU code execution from RAM halted during flash page erase operation
          [4] GPIO: Bits in GPIO LATCH register are incorrectly set to 1
          [6] POWER: SLEEPENTER and SLEEPEXIT events asserted after pin reset
          [7] KMU: Subsequent accesses between info_mem and main_mem of the flash may not work properly
          [9] SAADC: Reduced SFDR
          [15] REGULATORS: Supply regulators default to LDO mode after reset
          [21] NVMC: Disabling instruction cache causes skip of next instruction
          [23] UART: TASKS_RESUME impacts UARTE
          [24] NVMC: CPU is not halted for page erase in debug session
          [26] CLOCK, LFXO: System locks up when set in System ON IDLE while waiting for EVENTS_LFCLKSTARTED
          [27] CryptoCell: Arm CryptoCell true random number generator (TRNG) has wrong configuration
          [28] SAADC: Events are not generated when switching from scan mode to no-scan mode
          [29] Debug and Trace: System reset does not work
          [30] PWM: False SEQEND[0] and SEQEND[1] events are generated
          [31] LFXO: LFXO startup fails
        Fixed anomalies
      nRF9160 Engineering A Errata
        Change log
        New and inherited anomalies
          [1] I2S: Excessive power consumption after using STOP task
          [2] NVMC: CPU code execution from RAM halted during flash page erase operation
          [4] GPIO: Bits in GPIO LATCH register are incorrectly set to 1
          [6] POWER: SLEEPENTER and SLEEPEXIT events asserted after pin reset
          [7] KMU: Subsequent accesses between info_mem and main_mem of the flash may not work properly
          [8] SAADC: Reduced SFDR
          [10] LTE Modem: MAGPIO and MIPI RFFE - high initial voltage
          [12] Debug and Trace: SWD debugger scan
          [14] REGULATORS: Supply regulators default to LDO mode after reset
          [16] SAADC: SAADC result
          [17] Debug and Trace: LTE modem stops when debugging through SWD interface
          [20] RAM: RAM content cannot be trusted upon waking up from System ON IDLE or System OFF mode
          [21] NVMC: Disabling instruction cache causes skip of next instruction
          [23] UART: TASKS_RESUME impacts UARTE
          [24] NVMC: CPU is not halted for page erase in debug session
          [26] CLOCK, LFXO: System locks up when set in System ON IDLE while waiting for EVENTS_LFCLKSTARTED
          [28] SAADC: Events are not generated when switching from scan mode to no-scan mode
          [29] Debug and Trace: System reset does not work
          [30] PWM: False SEQEND[0] and SEQEND[1] events are generated
          [31] LFXO: LFXO startup fails
    PCN and IN
      IN114 Informational Notice v1.0
    Compatibility Matrix
      IC revisions and variants
      Documentation and reference design files
      nRF Connect SDK
      Development HW
      Revision history
    nRF9160 DK
      Revision history
      Kit content
        Hardware content
        Related documentation
      Operating modes
        Firmware development mode
          Device programming
          Virtual COM port
          MSD
          Reset
        Performance measurement mode
          USB detect
      Hardware description
        Block diagram
        Hardware figures
        Power supply
          nRF9160 supply
          VDD supply rail
          Other power domains
        Antenna interfaces
        GPS
        GPIO interfaces
        nRF52840
          nRF9160 DK board control
          Bluetooth/IEEE 802.15.4 network processor
        Buttons, slide switches, and LEDs
        Debug input and trace options
          Debug output
        Signal routing switches
          Interface MCU disconnect switches
          Switches for UART interface
          Switches for buttons and LEDs
          Switches for nRF52840 interface
        SIM and eSIM
        Additional nRF9160 interfaces
        SiP enable
        Solder bridge configuration
      Measuring current
        Preparing the development kit for current measurements
        Using an oscilloscope for current profile measurement
        Using a current meter for current measurement
      RF measurements
      Radiated performance of nRF9160 DK
      Glossary
        Band-Pass Filter (BPF)
        Cat-M1
        Cat-NB1
        Clear to Send (CTS)
        DK (Development Kit)
        Fast Identity Online (FIDO)
        Global Positioning System (GPS)
        Hardware Flow Control (HWFC)
        Inter-integrated Circuit (I2C)
        Low-Dropout Regulator (LDO)
        Low-Noise Amplifier (LNA)
        nRF Cloud
        Operational Amplifier (op-amp)
        Receive Data (RXD)
        Request to Send (RTS)
        SAW filter
        Surface Acoustic Wave (SAW)
        System in Package (SiP)
        System on Chip (SoC)
        Transmit Data (TXD)
      Acronyms and abbreviations
      Legal notices
    nRF9160 DK Errata v0.7
  nRF91 AT Commands
    Revision history
    AT command syntax
      Set command <CMD>[=...]
      Read command <CMD>?
      Test command <CMD>=?
      Response
    General
      Request manufacturer identification +CGMI
        Set command
        Read command
        Test command
      Request model identification +CGMM
        Set command
        Read command
        Test command
      Request revision identification +CGMR
        Set command
        Read command
        Test command
      Request product serial number identification +CGSN
        Set command
        Read command
        Test command
      Request IMSI +CIMI
        Set command
        Read command
        Test command
    Mobile termination control and status commands
      Functional mode +CFUN
        Set command
        Read command
        Test command
      PIN code +CPIN
        Set command
        Read command
        Test command
      Remaining PIN retries +CPINR
        Set command
        Read command
        Test command
      List all available AT commands +CLAC
        Set command
        Read command
        Test command
      Extended signal quality +CESQ
        Set command
        Read command
        Test command
      Signal quality notification %CESQ
        Set command
        Read command
        Test command
      SNR signal quality notification %XSNRSQ
        Set command
        Read command
        Test command
      Restricted SIM access +CRSM
        Set command
        Read command
        Test command
      Generic SIM access +CSIM
        Set command
        Read command
        Test command
      Device activity status +CPAS
        Set command
        Read command
        Test command
      Indicator control +CIND
        Set command
        Read command
        Test command
      IP address format +CGPIAF
        Set command
        Read command
        Test command
      Current band %XCBAND
        Set command
        Read command
        Test command
      Read neighbor cells %NBRGRSRP
        Set command
        Read command
        Test command
      Mode of operation (CS/PS) +CEMODE
        Set command
        Read command
        Test command
      UICC state %XSIM
        Set command
        Read command
        Test command
      Authenticated access %XSUDO
        Set command
        Read command
        Test command
      Public key storage management %XPMNG
        Set command
        Read command
        Test command
      RF test execution %XRFTEST
        Set command
          RX testing
          TX testing
          GPS SNR testing
          RX SNR testing
        Read command
        Test command
      Band lock %XBANDLOCK
        Set command
        Read command
        Test command
      Data profile %XDATAPRFL
        Set command
        Read command
        Test command
      Connectivity statistics %XCONNSTAT
        Set command
        Read command
        Test command
      Battery voltage %XVBAT
        Set command
        Read command
        Test command
      Customer production done %XPRODDONE
        Set command
        Read command
        Test command
      Credential storage management %CMNG
        Set command
        Read command
        Test command
      Internal temperature %XTEMP
        Set command
        Read command
        Test command
      High level for internal temperature %XTEMPHIGHLVL
        Set command
        Read command
        Test command
      Clock +CCLK
        Set command
        Read command
        Test command
      Modem trace activation %XMODEMTRACE
        Set command
        Read command
        Test command
      System mode %XSYSTEMMODE
        Set command
        Read command
        Test command
      PTW setting %XPTW
        Set command
        Read command
        Test command
    SiP pin configuration
      COEX0 pin control configuration %XCOEX0
        Set command
        Read command
        Test command
      MAGPIO configuration %XMAGPIO
        Set command
        Read command
        Test command
      SiP-external MIPIRFFE device introduction %XMIPIRFFEDEV
        Set command
        Read command
        Delete configuration
      SiP-external MIPIRFFE device control configuration %XMIPIRFFECTRL
        Set command
        Use cases INIT(0), OFF(2), and PWROFF(3)
        Use case ON(1)
        Delete configuration
    Packet domain commands
      Define PDP Context +CGDCONT
        Set command
        Read command
        Test command
      Packet domain event reporting +CGEREP
        Set command
        Read command
        Test command
      Packet domain event unsolicited result codes +CGEV
      PDP context activate +CGACT
        Set command
        Read command
        Test command
      Allocate new CID %XNEWCID
        Set command
        Read command
        Test command
      Map CID to PDN ID %XGETPDNID
        Set command
        Read command
        Test command
      QoS dynamic params +CGEQOSRDP
        Set command
        Read command
        Test command
      Show PDP address(es) +CGPADDR
        Set command
        Read command
        Test command
      PDN connection dynamic parameters +CGCONTRDP
        Set command
        Read command
        Test command
      PS attach or detach +CGATT
        Set command
        Read command
        Test command
      Power preference indication for EPS +CEPPI
        Set command
        Read command
        Test command
      Protocol configuration options notification %XPCO
        Set command
        Read command
        Test command
      Usage of ePCO/PCO in PDN connection establishment %XEPCO
        Set command
        Read command
        Test command
      APN class access %XAPNCLASS
        Set command
        Read command
        Test command
      External IP stack IPv6 address resolution/refresh failure %XIPV6FAIL
        Set command
        Read command
        Test command
      Define PDN connection authentication parameters +CGAUTH
        Set command
        Read command
        Test command
    Network service related commands
      PLMN selection +COPS
        Set command
        Read command
        Test command
      Power saving mode setting +CPSMS
        Set command
        Read command
        Test command
      eDRX setting +CEDRXS
        Set command
        Read command
        Test command
      Read EDRX dynamic parameters +CEDRXRDP
        Set command
        Read command
        Test command
      Subscriber number +CNUM
        Set command
        Read command
        Test command
      Read operator name +COPN
        Set command
        Read command
        Test command
      Facility lock +CLCK
        Set command
        Read command
        Test command
      Change password +CPWD
        Set command
        Read command
        Test command
      Network registration status +CEREG
        Set command
        Read command
        Test command
      Subscribe unsolicited operator name indications %XOPNAME
        Set command
        Read command
        Test command
      Subscribe unsolicited network time notifications %XTIME
        Set command
        Read command
        Test command
      Set release assistance information %XRAI
        Set command
        Read command
        Test command
      Operator ID %XOPERID
        Set command
        Read command
        Test command
      Read modem parameters %XMONITOR
        Set command
        Read command
        Test command
    Mobile termination errors
      Report mobile termination errors +CMEE
        Set command
        Read command
        Test command
      Report network error codes +CNEC
        Set command
        Read command
        Test command
      Extended error report +CEER
        Set command
        Read command
        Test command
    SMS commands
      Message format +CMGF
        Set command
        Read command
        Test command
      New message indications +CNMI
        Set command
        Read command
        Test command
      Send message, PDU mode + CMGS
        Set command
        Read command
        Test command
      Received SMS notification in PDU mode +CMT
      Delivery status notification in PDU mode +CDS
      New message ACK, PDU mode +CNMA
        Set command
        Read command
        Test command
      New message ACK, text mode +CNMA
        Set command
        Read command
        Test command
      Preferred message storage +CPMS
        Set command
        Read command
        Test command
      Message service failure result code +CMS ERROR
      Select SMS service +CGSMS
        Set command
        Read command
        Test command
      Short message memory available %XSMMA
        Set command
        Read command
        Test command
    Authenticating AT command usage
    Glossary
      16-state Quadrature Amplitude Modulation (16-QAM)
      Access Point Name (APN)
      Binary Phase-Shift Keying (BPSK)
      Carrier Wave (CW)
      Cat-M1
      Cat-NB1
      Check Digit (CD)
      Classless Inter-domain Routing (CIDR)
      CS/PS Mode of Operation
      Discontinuous Reception (DRX)
      Dynamic Host Configuration Protocol (DHCP)
      Electronic Serial Number (ESN)
      EPS Mobility Management (EMM)
      E-UTRA Absolute Radio Frequency Channel Number (EARFCN)
      Evolved Packet System (EPS)
      Extended Discontinuous Reception (eDRX)
      Global Navigation Satellite System (GNSS)
      International Mobile (Station) Equipment Identity (IMEI)
      International Mobile (Station) Equipment Identity, Software Version (IMEISV)
      International Mobile Subscriber Identity (IMSI)
      International Reference Alphabet (IRA)
      Low-Noise Amplifier (LNA)
      Maximum Transmission Unit (MTU)
      MIPI RF Front-End Control Interface (RFFE)
      Mobile Country Code (MCC)
      Mobile Equipment (ME)
      Mobile Network Code (MNC)
      Mobile Station International Subscriber Directory Number (MSISDN)
      Mobile Termination (MT)
      Non-access Stratum (NAS)
      Non-access Stratum (NAS) Signalling Low Priority Indication (NSLPI)
      Non-volatile Memory (NVM)
      Packet Data Network (PDN)
      Packet Data Protocol (PDP)
      Packet Data Protocol (PDP) Context
      Paging Time Window (PTW)
      Personal Identification Number (PIN)
      Personal Unblocking Key (PUK)
      Power Saving Mode (PSM)
      Pre-shared Key (PSK)
      Privacy Enhanced Mail (PEM)
      Protocol Configuration Options (PCO)
      Protocol Data Unit (PDU)
      PS Mode of Operation
      Public Land Mobile Network (PLMN)
      Quadrature Phase-Shift Keying (QPSK)
      Quality of Service (QoS)
      Reference Signal Received Power (RSRP)
      Resource Block (RB)
      RP-SMMA
      Serial Number (SNR)
      Signal-to-Noise Ratio (SNR)
      Software Version Number (SVN)
      Subscriber Identity Module (SIM)
      System in Package (SiP)
      Terminal Adapter (TA)
      Terminal Equipment (TE)
      Tracking Area Code (TAC)
      Tracking Area Update (TAU)
      Type Allocation Code (TAC)
      Universal Integrated Circuit Card (UICC)
      Unique Slave Identifier (USID)
      Universal Subscriber Identity Module (USIM)
      User Equipment (UE)
    Acronyms and abbreviations
    Legal notices
  Environmental Qualification Reports
    HSR nRF9160-SIxx (Qorvo) 2019-03
  nRF9160
    nRF9160 Product Specification
      Revision history
      About this document
        Document status
        Peripheral chapters
        Register tables
          Fields and values
          Permissions
        Registers
          DUMMY
      Product overview
        Introduction
        Block diagram
        Peripheral interface
          Peripheral ID
          Peripherals with shared ID
          Peripheral registers
          Bit set and clear
          Tasks
          Events
          Publish / Subscribe
          Shortcuts
          Interrupts
          Secure/non-secure peripherals
      Application core
        CPU
          CPU and support module configuration
          Electrical specification
            CPU performance
        Memory
          Memory map
          Instantiation
          Peripheral access control capabilities
        VMC — Volatile memory controller
          Registers
            RAM[n].POWER
            RAM[n].POWERSET
            RAM[n].POWERCLR
        NVMC — Non-volatile memory controller
          Writing to flash
          Erasing a secure page in flash
          Erasing a non-secure page in flash
          Writing to user information configuration registers (UICR)
          Erase all
          NVMC protection mechanisms
            NVMC blocking
            NVMC power failure protection
          Cache
          Registers
            READY
            READYNEXT
            CONFIG
            ERASEALL
            ERASEPAGEPARTIALCFG
            ICACHECNF
            IHIT
            IMISS
            CONFIGNS
            WRITEUICRNS
          Electrical specification
            Flash programming
            Cache size
        FICR — Factory information configuration registers
          Registers
            INFO.DEVICEID[n]
            INFO.PART
            INFO.VARIANT
            INFO.PACKAGE
            INFO.RAM
            INFO.FLASH
            INFO.CODEPAGESIZE
            INFO.CODESIZE
            INFO.DEVICETYPE
            TRIMCNF[n].ADDR
            TRIMCNF[n].DATA
            TRNG90B.BYTES
            TRNG90B.RCCUTOFF
            TRNG90B.APCUTOFF
            TRNG90B.STARTUP
            TRNG90B.ROSC1
            TRNG90B.ROSC2
            TRNG90B.ROSC3
            TRNG90B.ROSC4
        UICR — User information configuration registers
          Registers
            APPROTECT
            XOSC32M
            HFXOSRC
            HFXOCNT
            SECUREAPPROTECT
            ERASEPROTECT
            OTP[n]
            KEYSLOT.CONFIG[n].DEST
            KEYSLOT.CONFIG[n].PERM
            KEYSLOT.KEY[n].VALUE[o]
        EasyDMA
          EasyDMA error handling
          EasyDMA array list
        AHB multilayer interconnect
      Power and clock management
        Functional description
          Power management
            System ON mode
            System OFF mode
              Emulated System OFF mode
          Power supply
            General purpose I/O supply
          Power supply monitoring
            Power supply supervisor
            Battery monitoring on VDD
            Electrical specification
              Device startup times
              Power supply supervisor
          Clock management
            HFCLK clock controller
            LFCLK clock controller
              32.768 kHz RC oscillator (LFRC)
            Electrical specification
              64 MHz internal oscillator (HFINT)
               64 MHz high accuracy oscillator (HFXO)
              32.768 kHz high accuracy oscillator (LFXO)
              32.768 kHz RC oscillator (LFRC)
          Reset
            Power-on reset
            Pin reset
            Wakeup from System OFF mode reset
            Soft reset
            Watchdog reset
            Brownout reset
            Retained registers
            Reset behavior
            Electrical specification
              Pin reset
        Current consumption
          Electrical specification
            Sleep
            Application CPU active current consumption
            I2S
            PDM
            PWM
            SAADC
            TIMER
            SPIM
            SPIS
            TWIM
            TWIS
            UARTE
            WDT
            Modem current consumption
            GPS current consumption
        Register description
          POWER — Power control
            Registers
              TASKS_CONSTLAT
              TASKS_LOWPWR
              SUBSCRIBE_CONSTLAT
              SUBSCRIBE_LOWPWR
              EVENTS_POFWARN
              EVENTS_SLEEPENTER
              EVENTS_SLEEPEXIT
              PUBLISH_POFWARN
              PUBLISH_SLEEPENTER
              PUBLISH_SLEEPEXIT
              INTEN
              INTENSET
              INTENCLR
              RESETREAS
              POWERSTATUS
              GPREGRET[n]
          CLOCK — Clock control
            Registers
              TASKS_HFCLKSTART
              TASKS_HFCLKSTOP
              TASKS_LFCLKSTART
              TASKS_LFCLKSTOP
              SUBSCRIBE_HFCLKSTART
              SUBSCRIBE_HFCLKSTOP
              SUBSCRIBE_LFCLKSTART
              SUBSCRIBE_LFCLKSTOP
              EVENTS_HFCLKSTARTED
              EVENTS_LFCLKSTARTED
              PUBLISH_HFCLKSTARTED
              PUBLISH_LFCLKSTARTED
              INTEN
              INTENSET
              INTENCLR
              INTPEND
              HFCLKRUN
              HFCLKSTAT
              LFCLKRUN
              LFCLKSTAT
              LFCLKSRCCOPY
              LFCLKSRC
          REGULATORS — Voltage regulators control
            Registers
              SYSTEMOFF
              DCDCEN
      Peripherals
        CRYPTOCELL — ARM TrustZone CryptoCell 310
          Usage
          Always-on (AO) power domain
          Lifecycle state (LCS)
          Cryptographic key selection
            RTL key
            Device root key
          Direct memory access (DMA)
          Standards
          Registers
            ENABLE
          Host interface
            HOST_RGF block
              Registers
                HOST_CRYPTOKEY_SEL
                HOST_IOT_KPRTL_LOCK
                HOST_IOT_KDR0
                HOST_IOT_KDR1
                HOST_IOT_KDR2
                HOST_IOT_KDR3
                HOST_IOT_LCS
        DPPI - Distributed programmable peripheral interconnect
          Subscribing to and publishing on channels
          DPPI configuration (DPPIC)
          Connection examples
          Special considerations for a system implementing TrustZone for Cortex-M processors
          Registers
            TASKS_CHG[n].EN
            TASKS_CHG[n].DIS
            SUBSCRIBE_CHG[n].EN
            SUBSCRIBE_CHG[n].DIS
            CHEN
            CHENSET
            CHENCLR
            CHG[n]
        EGU — Event generator unit
          Registers
            TASKS_TRIGGER[n]
            SUBSCRIBE_TRIGGER[n]
            EVENTS_TRIGGERED[n]
            PUBLISH_TRIGGERED[n]
            INTEN
            INTENSET
            INTENCLR
          Electrical specification
            EGU Electrical Specification
        GPIO — General purpose input/output
          Pin configuration
          Pin sense mechanism
          GPIO security
          Registers
            OUT ( Retained )
            OUTSET
            OUTCLR
            IN
            DIR ( Retained )
            DIRSET
            DIRCLR
            LATCH ( Retained )
            DETECTMODE ( Retained )
            DETECTMODE_SEC ( Retained )
            PIN_CNF[n]
          Electrical specification
            GPIO Electrical Specification
        GPIOTE — GPIO tasks and events
          Pin events and tasks
          Port event
          Tasks and events pin configuration
          Registers
            TASKS_OUT[n]
            TASKS_SET[n]
            TASKS_CLR[n]
            SUBSCRIBE_OUT[n]
            SUBSCRIBE_SET[n]
            SUBSCRIBE_CLR[n]
            EVENTS_IN[n]
            EVENTS_PORT
            PUBLISH_IN[n]
            PUBLISH_PORT
            INTENSET
            INTENCLR
            CONFIG[n]
          Electrical specification
        IPC — Interprocessor communication
          IPC and PPI connections
          Registers
            TASKS_SEND[n]
            SUBSCRIBE_SEND[n]
            EVENTS_RECEIVE[n]
            PUBLISH_RECEIVE[n]
            INTEN
            INTENSET
            INTENCLR
            INTPEND
            SEND_CNF[n]
            RECEIVE_CNF[n]
            GPMEM[n]
          Electrical specification
            IPC Electrical Specification
        I2S — Inter-IC sound interface
          Mode
          Transmitting and receiving
          Left right clock (LRCK)
          Serial clock (SCK)
          Master clock (MCK)
          Width, alignment and format
          EasyDMA
          Module operation
          Pin configuration
          Registers
            TASKS_START
            TASKS_STOP
            SUBSCRIBE_START
            SUBSCRIBE_STOP
            EVENTS_RXPTRUPD
            EVENTS_STOPPED
            EVENTS_TXPTRUPD
            PUBLISH_RXPTRUPD
            PUBLISH_STOPPED
            PUBLISH_TXPTRUPD
            INTEN
            INTENSET
            INTENCLR
            ENABLE
            CONFIG.MODE
            CONFIG.RXEN
            CONFIG.TXEN
            CONFIG.MCKEN
            CONFIG.MCKFREQ
            CONFIG.RATIO
            CONFIG.SWIDTH
            CONFIG.ALIGN
            CONFIG.FORMAT
            CONFIG.CHANNELS
            RXD.PTR
            TXD.PTR
            RXTXD.MAXCNT
            PSEL.MCK
            PSEL.SCK
            PSEL.LRCK
            PSEL.SDIN
            PSEL.SDOUT
          Electrical specification
            I2S timing specification
        KMU — Key management unit
          Functional view
          Access control
          Protecting the UICR content
          Usage
            OTP
            Key storage
              Selecting a key slot
              Writing to a key slot
              Reading a key value
              Push over secure APB
              Revoking the key slots
            STATUS register
          Registers
            TASKS_PUSH_KEYSLOT
            EVENTS_KEYSLOT_PUSHED
            EVENTS_KEYSLOT_REVOKED
            EVENTS_KEYSLOT_ERROR
            INTEN
            INTENSET
            INTENCLR
            INTPEND
            STATUS
            SELECTKEYSLOT
        PDM — Pulse density modulation interface
          Master clock generator
          Module operation
          Decimation filter
          EasyDMA
          Hardware example
          Pin configuration
          Registers
            TASKS_START
            TASKS_STOP
            SUBSCRIBE_START
            SUBSCRIBE_STOP
            EVENTS_STARTED
            EVENTS_STOPPED
            EVENTS_END
            PUBLISH_STARTED
            PUBLISH_STOPPED
            PUBLISH_END
            INTEN
            INTENSET
            INTENCLR
            ENABLE
            PDMCLKCTRL
            MODE
            GAINL
            GAINR
            RATIO
            PSEL.CLK
            PSEL.DIN
            SAMPLE.PTR
            SAMPLE.MAXCNT
          Electrical specification
            PDM Electrical Specification
        PWM — Pulse width modulation
          Wave counter
          Decoder with EasyDMA
          Limitations
          Pin configuration
          Registers
            TASKS_STOP
            TASKS_SEQSTART[n]
            TASKS_NEXTSTEP
            SUBSCRIBE_STOP
            SUBSCRIBE_SEQSTART[n]
            SUBSCRIBE_NEXTSTEP
            EVENTS_STOPPED
            EVENTS_SEQSTARTED[n]
            EVENTS_SEQEND[n]
            EVENTS_PWMPERIODEND
            EVENTS_LOOPSDONE
            PUBLISH_STOPPED
            PUBLISH_SEQSTARTED[n]
            PUBLISH_SEQEND[n]
            PUBLISH_PWMPERIODEND
            PUBLISH_LOOPSDONE
            SHORTS
            INTEN
            INTENSET
            INTENCLR
            ENABLE
            MODE
            COUNTERTOP
            PRESCALER
            DECODER
            LOOP
            SEQ[n].PTR
            SEQ[n].CNT
            SEQ[n].REFRESH
            SEQ[n].ENDDELAY
            PSEL.OUT[n]
        RTC — Real-time counter
          Clock source
          Resolution versus overflow and the prescaler
          Counter register
          Overflow
          Tick event
          Event control
          Compare
          Task and event jitter/delay
          Reading the counter register
          Registers
            TASKS_START
            TASKS_STOP
            TASKS_CLEAR
            TASKS_TRIGOVRFLW
            SUBSCRIBE_START
            SUBSCRIBE_STOP
            SUBSCRIBE_CLEAR
            SUBSCRIBE_TRIGOVRFLW
            EVENTS_TICK
            EVENTS_OVRFLW
            EVENTS_COMPARE[n]
            PUBLISH_TICK
            PUBLISH_OVRFLW
            PUBLISH_COMPARE[n]
            INTENSET
            INTENCLR
            EVTEN
            EVTENSET
            EVTENCLR
            COUNTER
            PRESCALER
            CC[n]
          Electrical specification
        SAADC — Successive approximation analog-to-digital converter
          Overview
          Digital output
          Analog inputs and channels
          Operation modes
            One-shot mode
            Continuous mode
            Oversampling
            Scan mode
          EasyDMA
          Resistor ladder
          Reference
          Acquisition time
          Limits event monitoring
          Registers
            TASKS_START
            TASKS_SAMPLE
            TASKS_STOP
            TASKS_CALIBRATEOFFSET
            SUBSCRIBE_START
            SUBSCRIBE_SAMPLE
            SUBSCRIBE_STOP
            SUBSCRIBE_CALIBRATEOFFSET
            EVENTS_STARTED
            EVENTS_END
            EVENTS_DONE
            EVENTS_RESULTDONE
            EVENTS_CALIBRATEDONE
            EVENTS_STOPPED
            EVENTS_CH[n].LIMITH
            EVENTS_CH[n].LIMITL
            PUBLISH_STARTED
            PUBLISH_END
            PUBLISH_DONE
            PUBLISH_RESULTDONE
            PUBLISH_CALIBRATEDONE
            PUBLISH_STOPPED
            PUBLISH_CH[n].LIMITH
            PUBLISH_CH[n].LIMITL
            INTEN
            INTENSET
            INTENCLR
            STATUS
            ENABLE
            CH[n].PSELP
            CH[n].PSELN
            CH[n].CONFIG
            CH[n].LIMIT
            RESOLUTION
            OVERSAMPLE
            SAMPLERATE
            RESULT.PTR
            RESULT.MAXCNT
            RESULT.AMOUNT
          Electrical specification
            SAADC Electrical Specification
          Performance factors
        SPIM — Serial peripheral interface master with EasyDMA
          SPI master transaction sequence
          Master mode pin configuration
          Shared resources
          EasyDMA
          Low power
          Registers
            TASKS_START
            TASKS_STOP
            TASKS_SUSPEND
            TASKS_RESUME
            SUBSCRIBE_START
            SUBSCRIBE_STOP
            SUBSCRIBE_SUSPEND
            SUBSCRIBE_RESUME
            EVENTS_STOPPED
            EVENTS_ENDRX
            EVENTS_END
            EVENTS_ENDTX
            EVENTS_STARTED
            PUBLISH_STOPPED
            PUBLISH_ENDRX
            PUBLISH_END
            PUBLISH_ENDTX
            PUBLISH_STARTED
            SHORTS
            INTENSET
            INTENCLR
            ENABLE
            PSEL.SCK
            PSEL.MOSI
            PSEL.MISO
            FREQUENCY
            RXD.PTR
            RXD.MAXCNT
            RXD.AMOUNT
            RXD.LIST
            TXD.PTR
            TXD.MAXCNT
            TXD.AMOUNT
            TXD.LIST
            CONFIG
            ORC
          Electrical specification
            SPIM master interface electrical specifications
            Serial Peripheral Interface Master (SPIM) timing specifications
        SPIS — Serial peripheral interface slave with EasyDMA
          Shared resources
          EasyDMA
          SPI slave operation
          Semaphore operation
          Pin configuration
          Registers
            TASKS_ACQUIRE
            TASKS_RELEASE
            SUBSCRIBE_ACQUIRE
            SUBSCRIBE_RELEASE
            EVENTS_END
            EVENTS_ENDRX
            EVENTS_ACQUIRED
            PUBLISH_END
            PUBLISH_ENDRX
            PUBLISH_ACQUIRED
            SHORTS
            INTENSET
            INTENCLR
            SEMSTAT
            STATUS
            ENABLE
            PSEL.SCK
            PSEL.MISO
            PSEL.MOSI
            PSEL.CSN
            PSELSCK ( Deprecated )
            PSELMISO ( Deprecated )
            PSELMOSI ( Deprecated )
            PSELCSN ( Deprecated )
            RXDPTR ( Deprecated )
            MAXRX ( Deprecated )
            AMOUNTRX ( Deprecated )
            RXD.PTR
            RXD.MAXCNT
            RXD.AMOUNT
            RXD.LIST
            TXDPTR ( Deprecated )
            MAXTX ( Deprecated )
            AMOUNTTX ( Deprecated )
            TXD.PTR
            TXD.MAXCNT
            TXD.AMOUNT
            TXD.LIST
            CONFIG
            DEF
            ORC
          Electrical specification
            SPIS slave interface electrical specifications
            Serial Peripheral Interface Slave (SPIS) timing specifications
        SPU - System protection unit
          General concepts
            Special considerations for ARM TrustZone for Cortex-M enabled system
          Flash access control
            Non-secure callable (NSC) region definition in flash
            Flash access error reporting
            UICR and FICR protections
          RAM access control
            Non-secure callable (NSC) region definition in RAM
            RAM access error reporting
          Peripheral access control
            Peripherals with split security
            Peripheral address mapping
            Special considerations for peripherals with DMA master
            Peripheral access error reporting
          Pin access control
            Direct pin control through the GPIO peripheral
          DPPI access control
            Special considerations regarding the DPPIC configuration registers
          External domain access control
          TrustZone for Cortex-M ID allocation
          Registers
            EVENTS_RAMACCERR
            EVENTS_FLASHACCERR
            EVENTS_PERIPHACCERR
            PUBLISH_RAMACCERR
            PUBLISH_FLASHACCERR
            PUBLISH_PERIPHACCERR
            INTEN
            INTENSET
            INTENCLR
            CAP
            EXTDOMAIN[n].PERM
            DPPI[n].PERM
            DPPI[n].LOCK
            GPIOPORT[n].PERM
            GPIOPORT[n].LOCK
            FLASHNSC[n].REGION
            FLASHNSC[n].SIZE
            RAMNSC[n].REGION
            RAMNSC[n].SIZE
            FLASHREGION[n].PERM
            RAMREGION[n].PERM
            PERIPHID[n].PERM
        TIMER — Timer/counter
          Capture
          Compare
          Task delays
          Task priority
          Registers
            TASKS_START
            TASKS_STOP
            TASKS_COUNT
            TASKS_CLEAR
            TASKS_SHUTDOWN ( Deprecated )
            TASKS_CAPTURE[n]
            SUBSCRIBE_START
            SUBSCRIBE_STOP
            SUBSCRIBE_COUNT
            SUBSCRIBE_CLEAR
            SUBSCRIBE_SHUTDOWN ( Deprecated )
            SUBSCRIBE_CAPTURE[n]
            EVENTS_COMPARE[n]
            PUBLISH_COMPARE[n]
            SHORTS
            INTENSET
            INTENCLR
            MODE
            BITMODE
            PRESCALER
            ONESHOTEN[n]
            CC[n]
          Electrical specification
        TWIM — I2C compatible two-wire interface master with EasyDMA
          Shared resources
          EasyDMA
          Master write sequence
          Master read sequence
          Master repeated start sequence
          Low power
          Master mode pin configuration
          Registers
            TASKS_STARTRX
            TASKS_STARTTX
            TASKS_STOP
            TASKS_SUSPEND
            TASKS_RESUME
            SUBSCRIBE_STARTRX
            SUBSCRIBE_STARTTX
            SUBSCRIBE_STOP
            SUBSCRIBE_SUSPEND
            SUBSCRIBE_RESUME
            EVENTS_STOPPED
            EVENTS_ERROR
            EVENTS_SUSPENDED
            EVENTS_RXSTARTED
            EVENTS_TXSTARTED
            EVENTS_LASTRX
            EVENTS_LASTTX
            PUBLISH_STOPPED
            PUBLISH_ERROR
            PUBLISH_SUSPENDED
            PUBLISH_RXSTARTED
            PUBLISH_TXSTARTED
            PUBLISH_LASTRX
            PUBLISH_LASTTX
            SHORTS
            INTEN
            INTENSET
            INTENCLR
            ERRORSRC
            ENABLE
            PSEL.SCL
            PSEL.SDA
            FREQUENCY
            RXD.PTR
            RXD.MAXCNT
            RXD.AMOUNT
            RXD.LIST
            TXD.PTR
            TXD.MAXCNT
            TXD.AMOUNT
            TXD.LIST
            ADDRESS
          Electrical specification
            TWIM interface electrical specifications
            Two Wire Interface Master (TWIM) timing specifications
          Pullup resistor
        TWIS — I2C compatible two-wire interface slave with EasyDMA
          Shared resources
          EasyDMA
          TWI slave responding to a read command
          TWI slave responding to a write command
          Master repeated start sequence
          Terminating an ongoing TWI transaction
          Low power
          Slave mode pin configuration
          Registers
            TASKS_STOP
            TASKS_SUSPEND
            TASKS_RESUME
            TASKS_PREPARERX
            TASKS_PREPARETX
            SUBSCRIBE_STOP
            SUBSCRIBE_SUSPEND
            SUBSCRIBE_RESUME
            SUBSCRIBE_PREPARERX
            SUBSCRIBE_PREPARETX
            EVENTS_STOPPED
            EVENTS_ERROR
            EVENTS_RXSTARTED
            EVENTS_TXSTARTED
            EVENTS_WRITE
            EVENTS_READ
            PUBLISH_STOPPED
            PUBLISH_ERROR
            PUBLISH_RXSTARTED
            PUBLISH_TXSTARTED
            PUBLISH_WRITE
            PUBLISH_READ
            SHORTS
            INTEN
            INTENSET
            INTENCLR
            ERRORSRC
            MATCH
            ENABLE
            PSEL.SCL
            PSEL.SDA
            RXD.PTR
            RXD.MAXCNT
            RXD.AMOUNT
            RXD.LIST
            TXD.PTR
            TXD.MAXCNT
            TXD.AMOUNT
            TXD.LIST
            ADDRESS[n]
            CONFIG
            ORC
          Electrical specification
            TWIS slave timing specifications
        UARTE — Universal asynchronous receiver/transmitter with EasyDMA
          EasyDMA
          Transmission
          Reception
          Error conditions
          Using the UARTE without flow control
          Parity and stop bit configuration
          Low power
          Pin configuration
          Registers
            TASKS_STARTRX
            TASKS_STOPRX
            TASKS_STARTTX
            TASKS_STOPTX
            TASKS_FLUSHRX
            SUBSCRIBE_STARTRX
            SUBSCRIBE_STOPRX
            SUBSCRIBE_STARTTX
            SUBSCRIBE_STOPTX
            SUBSCRIBE_FLUSHRX
            EVENTS_CTS
            EVENTS_NCTS
            EVENTS_RXDRDY
            EVENTS_ENDRX
            EVENTS_TXDRDY
            EVENTS_ENDTX
            EVENTS_ERROR
            EVENTS_RXTO
            EVENTS_RXSTARTED
            EVENTS_TXSTARTED
            EVENTS_TXSTOPPED
            PUBLISH_CTS
            PUBLISH_NCTS
            PUBLISH_RXDRDY
            PUBLISH_ENDRX
            PUBLISH_TXDRDY
            PUBLISH_ENDTX
            PUBLISH_ERROR
            PUBLISH_RXTO
            PUBLISH_RXSTARTED
            PUBLISH_TXSTARTED
            PUBLISH_TXSTOPPED
            SHORTS
            INTEN
            INTENSET
            INTENCLR
            ERRORSRC
            ENABLE
            PSEL.RTS
            PSEL.TXD
            PSEL.CTS
            PSEL.RXD
            BAUDRATE
            RXD.PTR
            RXD.MAXCNT
            RXD.AMOUNT
            TXD.PTR
            TXD.MAXCNT
            TXD.AMOUNT
            CONFIG
          Electrical specification
            UARTE electrical specification
        WDT — Watchdog timer
          Reload criteria
          Temporarily pausing the watchdog
          Watchdog reset
          Registers
            TASKS_START
            SUBSCRIBE_START
            EVENTS_TIMEOUT
            PUBLISH_TIMEOUT
            INTENSET
            INTENCLR
            RUNSTATUS
            REQSTATUS
            CRV
            RREN
            CONFIG
            RR[n]
          Electrical specification
            Watchdog Timer Electrical Specification
      LTE modem
        Introduction
        SIM card interface
        LTE modem coexistence interface
        LTE modem RF control external interface
        RF front-end interface
        Electrical specification
          Key RF parameters for Cat-M1
          Key RF parameters for Cat-NB1 and Cat-NB2
          Receiver parameters for Cat-M1
          Receiver parameters for Cat-NB1 and Cat-NB2
          Transmitter parameters for Cat-M1
          Transmitter parameters for Cat-NB1 and Cat-NB2
      GPS receiver
        Electrical specification
      Debug and trace
        Overview
          Special consideration regarding debugger access
          DAP - Debug access port
          Debug interface mode
          Real-time debug
          Trace
          Registers
            TARGETID
          Electrical specification
            Trace port
        CTRL-AP - Control access port
          Reset request
          Erase all
          Mailbox interface
          Disabling erase protection
          Registers
            RESET
            ERASEALL
            ERASEALLSTATUS
            APPROTECT.STATUS
            ERASEPROTECT.STATUS
            ERASEPROTECT.DISABLE
            MAILBOX.TXDATA
            MAILBOX.TXSTATUS
            MAILBOX.RXDATA
            MAILBOX.RXSTATUS
            IDR
          Registers
            MAILBOX.RXDATA
            MAILBOX.RXSTATUS
            MAILBOX.TXDATA
            MAILBOX.TXSTATUS
            ERASEPROTECT.LOCK
            ERASEPROTECT.DISABLE
        TAD - Trace and debug control
          Registers
            CLOCKSTART
            CLOCKSTOP
            ENABLE
            PSEL.TRACECLK
            PSEL.TRACEDATA0
            PSEL.TRACEDATA1
            PSEL.TRACEDATA2
            PSEL.TRACEDATA3
            TRACEPORTSPEED ( Retained )
      Hardware and layout
        Pin assignments
          Pin assignments
        Mechanical specifications
          16.00 x 10.50 mm package
        Reference circuitry
          Schematic SIxA LGA127
      Operating conditions
        VDD_GPIO considerations
      Absolute maximum ratings
      Ordering information
        IC marking
        Box labels
        Order code
        Code ranges and values
        Product options
      Regulatory information
      Legal notices
    Errata
      nRF9160 Revision 1 Errata
        Change log
        New and inherited anomalies
          [1] I2S: Excessive power consumption after using STOP task
          [2] NVMC: CPU code execution from RAM halted during flash page erase operation
          [4] GPIO: Bits in GPIO LATCH register are incorrectly set to 1
          [6] POWER: SLEEPENTER and SLEEPEXIT events asserted after pin reset
          [7] KMU: Subsequent accesses between info_mem and main_mem of the flash may not work properly
          [9] SAADC: Reduced SFDR
          [15] REGULATORS: Supply regulators default to LDO mode after reset
          [21] NVMC: Disabling instruction cache causes skip of next instruction
          [23] UART: TASKS_RESUME impacts UARTE
          [24] NVMC: CPU is not halted for page erase in debug session
          [26] CLOCK, LFXO: System locks up when set in System ON IDLE while waiting for EVENTS_LFCLKSTARTED
          [27] CryptoCell: Arm CryptoCell true random number generator (TRNG) has wrong configuration
          [28] SAADC: Events are not generated when switching from scan mode to no-scan mode
          [29] Debug and Trace: System reset does not work
          [30] PWM: False SEQEND[0] and SEQEND[1] events are generated
          [31] LFXO: LFXO startup fails
        Fixed anomalies
      nRF9160 Engineering A Errata
        Change log
        New and inherited anomalies
          [1] I2S: Excessive power consumption after using STOP task
          [2] NVMC: CPU code execution from RAM halted during flash page erase operation
          [4] GPIO: Bits in GPIO LATCH register are incorrectly set to 1
          [6] POWER: SLEEPENTER and SLEEPEXIT events asserted after pin reset
          [7] KMU: Subsequent accesses between info_mem and main_mem of the flash may not work properly
          [8] SAADC: Reduced SFDR
          [10] LTE Modem: MAGPIO and MIPI RFFE - high initial voltage
          [12] Debug and Trace: SWD debugger scan
          [14] REGULATORS: Supply regulators default to LDO mode after reset
          [16] SAADC: SAADC result
          [17] Debug and Trace: LTE modem stops when debugging through SWD interface
          [20] RAM: RAM content cannot be trusted upon waking up from System ON IDLE or System OFF mode
          [21] NVMC: Disabling instruction cache causes skip of next instruction
          [23] UART: TASKS_RESUME impacts UARTE
          [24] NVMC: CPU is not halted for page erase in debug session
          [26] CLOCK, LFXO: System locks up when set in System ON IDLE while waiting for EVENTS_LFCLKSTARTED
          [28] SAADC: Events are not generated when switching from scan mode to no-scan mode
          [29] Debug and Trace: System reset does not work
          [30] PWM: False SEQEND[0] and SEQEND[1] events are generated
          [31] LFXO: LFXO startup fails
    PCN and IN
      IN114 Informational Notice v1.0
    Compatibility Matrix
      IC revisions and variants
      Documentation and reference design files
      nRF Connect SDK
      Development HW
      Revision history
    nRF9160 DK
      Revision history
      Kit content
        Hardware content
        Related documentation
      Operating modes
        Firmware development mode
          Device programming
          Virtual COM port
          MSD
          Reset
        Performance measurement mode
          USB detect
      Hardware description
        Block diagram
        Hardware figures
        Power supply
          nRF9160 supply
          VDD supply rail
          Other power domains
        Antenna interfaces
        GPS
        GPIO interfaces
        nRF52840
          nRF9160 DK board control
          Bluetooth/IEEE 802.15.4 network processor
        Buttons, slide switches, and LEDs
        Debug input and trace options
          Debug output
        Signal routing switches
          Interface MCU disconnect switches
          Switches for UART interface
          Switches for buttons and LEDs
          Switches for nRF52840 interface
        SIM and eSIM
        Additional nRF9160 interfaces
        SiP enable
        Solder bridge configuration
      Measuring current
        Preparing the development kit for current measurements
        Using an oscilloscope for current profile measurement
        Using a current meter for current measurement
      RF measurements
      Radiated performance of nRF9160 DK
      Glossary
        Band-Pass Filter (BPF)
        Cat-M1
        Cat-NB1
        Clear to Send (CTS)
        DK (Development Kit)
        Fast Identity Online (FIDO)
        Global Positioning System (GPS)
        Hardware Flow Control (HWFC)
        Inter-integrated Circuit (I2C)
        Low-Dropout Regulator (LDO)
        Low-Noise Amplifier (LNA)
        nRF Cloud
        Operational Amplifier (op-amp)
        Receive Data (RXD)
        Request to Send (RTS)
        SAW filter
        Surface Acoustic Wave (SAW)
        System in Package (SiP)
        System on Chip (SoC)
        Transmit Data (TXD)
      Acronyms and abbreviations
      Legal notices
    nRF9160 DK Errata v0.7
  nRF91 AT Commands
    Revision history
    AT command syntax
      Set command <CMD>[=...]
      Read command <CMD>?
      Test command <CMD>=?
      Response
    General
      Request manufacturer identification +CGMI
        Set command
        Read command
        Test command
      Request model identification +CGMM
        Set command
        Read command
        Test command
      Request revision identification +CGMR
        Set command
        Read command
        Test command
      Request product serial number identification +CGSN
        Set command
        Read command
        Test command
      Request IMSI +CIMI
        Set command
        Read command
        Test command
    Mobile termination control and status commands
      Functional mode +CFUN
        Set command
        Read command
        Test command
      PIN code +CPIN
        Set command
        Read command
        Test command
      Remaining PIN retries +CPINR
        Set command
        Read command
        Test command
      List all available AT commands +CLAC
        Set command
        Read command
        Test command
      Extended signal quality +CESQ
        Set command
        Read command
        Test command
      Signal quality notification %CESQ
        Set command
        Read command
        Test command
      SNR signal quality notification %XSNRSQ
        Set command
        Read command
        Test command
      Restricted SIM access +CRSM
        Set command
        Read command
        Test command
      Generic SIM access +CSIM
        Set command
        Read command
        Test command
      Device activity status +CPAS
        Set command
        Read command
        Test command
      Indicator control +CIND
        Set command
        Read command
        Test command
      IP address format +CGPIAF
        Set command
        Read command
        Test command
      Current band %XCBAND
        Set command
        Read command
        Test command
      Read neighbor cells %NBRGRSRP
        Set command
        Read command
        Test command
      Mode of operation (CS/PS) +CEMODE
        Set command
        Read command
        Test command
      UICC state %XSIM
        Set command
        Read command
        Test command
      Authenticated access %XSUDO
        Set command
        Read command
        Test command
      Public key storage management %XPMNG
        Set command
        Read command
        Test command
      RF test execution %XRFTEST
        Set command
          RX testing
          TX testing
          GPS SNR testing
          RX SNR testing
        Read command
        Test command
      Band lock %XBANDLOCK
        Set command
        Read command
        Test command
      Data profile %XDATAPRFL
        Set command
        Read command
        Test command
      Connectivity statistics %XCONNSTAT
        Set command
        Read command
        Test command
      Battery voltage %XVBAT
        Set command
        Read command
        Test command
      Customer production done %XPRODDONE
        Set command
        Read command
        Test command
      Credential storage management %CMNG
        Set command
        Read command
        Test command
      Internal temperature %XTEMP
        Set command
        Read command
        Test command
      High level for internal temperature %XTEMPHIGHLVL
        Set command
        Read command
        Test command
      Clock +CCLK
        Set command
        Read command
        Test command
      Modem trace activation %XMODEMTRACE
        Set command
        Read command
        Test command
      System mode %XSYSTEMMODE
        Set command
        Read command
        Test command
      PTW setting %XPTW
        Set command
        Read command
        Test command
    SiP pin configuration
      COEX0 pin control configuration %XCOEX0
        Set command
        Read command
        Test command
      MAGPIO configuration %XMAGPIO
        Set command
        Read command
        Test command
      SiP-external MIPIRFFE device introduction %XMIPIRFFEDEV
        Set command
        Read command
        Delete configuration
      SiP-external MIPIRFFE device control configuration %XMIPIRFFECTRL
        Set command
        Use cases INIT(0), OFF(2), and PWROFF(3)
        Use case ON(1)
        Delete configuration
    Packet domain commands
      Define PDP Context +CGDCONT
        Set command
        Read command
        Test command
      Packet domain event reporting +CGEREP
        Set command
        Read command
        Test command
      Packet domain event unsolicited result codes +CGEV
      PDP context activate +CGACT
        Set command
        Read command
        Test command
      Allocate new CID %XNEWCID
        Set command
        Read command
        Test command
      Map CID to PDN ID %XGETPDNID
        Set command
        Read command
        Test command
      QoS dynamic params +CGEQOSRDP
        Set command
        Read command
        Test command
      Show PDP address(es) +CGPADDR
        Set command
        Read command
        Test command
      PDN connection dynamic parameters +CGCONTRDP
        Set command
        Read command
        Test command
      PS attach or detach +CGATT
        Set command
        Read command
        Test command
      Power preference indication for EPS +CEPPI
        Set command
        Read command
        Test command
      Protocol configuration options notification %XPCO
        Set command
        Read command
        Test command
      Usage of ePCO/PCO in PDN connection establishment %XEPCO
        Set command
        Read command
        Test command
      APN class access %XAPNCLASS
        Set command
        Read command
        Test command
      External IP stack IPv6 address resolution/refresh failure %XIPV6FAIL
        Set command
        Read command
        Test command
      Define PDN connection authentication parameters +CGAUTH
        Set command
        Read command
        Test command
    Network service related commands
      PLMN selection +COPS
        Set command
        Read command
        Test command
      Power saving mode setting +CPSMS
        Set command
        Read command
        Test command
      eDRX setting +CEDRXS
        Set command
        Read command
        Test command
      Read EDRX dynamic parameters +CEDRXRDP
        Set command
        Read command
        Test command
      Subscriber number +CNUM
        Set command
        Read command
        Test command
      Read operator name +COPN
        Set command
        Read command
        Test command
      Facility lock +CLCK
        Set command
        Read command
        Test command
      Change password +CPWD
        Set command
        Read command
        Test command
      Network registration status +CEREG
        Set command
        Read command
        Test command
      Subscribe unsolicited operator name indications %XOPNAME
        Set command
        Read command
        Test command
      Subscribe unsolicited network time notifications %XTIME
        Set command
        Read command
        Test command
      Set release assistance information %XRAI
        Set command
        Read command
        Test command
      Operator ID %XOPERID
        Set command
        Read command
        Test command
      Read modem parameters %XMONITOR
        Set command
        Read command
        Test command
    Mobile termination errors
      Report mobile termination errors +CMEE
        Set command
        Read command
        Test command
      Report network error codes +CNEC
        Set command
        Read command
        Test command
      Extended error report +CEER
        Set command
        Read command
        Test command
    SMS commands
      Message format +CMGF
        Set command
        Read command
        Test command
      New message indications +CNMI
        Set command
        Read command
        Test command
      Send message, PDU mode + CMGS
        Set command
        Read command
        Test command
      Received SMS notification in PDU mode +CMT
      Delivery status notification in PDU mode +CDS
      New message ACK, PDU mode +CNMA
        Set command
        Read command
        Test command
      New message ACK, text mode +CNMA
        Set command
        Read command
        Test command
      Preferred message storage +CPMS
        Set command
        Read command
        Test command
      Message service failure result code +CMS ERROR
      Select SMS service +CGSMS
        Set command
        Read command
        Test command
      Short message memory available %XSMMA
        Set command
        Read command
        Test command
    Authenticating AT command usage
    Glossary
      16-state Quadrature Amplitude Modulation (16-QAM)
      Access Point Name (APN)
      Binary Phase-Shift Keying (BPSK)
      Carrier Wave (CW)
      Cat-M1
      Cat-NB1
      Check Digit (CD)
      Classless Inter-domain Routing (CIDR)
      CS/PS Mode of Operation
      Discontinuous Reception (DRX)
      Dynamic Host Configuration Protocol (DHCP)
      Electronic Serial Number (ESN)
      EPS Mobility Management (EMM)
      E-UTRA Absolute Radio Frequency Channel Number (EARFCN)
      Evolved Packet System (EPS)
      Extended Discontinuous Reception (eDRX)
      Global Navigation Satellite System (GNSS)
      International Mobile (Station) Equipment Identity (IMEI)
      International Mobile (Station) Equipment Identity, Software Version (IMEISV)
      International Mobile Subscriber Identity (IMSI)
      International Reference Alphabet (IRA)
      Low-Noise Amplifier (LNA)
      Maximum Transmission Unit (MTU)
      MIPI RF Front-End Control Interface (RFFE)
      Mobile Country Code (MCC)
      Mobile Equipment (ME)
      Mobile Network Code (MNC)
      Mobile Station International Subscriber Directory Number (MSISDN)
      Mobile Termination (MT)
      Non-access Stratum (NAS)
      Non-access Stratum (NAS) Signalling Low Priority Indication (NSLPI)
      Non-volatile Memory (NVM)
      Packet Data Network (PDN)
      Packet Data Protocol (PDP)
      Packet Data Protocol (PDP) Context
      Paging Time Window (PTW)
      Personal Identification Number (PIN)
      Personal Unblocking Key (PUK)
      Power Saving Mode (PSM)
      Pre-shared Key (PSK)
      Privacy Enhanced Mail (PEM)
      Protocol Configuration Options (PCO)
      Protocol Data Unit (PDU)
      PS Mode of Operation
      Public Land Mobile Network (PLMN)
      Quadrature Phase-Shift Keying (QPSK)
      Quality of Service (QoS)
      Reference Signal Received Power (RSRP)
      Resource Block (RB)
      RP-SMMA
      Serial Number (SNR)
      Signal-to-Noise Ratio (SNR)
      Software Version Number (SVN)
      Subscriber Identity Module (SIM)
      System in Package (SiP)
      Terminal Adapter (TA)
      Terminal Equipment (TE)
      Tracking Area Code (TAC)
      Tracking Area Update (TAU)
      Type Allocation Code (TAC)
      Universal Integrated Circuit Card (UICC)
      Unique Slave Identifier (USID)
      Universal Subscriber Identity Module (USIM)
      User Equipment (UE)
    Acronyms and abbreviations
    Legal notices
  Environmental Qualification Reports
    HSR nRF9160-SIxx (Qorvo) 2019-03
nRF53 Series
  nRF5340
    nRF5340 Objective Product Specification
      Revision history
      About this document
        Document status
        Peripheral chapters
        Register tables
          Fields and values
          Permissions
        Registers
          DUMMY
      Product overview
        Block diagram
        Memory
          RAM - Random access memory
          Flash (non-volatile memory)
          XIP - Execute in place
          Access latency
      Power and clock management
        Overview
          System ON mode
            Power submodes
          System OFF mode
            Emulated System OFF mode
          Core Force-off mode
            Emulated Force-off mode
        Current consumption
          Electrical specification
            Sleep
            Application CPU running
            Network CPU running
            COMP active
            LPCOMP active
            NFCT active
            RADIO transmitting/receiving
            RNG active
            SAADC active
            TEMP active
            TIMER running
            WDT active
            Compounded
            USBD active
        Power supply modes and regulators
          Normal voltage mode
          High voltage mode
          Power supply supervisor
            Power-fail comparator
        POWER — Power control
          Registers
            TASKS_CONSTLAT
            TASKS_LOWPWR
            SUBSCRIBE_CONSTLAT
            SUBSCRIBE_LOWPWR
            EVENTS_POFWARN
            EVENTS_SLEEPENTER
            EVENTS_SLEEPEXIT
            PUBLISH_POFWARN
            PUBLISH_SLEEPENTER
            PUBLISH_SLEEPEXIT
            INTEN
            INTENSET
            INTENCLR
            GPREGRET[n]
        REGULATORS - Regulator control
          Normal voltage mode - detailed setup
          High voltage mode - detailed setup
            External circuitry supply
          GPIO levels
          Registers
            MAINREGSTATUS ( Retained )
            SYSTEMOFF
            POFCON ( Retained )
            VREGMAIN.DCDCEN ( Retained )
            VREGRADIO.DCDCEN ( Retained )
            VREGH.DCDCEN ( Retained )
          Electrical specification
            Regulator startup times
            Application core startup times
            Network core startup times
            Power-fail comparator
            Regulator specifications, VREGH stage
        USBREG - USB regulator control
          Registers
            EVENTS_USBDETECTED
            EVENTS_USBREMOVED
            EVENTS_USBPWRRDY
            PUBLISH_USBDETECTED
            PUBLISH_USBREMOVED
            PUBLISH_USBPWRRDY
            INTEN
            INTENSET
            INTENCLR
            USBREGSTATUS
          Electrical specification
            USB operating conditions
            USB regulator specifications
            VBUS detection specifications
        VREQCTRL - Voltage request control
          Registers
            VREGRADIO.VREQH ( Retained )
            VREGRADIO.VREQHREADY
        RESET - Reset control
          Power-on reset
          Pin reset
          Brownout reset
          Wakeup from System OFF mode reset
          Soft reset
          Watchdog timer reset
          Network force off
          Retained registers
          Application core reset behavior
          Network core reset behavior
          Registers
            RESETREAS
            NETWORK.FORCEOFF
        CLOCK — Clock control
          HFCLK controller
            Application core frequency scaling
            32 MHz crystal oscillator (HFXO)
            Audio oscillator
            Overriding the automatic HFCLK control system
          LFCLK controller
            32.768 kHz RC oscillator (LFRC)
              Calibrating the 32.768 kHz RC oscillator
            32.768 kHz ultra-low power RC oscillator (LFULP)
            32.768 kHz crystal oscillator (LFXO)
            32.768 kHz synthesized from HFCLK (LFSYNT)
            Overriding the automatic LFCLK control system
          Registers
            TASKS_HFCLKSTART
            TASKS_HFCLKSTOP
            TASKS_LFCLKSTART
            TASKS_LFCLKSTOP
            TASKS_CAL
            TASKS_HFCLKAUDIOSTART
            TASKS_HFCLKAUDIOSTOP
            TASKS_HFCLK192MSTART
            TASKS_HFCLK192MSTOP
            SUBSCRIBE_HFCLKSTART
            SUBSCRIBE_HFCLKSTOP
            SUBSCRIBE_LFCLKSTART
            SUBSCRIBE_LFCLKSTOP
            SUBSCRIBE_CAL
            SUBSCRIBE_HFCLKAUDIOSTART
            SUBSCRIBE_HFCLKAUDIOSTOP
            SUBSCRIBE_HFCLK192MSTART
            SUBSCRIBE_HFCLK192MSTOP
            EVENTS_HFCLKSTARTED
            EVENTS_LFCLKSTARTED
            EVENTS_DONE
            EVENTS_HFCLKAUDIOSTARTED
            EVENTS_HFCLK192MSTARTED
            PUBLISH_HFCLKSTARTED
            PUBLISH_LFCLKSTARTED
            PUBLISH_DONE
            PUBLISH_HFCLKAUDIOSTARTED
            PUBLISH_HFCLK192MSTARTED
            INTEN
            INTENSET
            INTENCLR
            INTPEND
            HFCLKRUN
            HFCLKSTAT
            LFCLKRUN
            LFCLKSTAT
            LFCLKSRCCOPY
            HFCLKAUDIORUN
            HFCLKAUDIOSTAT
            HFCLK192MRUN
            HFCLK192MSTAT
            HFCLKSRC
            LFCLKSRC
            HFCLKCTRL
            HFCLKAUDIO.FREQUENCY
            HFCLKALWAYSRUN
            LFCLKALWAYSRUN
            HFCLKAUDIOALWAYSRUN
            HFCLK192MSRC
            HFCLK192MALWAYSRUN
            HFCLK192MCTRL
          Electrical specification
            128 MHz clock source (HFCLK128M)
            64 MHz clock source (HFCLK64M)
            192 MHz clock source (HFCLK192M)
            Audio clock source (HFCLKAUDIO)
            32 MHz crystal oscillator (HFXO)
            32.768 kHz crystal oscillator (LFXO)
            32.768 kHz RC oscillator (LFRC)
            32.768 kHz ultra-low power RC oscillator (LFULP)
            Synthesized 32.768 kHz clock (LFSYNT)
        OSCILLATORS — Oscillator control
          High-frequency (32 MHz) crystal oscillator (HFXO)
            Using internal capacitors
          Low-frequency (32.768 kHz) crystal oscillator (LFXO)
            Using internal capacitors
          Low-frequency (32.768 kHz) external source
          Registers
            XOSC32MCAPS ( Retained )
            XOSC32KI.BYPASS ( Retained )
            XOSC32KI.INTCAP ( Retained )
      Application core
        Application core overview
        CPU
          Floating point interrupt
          Electrical specification
            CPU performance
          CPU and support module configuration
        Memory
          Peripheral instantiation
        Core components
          CACHE — Instruction/data cache
            Cache content
            Profiling
            Registers
              PROFILING[n].IHIT
              PROFILING[n].IMISS
              PROFILING[n].DHIT
              PROFILING[n].DMISS
              ENABLE
              INVALIDATE
              ERASE
              PROFILINGENABLE
              PROFILINGCLEAR
              MODE
              DEBUGLOCK
              ERASESTATUS
              WRITELOCK
            Registers
              SET[n].WAY[o]
            Registers
              SET[n].WAY[o].DATA0
              SET[n].WAY[o].DATA1
              SET[n].WAY[o].DATA2
              SET[n].WAY[o].DATA3
          FICR — Factory information configuration registers
            Registers
              INFO.CONFIGID
              INFO.DEVICEID[n]
              INFO.PART
              INFO.VARIANT
              INFO.PACKAGE
              INFO.RAM
              INFO.FLASH
              INFO.CODEPAGESIZE
              INFO.CODESIZE
              INFO.DEVICETYPE
              TRIMCNF[n].ADDR
              TRIMCNF[n].DATA
              NFC.TAGHEADER0
              NFC.TAGHEADER1
              NFC.TAGHEADER2
              NFC.TAGHEADER3
              TRNG90B.BYTES
              TRNG90B.RCCUTOFF
              TRNG90B.APCUTOFF
              TRNG90B.STARTUP
              TRNG90B.ROSC1
              TRNG90B.ROSC2
              TRNG90B.ROSC3
              TRNG90B.ROSC4
              XOSC32MTRIM
          UICR — User information configuration registers
            Registers
              APPROTECT
              EXTSUPPLY
              VREGHVOUT
              HFXOCNT
              SECUREAPPROTECT
              ERASEPROTECT
              TINSTANCE
              NFCPINS
              OTP[n]
              KEYSLOT.CONFIG[n].DEST
              KEYSLOT.CONFIG[n].PERM
              KEYSLOT.KEY[n].VALUE[o]
          AHB multilayer
            AHB multilayer priorities
      Network core
        Network core overview
        CPU
          Electrical specification
            CPU performance
          CPU and support module configuration
        Memory
          Peripheral instantiation
        Core components
          FICR — Factory information configuration registers
            Registers
              INFO.CONFIGID
              INFO.DEVICEID[n]
              INFO.PART
              INFO.VARIANT
              INFO.PACKAGE
              INFO.RAM
              INFO.FLASH
              INFO.CODEPAGESIZE
              INFO.CODESIZE
              INFO.DEVICETYPE
              ER[n]
              IR[n]
              DEVICEADDRTYPE
              DEVICEADDR[n]
              TRIMCNF[n].ADDR
              TRIMCNF[n].DATA
          UICR — User information configuration registers
            Registers
              APPROTECT
              ERASEPROTECT
              NRFFW[n]
              CUSTOMER[n]
          AHB multilayer
            AHB multilayer priorities
      Peripherals
        Instantiation
        Peripheral interface
          Peripheral ID
          Peripherals with shared ID
          Peripheral registers
          Bit set and clear
          Tasks
          Events
          Publish and subscribe
          Shortcuts
          Interrupts
            Interrupt clearing and disabling
          Secure/non-secure peripherals
        EasyDMA
          EasyDMA error handling
          EasyDMA array list
        ACL — Access control lists
          Registers
            ACL[n].ADDR
            ACL[n].SIZE
            ACL[n].PERM
        AAR — Accelerated address resolver
          Shared resources
          EasyDMA
          Resolving a resolvable address
          Use case example for chaining RADIO packet reception with address resolution using AAR
          IRK data structure
          Registers
            TASKS_START
            TASKS_STOP
            SUBSCRIBE_START
            SUBSCRIBE_STOP
            EVENTS_END
            EVENTS_RESOLVED
            EVENTS_NOTRESOLVED
            PUBLISH_END
            PUBLISH_RESOLVED
            PUBLISH_NOTRESOLVED
            INTENSET
            INTENCLR
            STATUS
            ENABLE
            NIRK
            IRKPTR
            ADDRPTR
            SCRATCHPTR
          Electrical specification
            AAR Electrical Specification
        CCM — AES CCM mode encryption
          Shared resources
          Keystream generation
          Encryption
          Decryption
          AES CCM and radio concurrent operation
          Encrypting packets on-the-fly in radio transmit mode
          Decrypting packets on-the-fly in radio receive mode
          CCM data structure
          EasyDMA and ERROR event
          Registers
            TASKS_KSGEN
            TASKS_CRYPT
            TASKS_STOP
            TASKS_RATEOVERRIDE
            SUBSCRIBE_KSGEN
            SUBSCRIBE_CRYPT
            SUBSCRIBE_STOP
            SUBSCRIBE_RATEOVERRIDE
            EVENTS_ENDKSGEN
            EVENTS_ENDCRYPT
            EVENTS_ERROR ( Deprecated )
            PUBLISH_ENDKSGEN
            PUBLISH_ENDCRYPT
            PUBLISH_ERROR ( Deprecated )
            SHORTS
            INTENSET
            INTENCLR
            MICSTATUS
            ENABLE
            MODE
            CNFPTR
            INPTR
            OUTPTR
            SCRATCHPTR
            MAXPACKETSIZE
            RATEOVERRIDE
            HEADERMASK
          Electrical specification
            Timing specification
        COMP — Comparator
          Shared resources
          Differential mode
          Single-ended mode
          Registers
            TASKS_START
            TASKS_STOP
            TASKS_SAMPLE
            SUBSCRIBE_START
            SUBSCRIBE_STOP
            SUBSCRIBE_SAMPLE
            EVENTS_READY
            EVENTS_DOWN
            EVENTS_UP
            EVENTS_CROSS
            PUBLISH_READY
            PUBLISH_DOWN
            PUBLISH_UP
            PUBLISH_CROSS
            SHORTS
            INTEN
            INTENSET
            INTENCLR
            RESULT
            ENABLE
            PSEL
            REFSEL
            EXTREFSEL
            TH
            MODE
            HYST
            ISOURCE
          Electrical specification
            COMP Electrical Specification
        CRYPTOCELL — ARM TrustZone CryptoCell 312
          Usage
          Direct memory access (DMA)
          Standards
          Registers
            ENABLE
        DCNF — Domain configuration
          Protection
          Registers
            CPUID
            EXTPERI[n].PROTECT
            EXTRAM[n].PROTECT
            EXTCODE[n].PROTECT
        DPPI - Distributed programmable peripheral interconnect
          Subscribing to and publishing on channels
          DPPI configuration (DPPIC)
          Connection examples
          Special considerations for a system implementing TrustZone for Cortex-M processors
          Registers
            TASKS_CHG[n].EN
            TASKS_CHG[n].DIS
            SUBSCRIBE_CHG[n].EN
            SUBSCRIBE_CHG[n].DIS
            CHEN
            CHENSET
            CHENCLR
            CHG[n]
        ECB — AES electronic codebook mode encryption
          Shared resources
          EasyDMA
          ECB data structure
          Registers
            TASKS_STARTECB
            TASKS_STOPECB
            SUBSCRIBE_STARTECB
            SUBSCRIBE_STOPECB
            EVENTS_ENDECB
            EVENTS_ERRORECB
            PUBLISH_ENDECB
            PUBLISH_ERRORECB
            INTENSET
            INTENCLR
            ECBDATAPTR
          Electrical specification
            ECB Electrical Specification
        EGU — Event generator unit
          Registers
            TASKS_TRIGGER[n]
            SUBSCRIBE_TRIGGER[n]
            EVENTS_TRIGGERED[n]
            PUBLISH_TRIGGERED[n]
            INTEN
            INTENSET
            INTENCLR
          Electrical specification
            EGU Electrical Specification
        FPU - Floating point unit (FPU) exceptions
          Registers
            EVENTS_INVALIDOPERATION
            EVENTS_DIVIDEBYZERO
            EVENTS_OVERFLOW
            EVENTS_UNDERFLOW
            EVENTS_INEXACT
            EVENTS_DENORMALINPUT
            INTEN
            INTENSET
            INTENCLR
        GPIO — General purpose input/output
          Assigning pins to MCUs and Subsystems
          Pin configuration
          Pin sense mechanism
          GPIO security
          Registers
            OUT ( Retained )
            OUTSET
            OUTCLR
            IN
            DIR ( Retained )
            DIRSET
            DIRCLR
            LATCH ( Retained )
            DETECTMODE ( Retained )
            DETECTMODE_SEC ( Retained )
            PIN_CNF[n]
          Electrical specification
            GPIO Electrical Specification
        GPIOTE — GPIO tasks and events
          Pin events and tasks
          Port event
          Tasks and events pin configuration
          Registers
            TASKS_OUT[n]
            TASKS_SET[n]
            TASKS_CLR[n]
            SUBSCRIBE_OUT[n]
            SUBSCRIBE_SET[n]
            SUBSCRIBE_CLR[n]
            EVENTS_IN[n]
            EVENTS_PORT
            PUBLISH_IN[n]
            PUBLISH_PORT
            INTENSET
            INTENCLR
            CONFIG[n]
          Electrical specification
        I2S — Inter-IC sound interface
          Mode
          Transmitting and receiving
          Left right clock (LRCK)
          Serial clock (SCK)
          Master clock (MCK)
            Clock source selection
            Configuration examples
          Width, alignment and format
          EasyDMA
          Module operation
          Pin configuration
          Registers
            TASKS_START
            TASKS_STOP
            SUBSCRIBE_START
            SUBSCRIBE_STOP
            EVENTS_RXPTRUPD
            EVENTS_STOPPED
            EVENTS_TXPTRUPD
            EVENTS_FRAMESTART
            PUBLISH_RXPTRUPD
            PUBLISH_STOPPED
            PUBLISH_TXPTRUPD
            PUBLISH_FRAMESTART
            INTEN
            INTENSET
            INTENCLR
            ENABLE
            CONFIG.MODE
            CONFIG.RXEN
            CONFIG.TXEN
            CONFIG.MCKEN
            CONFIG.MCKFREQ
            CONFIG.RATIO
            CONFIG.SWIDTH
            CONFIG.ALIGN
            CONFIG.FORMAT
            CONFIG.CHANNELS
            CONFIG.CLKCONFIG
            RXD.PTR
            TXD.PTR
            RXTXD.MAXCNT
            PSEL.MCK
            PSEL.SCK
            PSEL.LRCK
            PSEL.SDIN
            PSEL.SDOUT
          Electrical specification
            I2S timing specification
        IPC — Interprocessor communication
          IPC and PPI connections
          Registers
            TASKS_SEND[n]
            SUBSCRIBE_SEND[n]
            EVENTS_RECEIVE[n]
            PUBLISH_RECEIVE[n]
            INTEN
            INTENSET
            INTENCLR
            INTPEND
            SEND_CNF[n]
            RECEIVE_CNF[n]
            GPMEM[n]
          Electrical specification
            IPC Electrical Specification
        KMU — Key management unit
          Functional view
          Access control
          Protecting the UICR content
          Usage
            OTP
            Key storage
              Selecting a key slot
              Writing to a key slot
              Reading a key value
              Push over secure APB
              Revoking the key slots
            STATUS register
          Registers
            TASKS_PUSH_KEYSLOT
            EVENTS_KEYSLOT_PUSHED
            EVENTS_KEYSLOT_REVOKED
            EVENTS_KEYSLOT_ERROR
            INTEN
            INTENSET
            INTENCLR
            INTPEND
            STATUS
            SELECTKEYSLOT
        LPCOMP — Low-power comparator
          Shared resources
          Pin configuration
          Registers
            TASKS_START
            TASKS_STOP
            TASKS_SAMPLE
            SUBSCRIBE_START
            SUBSCRIBE_STOP
            SUBSCRIBE_SAMPLE
            EVENTS_READY
            EVENTS_DOWN
            EVENTS_UP
            EVENTS_CROSS
            PUBLISH_READY
            PUBLISH_DOWN
            PUBLISH_UP
            PUBLISH_CROSS
            SHORTS
            INTENSET
            INTENCLR
            RESULT
            ENABLE
            PSEL
            REFSEL
            EXTREFSEL
            ANADETECT
            HYST
          Electrical specification
            LPCOMP Electrical Specification
        MUTEX — Mutual exclusive peripheral
          Registers
            MUTEX[n]
        NFCT — Near field communication tag
          Overview
          Operating states
          Pin configuration
          EasyDMA
          Frame assembler
          Frame disassembler
          Frame timing controller
          Collision resolution
          Antenna interface
          NFCT antenna recommendations
          Battery protection
           References
          Registers
            TASKS_ACTIVATE
            TASKS_DISABLE
            TASKS_SENSE
            TASKS_STARTTX
            TASKS_ENABLERXDATA
            TASKS_GOIDLE
            TASKS_GOSLEEP
            SUBSCRIBE_ACTIVATE
            SUBSCRIBE_DISABLE
            SUBSCRIBE_SENSE
            SUBSCRIBE_STARTTX
            SUBSCRIBE_ENABLERXDATA
            SUBSCRIBE_GOIDLE
            SUBSCRIBE_GOSLEEP
            EVENTS_READY
            EVENTS_FIELDDETECTED
            EVENTS_FIELDLOST
            EVENTS_TXFRAMESTART
            EVENTS_TXFRAMEEND
            EVENTS_RXFRAMESTART
            EVENTS_RXFRAMEEND
            EVENTS_ERROR
            EVENTS_RXERROR
            EVENTS_ENDRX
            EVENTS_ENDTX
            EVENTS_AUTOCOLRESSTARTED
            EVENTS_COLLISION
            EVENTS_SELECTED
            EVENTS_STARTED
            PUBLISH_READY
            PUBLISH_FIELDDETECTED
            PUBLISH_FIELDLOST
            PUBLISH_TXFRAMESTART
            PUBLISH_TXFRAMEEND
            PUBLISH_RXFRAMESTART
            PUBLISH_RXFRAMEEND
            PUBLISH_ERROR
            PUBLISH_RXERROR
            PUBLISH_ENDRX
            PUBLISH_ENDTX
            PUBLISH_AUTOCOLRESSTARTED
            PUBLISH_COLLISION
            PUBLISH_SELECTED
            PUBLISH_STARTED
            SHORTS
            INTEN
            INTENSET
            INTENCLR
            ERRORSTATUS
            FRAMESTATUS.RX
            NFCTAGSTATE
            SLEEPSTATE
            FIELDPRESENT
            FRAMEDELAYMIN
            FRAMEDELAYMAX
            FRAMEDELAYMODE
            PACKETPTR
            MAXLEN
            TXD.FRAMECONFIG
            TXD.AMOUNT
            RXD.FRAMECONFIG
            RXD.AMOUNT
            MODULATIONCTRL
            MODULATIONPSEL
            NFCID1_LAST
            NFCID1_2ND_LAST
            NFCID1_3RD_LAST
            AUTOCOLRESCONFIG
            SENSRES
            SELRES
          Electrical specification
            NFCT Electrical Specification
            NFCT Timing Parameters
        NVMC — Non-volatile memory controller
          Writing to flash
          Erasing a secure page in flash
          Erasing a non-secure page in flash
          Writing to user information configuration registers (UICR)
          Erase all
          NVMC protection mechanisms
            NVMC blocking
            NVMC power failure protection
          Cache
          Registers
            READY
            READYNEXT
            CONFIG
            ERASEALL
            ERASEPAGEPARTIALCFG
            ICACHECNF
            IHIT
            IMISS
            CONFIGNS
            WRITEUICRNS
          Electrical specification
            Flash programming
            Cache size
        PDM — Pulse density modulation interface
          Master clock source selection
          Master clock generator
          Module operation
          Decimation filter
          EasyDMA
          Hardware example
          Pin configuration
          Registers
            TASKS_START
            TASKS_STOP
            SUBSCRIBE_START
            SUBSCRIBE_STOP
            EVENTS_STARTED
            EVENTS_STOPPED
            EVENTS_END
            PUBLISH_STARTED
            PUBLISH_STOPPED
            PUBLISH_END
            INTEN
            INTENSET
            INTENCLR
            ENABLE
            PDMCLKCTRL
            MODE
            GAINL
            GAINR
            RATIO
            PSEL.CLK
            PSEL.DIN
            MCLKCONFIG
            SAMPLE.PTR
            SAMPLE.MAXCNT
          Electrical specification
            PDM Electrical Specification
        PWM — Pulse width modulation
          Wave counter
          Decoder with EasyDMA
          Limitations
          Pin configuration
          Registers
            TASKS_STOP
            TASKS_SEQSTART[n]
            TASKS_NEXTSTEP
            SUBSCRIBE_STOP
            SUBSCRIBE_SEQSTART[n]
            SUBSCRIBE_NEXTSTEP
            EVENTS_STOPPED
            EVENTS_SEQSTARTED[n]
            EVENTS_SEQEND[n]
            EVENTS_PWMPERIODEND
            EVENTS_LOOPSDONE
            PUBLISH_STOPPED
            PUBLISH_SEQSTARTED[n]
            PUBLISH_SEQEND[n]
            PUBLISH_PWMPERIODEND
            PUBLISH_LOOPSDONE
            SHORTS
            INTEN
            INTENSET
            INTENCLR
            ENABLE
            MODE
            COUNTERTOP
            PRESCALER
            DECODER
            LOOP
            SEQ[n].PTR
            SEQ[n].CNT
            SEQ[n].REFRESH
            SEQ[n].ENDDELAY
            PSEL.OUT[n]
        QDEC — Quadrature decoder
          Sampling and decoding
          LED output
          Debounce filters
          Accumulators
          Output/input pins
          Pin configuration
          Registers
            TASKS_START
            TASKS_STOP
            TASKS_READCLRACC
            TASKS_RDCLRACC
            TASKS_RDCLRDBL
            SUBSCRIBE_START
            SUBSCRIBE_STOP
            SUBSCRIBE_READCLRACC
            SUBSCRIBE_RDCLRACC
            SUBSCRIBE_RDCLRDBL
            EVENTS_SAMPLERDY
            EVENTS_REPORTRDY
            EVENTS_ACCOF
            EVENTS_DBLRDY
            EVENTS_STOPPED
            PUBLISH_SAMPLERDY
            PUBLISH_REPORTRDY
            PUBLISH_ACCOF
            PUBLISH_DBLRDY
            PUBLISH_STOPPED
            SHORTS
            INTENSET
            INTENCLR
            ENABLE
            LEDPOL
            SAMPLEPER
            SAMPLE
            REPORTPER
            ACC
            ACCREAD
            PSEL.LED
            PSEL.A
            PSEL.B
            DBFEN
            LEDPRE
            ACCDBL
            ACCDBLREAD
          Electrical specification
            QDEC Electrical Specification
        QSPI — Quad serial peripheral interface
          Configuring peripheral
          Write operation
          Read operation
          Erase operation
          Execute in place
          Encryption
          Sending custom instructions
            Long frame mode
          Deep power-down mode
          Instruction set
          Interface description
          Registers
            TASKS_ACTIVATE
            TASKS_READSTART
            TASKS_WRITESTART
            TASKS_ERASESTART
            TASKS_DEACTIVATE
            SUBSCRIBE_ACTIVATE
            SUBSCRIBE_READSTART
            SUBSCRIBE_WRITESTART
            SUBSCRIBE_ERASESTART
            SUBSCRIBE_DEACTIVATE
            EVENTS_READY
            PUBLISH_READY
            INTEN
            INTENSET
            INTENCLR
            ENABLE
            READ.SRC
            READ.DST
            READ.CNT
            WRITE.DST
            WRITE.SRC
            WRITE.CNT
            ERASE.PTR
            ERASE.LEN
            PSEL.SCK
            PSEL.CSN
            PSEL.IO0
            PSEL.IO1
            PSEL.IO2
            PSEL.IO3
            XIPOFFSET
            IFCONFIG0
            XIPEN
            XIP_ENC.KEY0
            XIP_ENC.KEY1
            XIP_ENC.KEY2
            XIP_ENC.KEY3
            XIP_ENC.NONCE0
            XIP_ENC.NONCE1
            XIP_ENC.NONCE2
            XIP_ENC.ENABLE
            DMA_ENC.KEY0
            DMA_ENC.KEY1
            DMA_ENC.KEY2
            DMA_ENC.KEY3
            DMA_ENC.NONCE0
            DMA_ENC.NONCE1
            DMA_ENC.NONCE2
            DMA_ENC.ENABLE
            IFCONFIG1
            STATUS
            DPMDUR
            ADDRCONF
            CINSTRCONF
            CINSTRDAT0
            CINSTRDAT1
            IFTIMING
          Electrical specification
            Timing specification
        RADIO — 2.4 GHz radio
          Packet configuration
          Address configuration
          Data whitening
          CRC
          Radio states
          Transmit sequence
          Receive sequence
          Received signal strength indicator (RSSI)
          Interframe spacing (IFS)
          Device address match
          Bit counter
          Direction finding
            CTE format
            Mode
            Inline configuration
            Manual configuration
            Receive- and transmit sequences
            Antenna switching
            IQ sampling
          IEEE 802.15.4 operation
            Packet structure
            Operating frequencies
            Energy detection (ED)
            Clear channel assessment (CCA)
            Cyclic redundancy check (CRC)
            Transmit sequence
            Receive sequence
            Interframe spacing (IFS)
          EasyDMA
          Registers
            TASKS_TXEN
            TASKS_RXEN
            TASKS_START
            TASKS_STOP
            TASKS_DISABLE
            TASKS_RSSISTART
            TASKS_RSSISTOP
            TASKS_BCSTART
            TASKS_BCSTOP
            TASKS_EDSTART
            TASKS_EDSTOP
            TASKS_CCASTART
            TASKS_CCASTOP
            SUBSCRIBE_TXEN
            SUBSCRIBE_RXEN
            SUBSCRIBE_START
            SUBSCRIBE_STOP
            SUBSCRIBE_DISABLE
            SUBSCRIBE_RSSISTART
            SUBSCRIBE_RSSISTOP
            SUBSCRIBE_BCSTART
            SUBSCRIBE_BCSTOP
            SUBSCRIBE_EDSTART
            SUBSCRIBE_EDSTOP
            SUBSCRIBE_CCASTART
            SUBSCRIBE_CCASTOP
            EVENTS_READY
            EVENTS_ADDRESS
            EVENTS_PAYLOAD
            EVENTS_END
            EVENTS_DISABLED
            EVENTS_DEVMATCH
            EVENTS_DEVMISS
            EVENTS_RSSIEND
            EVENTS_BCMATCH
            EVENTS_CRCOK
            EVENTS_CRCERROR
            EVENTS_FRAMESTART
            EVENTS_EDEND
            EVENTS_EDSTOPPED
            EVENTS_CCAIDLE
            EVENTS_CCABUSY
            EVENTS_CCASTOPPED
            EVENTS_RATEBOOST
            EVENTS_TXREADY
            EVENTS_RXREADY
            EVENTS_MHRMATCH
            EVENTS_PHYEND
            EVENTS_CTEPRESENT
            PUBLISH_READY
            PUBLISH_ADDRESS
            PUBLISH_PAYLOAD
            PUBLISH_END
            PUBLISH_DISABLED
            PUBLISH_DEVMATCH
            PUBLISH_DEVMISS
            PUBLISH_RSSIEND
            PUBLISH_BCMATCH
            PUBLISH_CRCOK
            PUBLISH_CRCERROR
            PUBLISH_FRAMESTART
            PUBLISH_EDEND
            PUBLISH_EDSTOPPED
            PUBLISH_CCAIDLE
            PUBLISH_CCABUSY
            PUBLISH_CCASTOPPED
            PUBLISH_RATEBOOST
            PUBLISH_TXREADY
            PUBLISH_RXREADY
            PUBLISH_MHRMATCH
            PUBLISH_PHYEND
            PUBLISH_CTEPRESENT
            SHORTS
            INTENSET
            INTENCLR
            CRCSTATUS
            RXMATCH
            RXCRC
            DAI
            PDUSTAT
            CTESTATUS
            DFESTATUS
            PACKETPTR
            FREQUENCY
            TXPOWER
            MODE
            PCNF0
            PCNF1
            BASE0
            BASE1
            PREFIX0
            PREFIX1
            TXADDRESS
            RXADDRESSES
            CRCCNF
            CRCPOLY
            CRCINIT
            TIFS
            RSSISAMPLE
            STATE
            DATAWHITEIV
            BCC
            DAB[n]
            DAP[n]
            DACNF
            MHRMATCHCONF
            MHRMATCHMAS
            MODECNF0
            SFD
            EDCNT
            EDSAMPLE
            CCACTRL
            DFEMODE
            CTEINLINECONF
            DFECTRL1
            DFECTRL2
            SWITCHPATTERN
            CLEARPATTERN
            PSEL.DFEGPIO[n]
            DFEPACKET.PTR
            DFEPACKET.MAXCNT
            DFEPACKET.AMOUNT
            POWER
          Electrical specification
            General radio characteristics
            Radio current consumption (transmitter)
            Radio current consumption (Receiver)
            Transmitter specification
            Receiver operation
            RX selectivity
            RX intermodulation
            Radio timing
            Received signal strength indicator (RSSI) specifications
            Jitter
            IEEE 802.15.4 energy detection constants
        RNG — Random number generator
          Bias correction
          Speed
          Registers
            TASKS_START
            TASKS_STOP
            SUBSCRIBE_START
            SUBSCRIBE_STOP
            EVENTS_VALRDY
            PUBLISH_VALRDY
            SHORTS
            INTENSET
            INTENCLR
            CONFIG
            VALUE
          Electrical specification
            RNG Electrical Specification
        RTC — Real-time counter
          Clock source
          Resolution versus overflow and the prescaler
          Counter register
            Reading the counter register
          Overflow
          Tick event
          Event control
          Capture
          Compare
          Task and event jitter/delay
          Registers
            TASKS_START
            TASKS_STOP
            TASKS_CLEAR
            TASKS_TRIGOVRFLW
            TASKS_CAPTURE[n]
            SUBSCRIBE_START
            SUBSCRIBE_STOP
            SUBSCRIBE_CLEAR
            SUBSCRIBE_TRIGOVRFLW
            SUBSCRIBE_CAPTURE[n]
            EVENTS_TICK
            EVENTS_OVRFLW
            EVENTS_COMPARE[n]
            PUBLISH_TICK
            PUBLISH_OVRFLW
            PUBLISH_COMPARE[n]
            SHORTS
            INTENSET
            INTENCLR
            EVTEN
            EVTENSET
            EVTENCLR
            COUNTER
            PRESCALER
            CC[n]
          Electrical specification
        SAADC — Successive approximation analog-to-digital converter
          Shared resources
          Overview
          Digital output
          Analog inputs and channels
          Operation modes
            One-shot mode
            Continuous mode
            Oversampling
            Scan mode
          EasyDMA
          Resistor ladder
          Reference
          Acquisition time
          Limits event monitoring
          Registers
            TASKS_START
            TASKS_SAMPLE
            TASKS_STOP
            TASKS_CALIBRATEOFFSET
            SUBSCRIBE_START
            SUBSCRIBE_SAMPLE
            SUBSCRIBE_STOP
            SUBSCRIBE_CALIBRATEOFFSET
            EVENTS_STARTED
            EVENTS_END
            EVENTS_DONE
            EVENTS_RESULTDONE
            EVENTS_CALIBRATEDONE
            EVENTS_STOPPED
            EVENTS_CH[n].LIMITH
            EVENTS_CH[n].LIMITL
            PUBLISH_STARTED
            PUBLISH_END
            PUBLISH_DONE
            PUBLISH_RESULTDONE
            PUBLISH_CALIBRATEDONE
            PUBLISH_STOPPED
            PUBLISH_CH[n].LIMITH
            PUBLISH_CH[n].LIMITL
            INTEN
            INTENSET
            INTENCLR
            STATUS
            ENABLE
            CH[n].PSELP
            CH[n].PSELN
            CH[n].CONFIG
            CH[n].LIMIT
            RESOLUTION
            OVERSAMPLE
            SAMPLERATE
            RESULT.PTR
            RESULT.MAXCNT
            RESULT.AMOUNT
          Electrical specification
            SAADC Electrical Specification
          Performance factors
        SPIM — Serial peripheral interface master with EasyDMA
          SPI master transaction sequence
          D/CX functionality
          Pin configuration
          Shared resources
          EasyDMA
          Low power
          Registers
            TASKS_START
            TASKS_STOP
            TASKS_SUSPEND
            TASKS_RESUME
            SUBSCRIBE_START
            SUBSCRIBE_STOP
            SUBSCRIBE_SUSPEND
            SUBSCRIBE_RESUME
            EVENTS_STOPPED
            EVENTS_ENDRX
            EVENTS_END
            EVENTS_ENDTX
            EVENTS_STARTED
            PUBLISH_STOPPED
            PUBLISH_ENDRX
            PUBLISH_END
            PUBLISH_ENDTX
            PUBLISH_STARTED
            SHORTS
            INTENSET
            INTENCLR
            STALLSTAT
            ENABLE
            PSEL.SCK
            PSEL.MOSI
            PSEL.MISO
            PSEL.CSN
            FREQUENCY
            RXD.PTR
            RXD.MAXCNT
            RXD.AMOUNT
            RXD.LIST
            TXD.PTR
            TXD.MAXCNT
            TXD.AMOUNT
            TXD.LIST
            CONFIG
            IFTIMING.RXDELAY
            IFTIMING.CSNDUR
            CSNPOL
            PSELDCX
            DCXCNT
            ORC
          Electrical specification
            Timing specifications
        SPIS — Serial peripheral interface slave with EasyDMA
          Shared resources
          EasyDMA
          SPI slave operation
          Pin configuration
          Registers
            TASKS_ACQUIRE
            TASKS_RELEASE
            SUBSCRIBE_ACQUIRE
            SUBSCRIBE_RELEASE
            EVENTS_END
            EVENTS_ENDRX
            EVENTS_ACQUIRED
            PUBLISH_END
            PUBLISH_ENDRX
            PUBLISH_ACQUIRED
            SHORTS
            INTENSET
            INTENCLR
            SEMSTAT
            STATUS
            ENABLE
            PSEL.SCK
            PSEL.MISO
            PSEL.MOSI
            PSEL.CSN
            PSELSCK ( Deprecated )
            PSELMISO ( Deprecated )
            PSELMOSI ( Deprecated )
            PSELCSN ( Deprecated )
            RXDPTR ( Deprecated )
            MAXRX ( Deprecated )
            AMOUNTRX ( Deprecated )
            RXD.PTR
            RXD.MAXCNT
            RXD.AMOUNT
            RXD.LIST
            TXDPTR ( Deprecated )
            MAXTX ( Deprecated )
            AMOUNTTX ( Deprecated )
            TXD.PTR
            TXD.MAXCNT
            TXD.AMOUNT
            TXD.LIST
            CONFIG
            DEF
            ORC
          Electrical specification
            SPIS slave interface electrical specifications
            Serial Peripheral Interface Slave (SPIS) timing specifications
        SPU — System protection unit
          General concepts
            Special considerations for ARM TrustZone for Cortex-M enabled system
          Flash access control
            Non-secure callable (NSC) region definition in flash
            Flash access error reporting
            UICR and FICR protections
          RAM access control
            Non-secure callable (NSC) region definition in RAM
            RAM access error reporting
          Peripheral access control
            Peripherals with split security
            Peripheral address mapping
            Special considerations for peripherals with DMA master
            Peripheral access error reporting
          Pin access control
          DPPI access control
            Special considerations regarding the DPPIC configuration registers
          External domain access control
          TrustZone for Cortex-M ID allocation
          Registers
            EVENTS_RAMACCERR
            EVENTS_FLASHACCERR
            EVENTS_PERIPHACCERR
            PUBLISH_RAMACCERR
            PUBLISH_FLASHACCERR
            PUBLISH_PERIPHACCERR
            INTEN
            INTENSET
            INTENCLR
            CAP
            CPULOCK
            EXTDOMAIN[n].PERM
            DPPI[n].PERM
            DPPI[n].LOCK
            GPIOPORT[n].PERM
            GPIOPORT[n].LOCK
            FLASHNSC[n].REGION
            FLASHNSC[n].SIZE
            RAMNSC[n].REGION
            RAMNSC[n].SIZE
            FLASHREGION[n].PERM
            RAMREGION[n].PERM
            PERIPHID[n].PERM
        SWI — Software interrupts
          Registers
        TEMP — Temperature sensor
          Registers
            TASKS_START
            TASKS_STOP
            SUBSCRIBE_START
            SUBSCRIBE_STOP
            EVENTS_DATARDY
            PUBLISH_DATARDY
            INTENSET
            INTENCLR
            TEMP
            A0
            A1
            A2
            A3
            A4
            A5
            B0
            B1
            B2
            B3
            B4
            B5
            T0
            T1
            T2
            T3
            T4
          Electrical specification
            Temperature Sensor Electrical Specification
        TIMER — Timer/counter
          Capture
          Compare
          Task delays
          Task priority
          Registers
            TASKS_START
            TASKS_STOP
            TASKS_COUNT
            TASKS_CLEAR
            TASKS_SHUTDOWN ( Deprecated )
            TASKS_CAPTURE[n]
            SUBSCRIBE_START
            SUBSCRIBE_STOP
            SUBSCRIBE_COUNT
            SUBSCRIBE_CLEAR
            SUBSCRIBE_SHUTDOWN ( Deprecated )
            SUBSCRIBE_CAPTURE[n]
            EVENTS_COMPARE[n]
            PUBLISH_COMPARE[n]
            SHORTS
            INTEN
            INTENSET
            INTENCLR
            MODE
            BITMODE
            PRESCALER
            CC[n]
            ONESHOTEN[n]
          Electrical specification
        TWIM — I2C compatible two-wire interface master with EasyDMA
          Shared resources
          EasyDMA
          Master write sequence
          Master read sequence
          Master repeated start sequence
          Low power
          Master mode pin configuration
          Registers
            TASKS_STARTRX
            TASKS_STARTTX
            TASKS_STOP
            TASKS_SUSPEND
            TASKS_RESUME
            SUBSCRIBE_STARTRX
            SUBSCRIBE_STARTTX
            SUBSCRIBE_STOP
            SUBSCRIBE_SUSPEND
            SUBSCRIBE_RESUME
            EVENTS_STOPPED
            EVENTS_ERROR
            EVENTS_SUSPENDED
            EVENTS_RXSTARTED
            EVENTS_TXSTARTED
            EVENTS_LASTRX
            EVENTS_LASTTX
            PUBLISH_STOPPED
            PUBLISH_ERROR
            PUBLISH_SUSPENDED
            PUBLISH_RXSTARTED
            PUBLISH_TXSTARTED
            PUBLISH_LASTRX
            PUBLISH_LASTTX
            SHORTS
            INTEN
            INTENSET
            INTENCLR
            ERRORSRC
            ENABLE
            PSEL.SCL
            PSEL.SDA
            FREQUENCY
            RXD.PTR
            RXD.MAXCNT
            RXD.AMOUNT
            RXD.LIST
            TXD.PTR
            TXD.MAXCNT
            TXD.AMOUNT
            TXD.LIST
            ADDRESS
          Electrical specification
            TWIM interface electrical specifications
            Two Wire Interface Master (TWIM) timing specifications
          Pullup resistor
        TWIS — I2C compatible two-wire interface slave with EasyDMA
          Shared resources
          EasyDMA
          TWI slave responding to a read command
          TWI slave responding to a write command
          Master repeated start sequence
          Terminating an ongoing TWI transaction
          Low power
          Slave mode pin configuration
          Registers
            TASKS_STOP
            TASKS_SUSPEND
            TASKS_RESUME
            TASKS_PREPARERX
            TASKS_PREPARETX
            SUBSCRIBE_STOP
            SUBSCRIBE_SUSPEND
            SUBSCRIBE_RESUME
            SUBSCRIBE_PREPARERX
            SUBSCRIBE_PREPARETX
            EVENTS_STOPPED
            EVENTS_ERROR
            EVENTS_RXSTARTED
            EVENTS_TXSTARTED
            EVENTS_WRITE
            EVENTS_READ
            PUBLISH_STOPPED
            PUBLISH_ERROR
            PUBLISH_RXSTARTED
            PUBLISH_TXSTARTED
            PUBLISH_WRITE
            PUBLISH_READ
            SHORTS
            INTEN
            INTENSET
            INTENCLR
            ERRORSRC
            MATCH
            ENABLE
            PSEL.SCL
            PSEL.SDA
            RXD.PTR
            RXD.MAXCNT
            RXD.AMOUNT
            RXD.LIST
            TXD.PTR
            TXD.MAXCNT
            TXD.AMOUNT
            TXD.LIST
            ADDRESS[n]
            CONFIG
            ORC
          Electrical specification
            TWIS slave timing specifications
        UARTE — Universal asynchronous receiver/transmitter with EasyDMA
          EasyDMA
          Transmission
          Reception
          Error conditions
          Using the UARTE without flow control
          Parity and stop bit configuration
          Low power
          Pin configuration
          Registers
            TASKS_STARTRX
            TASKS_STOPRX
            TASKS_STARTTX
            TASKS_STOPTX
            TASKS_FLUSHRX
            SUBSCRIBE_STARTRX
            SUBSCRIBE_STOPRX
            SUBSCRIBE_STARTTX
            SUBSCRIBE_STOPTX
            SUBSCRIBE_FLUSHRX
            EVENTS_CTS
            EVENTS_NCTS
            EVENTS_RXDRDY
            EVENTS_ENDRX
            EVENTS_TXDRDY
            EVENTS_ENDTX
            EVENTS_ERROR
            EVENTS_RXTO
            EVENTS_RXSTARTED
            EVENTS_TXSTARTED
            EVENTS_TXSTOPPED
            PUBLISH_CTS
            PUBLISH_NCTS
            PUBLISH_RXDRDY
            PUBLISH_ENDRX
            PUBLISH_TXDRDY
            PUBLISH_ENDTX
            PUBLISH_ERROR
            PUBLISH_RXTO
            PUBLISH_RXSTARTED
            PUBLISH_TXSTARTED
            PUBLISH_TXSTOPPED
            SHORTS
            INTEN
            INTENSET
            INTENCLR
            ERRORSRC
            ENABLE
            PSEL.RTS
            PSEL.TXD
            PSEL.CTS
            PSEL.RXD
            BAUDRATE
            RXD.PTR
            RXD.MAXCNT
            RXD.AMOUNT
            TXD.PTR
            TXD.MAXCNT
            TXD.AMOUNT
            CONFIG
          Electrical specification
            UARTE electrical specification
        USBD — Universal serial bus device
          USB device states
          USB terminology
          USB pins
          USBD power-up sequence
          USB pull-up
          USB reset
          USB suspend and resume
            Entering suspend
            Host-initiated resume
            Device-initiated remote wake-up
          EasyDMA
          Control transfers
            Control read transfer
            Control write transfer
          Bulk and interrupt transactions
            Bulk and interrupt IN transaction
            Bulk and interrupt OUT transaction
          Isochronous transactions
            Isochronous IN transaction
            Isochronous OUT transaction
          USB register access limitations
          Registers
            TASKS_STARTEPIN[n]
            TASKS_STARTISOIN
            TASKS_STARTEPOUT[n]
            TASKS_STARTISOOUT
            TASKS_EP0RCVOUT
            TASKS_EP0STATUS
            TASKS_EP0STALL
            TASKS_DPDMDRIVE
            TASKS_DPDMNODRIVE
            SUBSCRIBE_STARTEPIN[n]
            SUBSCRIBE_STARTISOIN
            SUBSCRIBE_STARTEPOUT[n]
            SUBSCRIBE_STARTISOOUT
            SUBSCRIBE_EP0RCVOUT
            SUBSCRIBE_EP0STATUS
            SUBSCRIBE_EP0STALL
            SUBSCRIBE_DPDMDRIVE
            SUBSCRIBE_DPDMNODRIVE
            EVENTS_USBRESET
            EVENTS_STARTED
            EVENTS_ENDEPIN[n]
            EVENTS_EP0DATADONE
            EVENTS_ENDISOIN
            EVENTS_ENDEPOUT[n]
            EVENTS_ENDISOOUT
            EVENTS_SOF
            EVENTS_USBEVENT
            EVENTS_EP0SETUP
            EVENTS_EPDATA
            PUBLISH_USBRESET
            PUBLISH_STARTED
            PUBLISH_ENDEPIN[n]
            PUBLISH_EP0DATADONE
            PUBLISH_ENDISOIN
            PUBLISH_ENDEPOUT[n]
            PUBLISH_ENDISOOUT
            PUBLISH_SOF
            PUBLISH_USBEVENT
            PUBLISH_EP0SETUP
            PUBLISH_EPDATA
            SHORTS
            INTEN
            INTENSET
            INTENCLR
            EVENTCAUSE
            HALTED.EPIN[n]
            HALTED.EPOUT[n]
            EPSTATUS
            EPDATASTATUS
            USBADDR
            BMREQUESTTYPE
            BREQUEST
            WVALUEL
            WVALUEH
            WINDEXL
            WINDEXH
            WLENGTHL
            WLENGTHH
            SIZE.EPOUT[n]
            SIZE.ISOOUT
            ENABLE
            USBPULLUP
            DPDMVALUE
            DTOGGLE
            EPINEN
            EPOUTEN
            EPSTALL
            ISOSPLIT
            FRAMECNTR
            LOWPOWER
            ISOINCONFIG
            EPIN[n].PTR
            EPIN[n].MAXCNT
            EPIN[n].AMOUNT
            ISOIN.PTR
            ISOIN.MAXCNT
            ISOIN.AMOUNT
            EPOUT[n].PTR
            EPOUT[n].MAXCNT
            EPOUT[n].AMOUNT
            ISOOUT.PTR
            ISOOUT.MAXCNT
            ISOOUT.AMOUNT
          Electrical specification
            USB Electrical Specification
        VMC — Volatile memory controller
          RAM power states
          Registers
            RAM[n].POWER
            RAM[n].POWERSET
            RAM[n].POWERCLR
        WDT — Watchdog timer
          Reload criteria
          Temporarily pausing the watchdog
          Watchdog reset
          Stopping the watchdog
          Registers
            TASKS_START
            TASKS_STOP
            SUBSCRIBE_START
            SUBSCRIBE_STOP
            EVENTS_TIMEOUT
            EVENTS_STOPPED
            PUBLISH_TIMEOUT
            PUBLISH_STOPPED
            INTENSET
            INTENCLR
            NMIENSET
            NMIENCLR
            RUNSTATUS
            REQSTATUS
            CRV
            RREN
            CONFIG
            TSEN
            RR[n]
          Electrical specification
            Watchdog Timer Electrical Specification
      Debug and trace
        Overview
          DAP - Debug access port
          Access port protection
          Debug interface mode
          Real-time debug
          ROM tables
          Cross-trigger network
          Multidrop SWD
          Trace
          Enabling the trace port
          Registers
            TARGETID
            DLPIDR
          Electrical specification
            SW-DP
            Trace port
        CTRL-AP - Control access port
          Reset request
          Erase all
          Mailbox interface
          Disabling erase protection
          Disabling access port protection
          Debugger registers
            Registers
              RESET
              ERASEALL
              ERASEALLSTATUS
              APPROTECT.STATUS
              APPROTECT.DISABLE
              SECUREAPPROTECT.DISABLE
              ERASEPROTECT.STATUS
              ERASEPROTECT.DISABLE
              MAILBOX.TXDATA
              MAILBOX.TXSTATUS
              MAILBOX.RXDATA
              MAILBOX.RXSTATUS
              IDR
          Registers
            MAILBOX.RXDATA
            MAILBOX.RXSTATUS
            MAILBOX.TXDATA
            MAILBOX.TXSTATUS
            ERASEPROTECT.LOCK
            ERASEPROTECT.DISABLE
            APPROTECT.LOCK
            APPROTECT.DISABLE
            SECUREAPPROTECT.LOCK
            SECUREAPPROTECT.DISABLE
            STATUS
        CTI - Cross Trigger Interface
          Registers
            CTICONTROL
            CTIINTACK
            CTIAPPSET
            CTIAPPCLEAR
            CTIAPPPULSE
            CTIINEN[n]
            CTIOUTEN[n]
            CTITRIGINSTATUS
            CTITRIGOUTSTATUS
            CTICHINSTATUS
            CTIGATE
            DEVARCH
            DEVID
            DEVTYPE
            PIDR4
            PIDR5
            PIDR6
            PIDR7
            PIDR0
            PIDR1
            PIDR2
            PIDR3
            CIDR0
            CIDR1
            CIDR2
            CIDR3
        TAD - Trace and debug control
          Registers
            CLOCKSTART
            CLOCKSTOP
            ENABLE
            PSEL.TRACECLK
            PSEL.TRACEDATA0
            PSEL.TRACEDATA1
            PSEL.TRACEDATA2
            PSEL.TRACEDATA3
            TRACEPORTSPEED
      Hardware and layout
        Pin assignments
          aQFN94 pin assignments
        Mechanical specifications
          aQFN94 7 x 7 mm package
        Reference circuitry
          Circuit configuration no. 1
          PCB layout example
      Recommended operating conditions
      Absolute maximum ratings
      Ordering information
        IC marking
        Box labels
        Order code
        Code ranges and values
        Product options
      Legal notices
    Errata
      nRF5340 Engineering A Errata
        Change log
        New and inherited anomalies
          [3] SAADC: VDDHDIV5 is not functional
          [4] CLOCK: Changing application core frequency register HFCLKCTRL requires additional register initialization
          [5] TAD: Trace is not functional when application core is running at 128 MHz
          [6] NVMC: Disabling instruction cache causes skip of next instruction
          [7] USBD: USBD is not functional
          [8] WDT: WDT1 is not functional
          [9] TAD: TPIU is missing from ROM table
          [10] CCM: Reading CNFPTR, INPTR, OUTPTR, and SCRATCHPTR pointers returns incorrect address
          [11] ACL: Reading ACL[n].ADDR returns incorrect address
          [12] QSPI: SCKFREQ is not functional at 96 MHz
          [13] GPIO: Bits in LATCH register are incorrectly set to 1
          [14] TIMER: CC[6] and CC[7] are not functional
          [15] UARTE: Odd parity setting is not functional
          [16] RADIO: POWER register is not functional
          [18] I2S: 32-bit sample widths and 8-bit sample in a 16-bit half-frame are not functional
          [19] SPU: Flash memory space is divided into 32 regions of 32 KiB
          [20] RTC: TASKS_CAPTURE[n], SUBSCRIBE_CAPTURE[n], and SHORTS registers are not functional
          [21] TWIM: 1000 kbps baud rate is not functional
          [22] SPU: CPULOCK register is not functional
          [23] SAADC: Events are not generated when switching from scan mode to no-scan mode with BURST enabled
          [26] CTRL-AP: APPROTECT.DISABLE and SECUREAPPROTECT.DISABLE registers are not functional
          [27] CTRL-AP: STATUS register is not functional
          [28] TIMER: INTEN register is not functional
          [29] SWIRQ: SWIRQ is not functional
          [30] RESET: LCTRLAP field in RESETREAS register is not functional
          [32] GPIO: GPIO pins assigned to network core do not retain their state in System OFF mode
          [33] CLOCK: LFRC frequency starts drifting even if calibration task is triggered
          [37] TWIM: First clock pulse after clock stretching may be too long or too short
          [42] CLOCK: Reset value of HFCLKCTRL is invalid
          [44] UARTE: TASKS_RESUME impacts UARTE
          [45] SPIM: Receive is not functional at 32 Mbps
          [46] CLOCK: LFRC has higher current consumption
          [47] TWIM: I2C timing spec is violated at 400 kHz
          [49] POWER: SLEEPENTER and SLEEPEXIT events are asserted after pin reset
          [50] SPU: Arm TrustZone region numbers for FICR, UICR, CACHEINFO, and CACHEDATA are incorrect
          [51] SPU: Accessing FICR, UICR, CACHEINFO, or CACHEDATA from non-secure state gives bus error
          [53] REGULATORS: Current consumption in normal voltage mode is higher in System ON idle
          [54] REGULATORS: Current consumption in normal voltage mode is higher in System ON idle and System OFF
          [55] RESET: Bits in RESETREAS are set when they should not be
          [57] I2S: EVENTS_FRAMESTART and PUBLISH_FRAMESTART registers are not functional
          [58] I2S: BYPASS in CONFIG.CLKCONFIG is not functional
          [59] QDEC: QDEC is not functional
          [65] SAADC: Events are not generated when switching from scan mode to no-scan mode with BURST disabled
          [69] REGULATORS: VREGMAIN configuration is not retained in System OFF
          [72] REGULATORS: Current consumption in high voltage mode is higher in System ON idle and System OFF
    Compatibility Matrix
      IC revisions and variants
      Documentation and reference design files
      nRF Connect SDK
      Development hardware
      Revision history
    nRF5340 PDK
      Revision history
      Minimum requirements
      Kit content
        Hardware content
        Downloadable content
        Related documentation
      Interface MCU
        IF Boot/Reset button
        Virtual COM port
          Dynamic HWFC handling
        MSD
      Hardware description
        Hardware drawings
        Block diagram
        Power supply
          5 V power sources
          VDD power sources
          Interface MCU power
          nRF5340 power source
          nRF5340 direct supply
        Operating modes
          USB detect
          nRF only mode
          Signal switches
        External memory
        Connector interface
          Mapping of analog pins
        Buttons and LEDs
        32.768 kHz crystal
        Debug input and trace
        Debug output
        NFC antenna interface
        Extra op-amp
        Solder bridge configuration
      Measuring current
        Preparing the PDK board
        Using an oscilloscope for current profile measurement
        Using an ampere-meter for current measurement
      RF measurements
      Glossary
        Clear to Send (CTS)
        Data Terminal Ready (DTR)
        DK (Development Kit)
        Hardware Flow Control (HWFC)
        Integrated Development Environment (IDE)
        Mass Storage Device (MSD)
        Near Field Communication (NFC)
        NFC-A Listen Mode
        Operational Amplifier (op-amp)
        Preview Development Kit (PDK)
        Receive Data (RXD)
        Request to Send (RTS)
        Root Mean Square (RMS)
        SubMiniature Version A (SMA) Connector
        System on Chip (SoC)
        Transmit Data (TXD)
      Acronyms and abbreviations
      Legal notices
  nRF5340
    nRF5340 Objective Product Specification
      Revision history
      About this document
        Document status
        Peripheral chapters
        Register tables
          Fields and values
          Permissions
        Registers
          DUMMY
      Product overview
        Block diagram
        Memory
          RAM - Random access memory
          Flash (non-volatile memory)
          XIP - Execute in place
          Access latency
      Power and clock management
        Overview
          System ON mode
            Power submodes
          System OFF mode
            Emulated System OFF mode
          Core Force-off mode
            Emulated Force-off mode
        Current consumption
          Electrical specification
            Sleep
            Application CPU running
            Network CPU running
            COMP active
            LPCOMP active
            NFCT active
            RADIO transmitting/receiving
            RNG active
            SAADC active
            TEMP active
            TIMER running
            WDT active
            Compounded
            USBD active
        Power supply modes and regulators
          Normal voltage mode
          High voltage mode
          Power supply supervisor
            Power-fail comparator
        POWER — Power control
          Registers
            TASKS_CONSTLAT
            TASKS_LOWPWR
            SUBSCRIBE_CONSTLAT
            SUBSCRIBE_LOWPWR
            EVENTS_POFWARN
            EVENTS_SLEEPENTER
            EVENTS_SLEEPEXIT
            PUBLISH_POFWARN
            PUBLISH_SLEEPENTER
            PUBLISH_SLEEPEXIT
            INTEN
            INTENSET
            INTENCLR
            GPREGRET[n]
        REGULATORS - Regulator control
          Normal voltage mode - detailed setup
          High voltage mode - detailed setup
            External circuitry supply
          GPIO levels
          Registers
            MAINREGSTATUS ( Retained )
            SYSTEMOFF
            POFCON ( Retained )
            VREGMAIN.DCDCEN ( Retained )
            VREGRADIO.DCDCEN ( Retained )
            VREGH.DCDCEN ( Retained )
          Electrical specification
            Regulator startup times
            Application core startup times
            Network core startup times
            Power-fail comparator
            Regulator specifications, VREGH stage
        USBREG - USB regulator control
          Registers
            EVENTS_USBDETECTED
            EVENTS_USBREMOVED
            EVENTS_USBPWRRDY
            PUBLISH_USBDETECTED
            PUBLISH_USBREMOVED
            PUBLISH_USBPWRRDY
            INTEN
            INTENSET
            INTENCLR
            USBREGSTATUS
          Electrical specification
            USB operating conditions
            USB regulator specifications
            VBUS detection specifications
        VREQCTRL - Voltage request control
          Registers
            VREGRADIO.VREQH ( Retained )
            VREGRADIO.VREQHREADY
        RESET - Reset control
          Power-on reset
          Pin reset
          Brownout reset
          Wakeup from System OFF mode reset
          Soft reset
          Watchdog timer reset
          Network force off
          Retained registers
          Application core reset behavior
          Network core reset behavior
          Registers
            RESETREAS
            NETWORK.FORCEOFF
        CLOCK — Clock control
          HFCLK controller
            Application core frequency scaling
            32 MHz crystal oscillator (HFXO)
            Audio oscillator
            Overriding the automatic HFCLK control system
          LFCLK controller
            32.768 kHz RC oscillator (LFRC)
              Calibrating the 32.768 kHz RC oscillator
            32.768 kHz ultra-low power RC oscillator (LFULP)
            32.768 kHz crystal oscillator (LFXO)
            32.768 kHz synthesized from HFCLK (LFSYNT)
            Overriding the automatic LFCLK control system
          Registers
            TASKS_HFCLKSTART
            TASKS_HFCLKSTOP
            TASKS_LFCLKSTART
            TASKS_LFCLKSTOP
            TASKS_CAL
            TASKS_HFCLKAUDIOSTART
            TASKS_HFCLKAUDIOSTOP
            TASKS_HFCLK192MSTART
            TASKS_HFCLK192MSTOP
            SUBSCRIBE_HFCLKSTART
            SUBSCRIBE_HFCLKSTOP
            SUBSCRIBE_LFCLKSTART
            SUBSCRIBE_LFCLKSTOP
            SUBSCRIBE_CAL
            SUBSCRIBE_HFCLKAUDIOSTART
            SUBSCRIBE_HFCLKAUDIOSTOP
            SUBSCRIBE_HFCLK192MSTART
            SUBSCRIBE_HFCLK192MSTOP
            EVENTS_HFCLKSTARTED
            EVENTS_LFCLKSTARTED
            EVENTS_DONE
            EVENTS_HFCLKAUDIOSTARTED
            EVENTS_HFCLK192MSTARTED
            PUBLISH_HFCLKSTARTED
            PUBLISH_LFCLKSTARTED
            PUBLISH_DONE
            PUBLISH_HFCLKAUDIOSTARTED
            PUBLISH_HFCLK192MSTARTED
            INTEN
            INTENSET
            INTENCLR
            INTPEND
            HFCLKRUN
            HFCLKSTAT
            LFCLKRUN
            LFCLKSTAT
            LFCLKSRCCOPY
            HFCLKAUDIORUN
            HFCLKAUDIOSTAT
            HFCLK192MRUN
            HFCLK192MSTAT
            HFCLKSRC
            LFCLKSRC
            HFCLKCTRL
            HFCLKAUDIO.FREQUENCY
            HFCLKALWAYSRUN
            LFCLKALWAYSRUN
            HFCLKAUDIOALWAYSRUN
            HFCLK192MSRC
            HFCLK192MALWAYSRUN
            HFCLK192MCTRL
          Electrical specification
            128 MHz clock source (HFCLK128M)
            64 MHz clock source (HFCLK64M)
            192 MHz clock source (HFCLK192M)
            Audio clock source (HFCLKAUDIO)
            32 MHz crystal oscillator (HFXO)
            32.768 kHz crystal oscillator (LFXO)
            32.768 kHz RC oscillator (LFRC)
            32.768 kHz ultra-low power RC oscillator (LFULP)
            Synthesized 32.768 kHz clock (LFSYNT)
        OSCILLATORS — Oscillator control
          High-frequency (32 MHz) crystal oscillator (HFXO)
            Using internal capacitors
          Low-frequency (32.768 kHz) crystal oscillator (LFXO)
            Using internal capacitors
          Low-frequency (32.768 kHz) external source
          Registers
            XOSC32MCAPS ( Retained )
            XOSC32KI.BYPASS ( Retained )
            XOSC32KI.INTCAP ( Retained )
      Application core
        Application core overview
        CPU
          Floating point interrupt
          Electrical specification
            CPU performance
          CPU and support module configuration
        Memory
          Peripheral instantiation
        Core components
          CACHE — Instruction/data cache
            Cache content
            Profiling
            Registers
              PROFILING[n].IHIT
              PROFILING[n].IMISS
              PROFILING[n].DHIT
              PROFILING[n].DMISS
              ENABLE
              INVALIDATE
              ERASE
              PROFILINGENABLE
              PROFILINGCLEAR
              MODE
              DEBUGLOCK
              ERASESTATUS
              WRITELOCK
            Registers
              SET[n].WAY[o]
            Registers
              SET[n].WAY[o].DATA0
              SET[n].WAY[o].DATA1
              SET[n].WAY[o].DATA2
              SET[n].WAY[o].DATA3
          FICR — Factory information configuration registers
            Registers
              INFO.CONFIGID
              INFO.DEVICEID[n]
              INFO.PART
              INFO.VARIANT
              INFO.PACKAGE
              INFO.RAM
              INFO.FLASH
              INFO.CODEPAGESIZE
              INFO.CODESIZE
              INFO.DEVICETYPE
              TRIMCNF[n].ADDR
              TRIMCNF[n].DATA
              NFC.TAGHEADER0
              NFC.TAGHEADER1
              NFC.TAGHEADER2
              NFC.TAGHEADER3
              TRNG90B.BYTES
              TRNG90B.RCCUTOFF
              TRNG90B.APCUTOFF
              TRNG90B.STARTUP
              TRNG90B.ROSC1
              TRNG90B.ROSC2
              TRNG90B.ROSC3
              TRNG90B.ROSC4
              XOSC32MTRIM
          UICR — User information configuration registers
            Registers
              APPROTECT
              EXTSUPPLY
              VREGHVOUT
              HFXOCNT
              SECUREAPPROTECT
              ERASEPROTECT
              TINSTANCE
              NFCPINS
              OTP[n]
              KEYSLOT.CONFIG[n].DEST
              KEYSLOT.CONFIG[n].PERM
              KEYSLOT.KEY[n].VALUE[o]
          AHB multilayer
            AHB multilayer priorities
      Network core
        Network core overview
        CPU
          Electrical specification
            CPU performance
          CPU and support module configuration
        Memory
          Peripheral instantiation
        Core components
          FICR — Factory information configuration registers
            Registers
              INFO.CONFIGID
              INFO.DEVICEID[n]
              INFO.PART
              INFO.VARIANT
              INFO.PACKAGE
              INFO.RAM
              INFO.FLASH
              INFO.CODEPAGESIZE
              INFO.CODESIZE
              INFO.DEVICETYPE
              ER[n]
              IR[n]
              DEVICEADDRTYPE
              DEVICEADDR[n]
              TRIMCNF[n].ADDR
              TRIMCNF[n].DATA
          UICR — User information configuration registers
            Registers
              APPROTECT
              ERASEPROTECT
              NRFFW[n]
              CUSTOMER[n]
          AHB multilayer
            AHB multilayer priorities
      Peripherals
        Instantiation
        Peripheral interface
          Peripheral ID
          Peripherals with shared ID
          Peripheral registers
          Bit set and clear
          Tasks
          Events
          Publish and subscribe
          Shortcuts
          Interrupts
            Interrupt clearing and disabling
          Secure/non-secure peripherals
        EasyDMA
          EasyDMA error handling
          EasyDMA array list
        ACL — Access control lists
          Registers
            ACL[n].ADDR
            ACL[n].SIZE
            ACL[n].PERM
        AAR — Accelerated address resolver
          Shared resources
          EasyDMA
          Resolving a resolvable address
          Use case example for chaining RADIO packet reception with address resolution using AAR
          IRK data structure
          Registers
            TASKS_START
            TASKS_STOP
            SUBSCRIBE_START
            SUBSCRIBE_STOP
            EVENTS_END
            EVENTS_RESOLVED
            EVENTS_NOTRESOLVED
            PUBLISH_END
            PUBLISH_RESOLVED
            PUBLISH_NOTRESOLVED
            INTENSET
            INTENCLR
            STATUS
            ENABLE
            NIRK
            IRKPTR
            ADDRPTR
            SCRATCHPTR
          Electrical specification
            AAR Electrical Specification
        CCM — AES CCM mode encryption
          Shared resources
          Keystream generation
          Encryption
          Decryption
          AES CCM and radio concurrent operation
          Encrypting packets on-the-fly in radio transmit mode
          Decrypting packets on-the-fly in radio receive mode
          CCM data structure
          EasyDMA and ERROR event
          Registers
            TASKS_KSGEN
            TASKS_CRYPT
            TASKS_STOP
            TASKS_RATEOVERRIDE
            SUBSCRIBE_KSGEN
            SUBSCRIBE_CRYPT
            SUBSCRIBE_STOP
            SUBSCRIBE_RATEOVERRIDE
            EVENTS_ENDKSGEN
            EVENTS_ENDCRYPT
            EVENTS_ERROR ( Deprecated )
            PUBLISH_ENDKSGEN
            PUBLISH_ENDCRYPT
            PUBLISH_ERROR ( Deprecated )
            SHORTS
            INTENSET
            INTENCLR
            MICSTATUS
            ENABLE
            MODE
            CNFPTR
            INPTR
            OUTPTR
            SCRATCHPTR
            MAXPACKETSIZE
            RATEOVERRIDE
            HEADERMASK
          Electrical specification
            Timing specification
        COMP — Comparator
          Shared resources
          Differential mode
          Single-ended mode
          Registers
            TASKS_START
            TASKS_STOP
            TASKS_SAMPLE
            SUBSCRIBE_START
            SUBSCRIBE_STOP
            SUBSCRIBE_SAMPLE
            EVENTS_READY
            EVENTS_DOWN
            EVENTS_UP
            EVENTS_CROSS
            PUBLISH_READY
            PUBLISH_DOWN
            PUBLISH_UP
            PUBLISH_CROSS
            SHORTS
            INTEN
            INTENSET
            INTENCLR
            RESULT
            ENABLE
            PSEL
            REFSEL
            EXTREFSEL
            TH
            MODE
            HYST
            ISOURCE
          Electrical specification
            COMP Electrical Specification
        CRYPTOCELL — ARM TrustZone CryptoCell 312
          Usage
          Direct memory access (DMA)
          Standards
          Registers
            ENABLE
        DCNF — Domain configuration
          Protection
          Registers
            CPUID
            EXTPERI[n].PROTECT
            EXTRAM[n].PROTECT
            EXTCODE[n].PROTECT
        DPPI - Distributed programmable peripheral interconnect
          Subscribing to and publishing on channels
          DPPI configuration (DPPIC)
          Connection examples
          Special considerations for a system implementing TrustZone for Cortex-M processors
          Registers
            TASKS_CHG[n].EN
            TASKS_CHG[n].DIS
            SUBSCRIBE_CHG[n].EN
            SUBSCRIBE_CHG[n].DIS
            CHEN
            CHENSET
            CHENCLR
            CHG[n]
        ECB — AES electronic codebook mode encryption
          Shared resources
          EasyDMA
          ECB data structure
          Registers
            TASKS_STARTECB
            TASKS_STOPECB
            SUBSCRIBE_STARTECB
            SUBSCRIBE_STOPECB
            EVENTS_ENDECB
            EVENTS_ERRORECB
            PUBLISH_ENDECB
            PUBLISH_ERRORECB
            INTENSET
            INTENCLR
            ECBDATAPTR
          Electrical specification
            ECB Electrical Specification
        EGU — Event generator unit
          Registers
            TASKS_TRIGGER[n]
            SUBSCRIBE_TRIGGER[n]
            EVENTS_TRIGGERED[n]
            PUBLISH_TRIGGERED[n]
            INTEN
            INTENSET
            INTENCLR
          Electrical specification
            EGU Electrical Specification
        FPU - Floating point unit (FPU) exceptions
          Registers
            EVENTS_INVALIDOPERATION
            EVENTS_DIVIDEBYZERO
            EVENTS_OVERFLOW
            EVENTS_UNDERFLOW
            EVENTS_INEXACT
            EVENTS_DENORMALINPUT
            INTEN
            INTENSET
            INTENCLR
        GPIO — General purpose input/output
          Assigning pins to MCUs and Subsystems
          Pin configuration
          Pin sense mechanism
          GPIO security
          Registers
            OUT ( Retained )
            OUTSET
            OUTCLR
            IN
            DIR ( Retained )
            DIRSET
            DIRCLR
            LATCH ( Retained )
            DETECTMODE ( Retained )
            DETECTMODE_SEC ( Retained )
            PIN_CNF[n]
          Electrical specification
            GPIO Electrical Specification
        GPIOTE — GPIO tasks and events
          Pin events and tasks
          Port event
          Tasks and events pin configuration
          Registers
            TASKS_OUT[n]
            TASKS_SET[n]
            TASKS_CLR[n]
            SUBSCRIBE_OUT[n]
            SUBSCRIBE_SET[n]
            SUBSCRIBE_CLR[n]
            EVENTS_IN[n]
            EVENTS_PORT
            PUBLISH_IN[n]
            PUBLISH_PORT
            INTENSET
            INTENCLR
            CONFIG[n]
          Electrical specification
        I2S — Inter-IC sound interface
          Mode
          Transmitting and receiving
          Left right clock (LRCK)
          Serial clock (SCK)
          Master clock (MCK)
            Clock source selection
            Configuration examples
          Width, alignment and format
          EasyDMA
          Module operation
          Pin configuration
          Registers
            TASKS_START
            TASKS_STOP
            SUBSCRIBE_START
            SUBSCRIBE_STOP
            EVENTS_RXPTRUPD
            EVENTS_STOPPED
            EVENTS_TXPTRUPD
            EVENTS_FRAMESTART
            PUBLISH_RXPTRUPD
            PUBLISH_STOPPED
            PUBLISH_TXPTRUPD
            PUBLISH_FRAMESTART
            INTEN
            INTENSET
            INTENCLR
            ENABLE
            CONFIG.MODE
            CONFIG.RXEN
            CONFIG.TXEN
            CONFIG.MCKEN
            CONFIG.MCKFREQ
            CONFIG.RATIO
            CONFIG.SWIDTH
            CONFIG.ALIGN
            CONFIG.FORMAT
            CONFIG.CHANNELS
            CONFIG.CLKCONFIG
            RXD.PTR
            TXD.PTR
            RXTXD.MAXCNT
            PSEL.MCK
            PSEL.SCK
            PSEL.LRCK
            PSEL.SDIN
            PSEL.SDOUT
          Electrical specification
            I2S timing specification
        IPC — Interprocessor communication
          IPC and PPI connections
          Registers
            TASKS_SEND[n]
            SUBSCRIBE_SEND[n]
            EVENTS_RECEIVE[n]
            PUBLISH_RECEIVE[n]
            INTEN
            INTENSET
            INTENCLR
            INTPEND
            SEND_CNF[n]
            RECEIVE_CNF[n]
            GPMEM[n]
          Electrical specification
            IPC Electrical Specification
        KMU — Key management unit
          Functional view
          Access control
          Protecting the UICR content
          Usage
            OTP
            Key storage
              Selecting a key slot
              Writing to a key slot
              Reading a key value
              Push over secure APB
              Revoking the key slots
            STATUS register
          Registers
            TASKS_PUSH_KEYSLOT
            EVENTS_KEYSLOT_PUSHED
            EVENTS_KEYSLOT_REVOKED
            EVENTS_KEYSLOT_ERROR
            INTEN
            INTENSET
            INTENCLR
            INTPEND
            STATUS
            SELECTKEYSLOT
        LPCOMP — Low-power comparator
          Shared resources
          Pin configuration
          Registers
            TASKS_START
            TASKS_STOP
            TASKS_SAMPLE
            SUBSCRIBE_START
            SUBSCRIBE_STOP
            SUBSCRIBE_SAMPLE
            EVENTS_READY
            EVENTS_DOWN
            EVENTS_UP
            EVENTS_CROSS
            PUBLISH_READY
            PUBLISH_DOWN
            PUBLISH_UP
            PUBLISH_CROSS
            SHORTS
            INTENSET
            INTENCLR
            RESULT
            ENABLE
            PSEL
            REFSEL
            EXTREFSEL
            ANADETECT
            HYST
          Electrical specification
            LPCOMP Electrical Specification
        MUTEX — Mutual exclusive peripheral
          Registers
            MUTEX[n]
        NFCT — Near field communication tag
          Overview
          Operating states
          Pin configuration
          EasyDMA
          Frame assembler
          Frame disassembler
          Frame timing controller
          Collision resolution
          Antenna interface
          NFCT antenna recommendations
          Battery protection
           References
          Registers
            TASKS_ACTIVATE
            TASKS_DISABLE
            TASKS_SENSE
            TASKS_STARTTX
            TASKS_ENABLERXDATA
            TASKS_GOIDLE
            TASKS_GOSLEEP
            SUBSCRIBE_ACTIVATE
            SUBSCRIBE_DISABLE
            SUBSCRIBE_SENSE
            SUBSCRIBE_STARTTX
            SUBSCRIBE_ENABLERXDATA
            SUBSCRIBE_GOIDLE
            SUBSCRIBE_GOSLEEP
            EVENTS_READY
            EVENTS_FIELDDETECTED
            EVENTS_FIELDLOST
            EVENTS_TXFRAMESTART
            EVENTS_TXFRAMEEND
            EVENTS_RXFRAMESTART
            EVENTS_RXFRAMEEND
            EVENTS_ERROR
            EVENTS_RXERROR
            EVENTS_ENDRX
            EVENTS_ENDTX
            EVENTS_AUTOCOLRESSTARTED
            EVENTS_COLLISION
            EVENTS_SELECTED
            EVENTS_STARTED
            PUBLISH_READY
            PUBLISH_FIELDDETECTED
            PUBLISH_FIELDLOST
            PUBLISH_TXFRAMESTART
            PUBLISH_TXFRAMEEND
            PUBLISH_RXFRAMESTART
            PUBLISH_RXFRAMEEND
            PUBLISH_ERROR
            PUBLISH_RXERROR
            PUBLISH_ENDRX
            PUBLISH_ENDTX
            PUBLISH_AUTOCOLRESSTARTED
            PUBLISH_COLLISION
            PUBLISH_SELECTED
            PUBLISH_STARTED
            SHORTS
            INTEN
            INTENSET
            INTENCLR
            ERRORSTATUS
            FRAMESTATUS.RX
            NFCTAGSTATE
            SLEEPSTATE
            FIELDPRESENT
            FRAMEDELAYMIN
            FRAMEDELAYMAX
            FRAMEDELAYMODE
            PACKETPTR
            MAXLEN
            TXD.FRAMECONFIG
            TXD.AMOUNT
            RXD.FRAMECONFIG
            RXD.AMOUNT
            MODULATIONCTRL
            MODULATIONPSEL
            NFCID1_LAST
            NFCID1_2ND_LAST
            NFCID1_3RD_LAST
            AUTOCOLRESCONFIG
            SENSRES
            SELRES
          Electrical specification
            NFCT Electrical Specification
            NFCT Timing Parameters
        NVMC — Non-volatile memory controller
          Writing to flash
          Erasing a secure page in flash
          Erasing a non-secure page in flash
          Writing to user information configuration registers (UICR)
          Erase all
          NVMC protection mechanisms
            NVMC blocking
            NVMC power failure protection
          Cache
          Registers
            READY
            READYNEXT
            CONFIG
            ERASEALL
            ERASEPAGEPARTIALCFG
            ICACHECNF
            IHIT
            IMISS
            CONFIGNS
            WRITEUICRNS
          Electrical specification
            Flash programming
            Cache size
        PDM — Pulse density modulation interface
          Master clock source selection
          Master clock generator
          Module operation
          Decimation filter
          EasyDMA
          Hardware example
          Pin configuration
          Registers
            TASKS_START
            TASKS_STOP
            SUBSCRIBE_START
            SUBSCRIBE_STOP
            EVENTS_STARTED
            EVENTS_STOPPED
            EVENTS_END
            PUBLISH_STARTED
            PUBLISH_STOPPED
            PUBLISH_END
            INTEN
            INTENSET
            INTENCLR
            ENABLE
            PDMCLKCTRL
            MODE
            GAINL
            GAINR
            RATIO
            PSEL.CLK
            PSEL.DIN
            MCLKCONFIG
            SAMPLE.PTR
            SAMPLE.MAXCNT
          Electrical specification
            PDM Electrical Specification
        PWM — Pulse width modulation
          Wave counter
          Decoder with EasyDMA
          Limitations
          Pin configuration
          Registers
            TASKS_STOP
            TASKS_SEQSTART[n]
            TASKS_NEXTSTEP
            SUBSCRIBE_STOP
            SUBSCRIBE_SEQSTART[n]
            SUBSCRIBE_NEXTSTEP
            EVENTS_STOPPED
            EVENTS_SEQSTARTED[n]
            EVENTS_SEQEND[n]
            EVENTS_PWMPERIODEND
            EVENTS_LOOPSDONE
            PUBLISH_STOPPED
            PUBLISH_SEQSTARTED[n]
            PUBLISH_SEQEND[n]
            PUBLISH_PWMPERIODEND
            PUBLISH_LOOPSDONE
            SHORTS
            INTEN
            INTENSET
            INTENCLR
            ENABLE
            MODE
            COUNTERTOP
            PRESCALER
            DECODER
            LOOP
            SEQ[n].PTR
            SEQ[n].CNT
            SEQ[n].REFRESH
            SEQ[n].ENDDELAY
            PSEL.OUT[n]
        QDEC — Quadrature decoder
          Sampling and decoding
          LED output
          Debounce filters
          Accumulators
          Output/input pins
          Pin configuration
          Registers
            TASKS_START
            TASKS_STOP
            TASKS_READCLRACC
            TASKS_RDCLRACC
            TASKS_RDCLRDBL
            SUBSCRIBE_START
            SUBSCRIBE_STOP
            SUBSCRIBE_READCLRACC
            SUBSCRIBE_RDCLRACC
            SUBSCRIBE_RDCLRDBL
            EVENTS_SAMPLERDY
            EVENTS_REPORTRDY
            EVENTS_ACCOF
            EVENTS_DBLRDY
            EVENTS_STOPPED
            PUBLISH_SAMPLERDY
            PUBLISH_REPORTRDY
            PUBLISH_ACCOF
            PUBLISH_DBLRDY
            PUBLISH_STOPPED
            SHORTS
            INTENSET
            INTENCLR
            ENABLE
            LEDPOL
            SAMPLEPER
            SAMPLE
            REPORTPER
            ACC
            ACCREAD
            PSEL.LED
            PSEL.A
            PSEL.B
            DBFEN
            LEDPRE
            ACCDBL
            ACCDBLREAD
          Electrical specification
            QDEC Electrical Specification
        QSPI — Quad serial peripheral interface
          Configuring peripheral
          Write operation
          Read operation
          Erase operation
          Execute in place
          Encryption
          Sending custom instructions
            Long frame mode
          Deep power-down mode
          Instruction set
          Interface description
          Registers
            TASKS_ACTIVATE
            TASKS_READSTART
            TASKS_WRITESTART
            TASKS_ERASESTART
            TASKS_DEACTIVATE
            SUBSCRIBE_ACTIVATE
            SUBSCRIBE_READSTART
            SUBSCRIBE_WRITESTART
            SUBSCRIBE_ERASESTART
            SUBSCRIBE_DEACTIVATE
            EVENTS_READY
            PUBLISH_READY
            INTEN
            INTENSET
            INTENCLR
            ENABLE
            READ.SRC
            READ.DST
            READ.CNT
            WRITE.DST
            WRITE.SRC
            WRITE.CNT
            ERASE.PTR
            ERASE.LEN
            PSEL.SCK
            PSEL.CSN
            PSEL.IO0
            PSEL.IO1
            PSEL.IO2
            PSEL.IO3
            XIPOFFSET
            IFCONFIG0
            XIPEN
            XIP_ENC.KEY0
            XIP_ENC.KEY1
            XIP_ENC.KEY2
            XIP_ENC.KEY3
            XIP_ENC.NONCE0
            XIP_ENC.NONCE1
            XIP_ENC.NONCE2
            XIP_ENC.ENABLE
            DMA_ENC.KEY0
            DMA_ENC.KEY1
            DMA_ENC.KEY2
            DMA_ENC.KEY3
            DMA_ENC.NONCE0
            DMA_ENC.NONCE1
            DMA_ENC.NONCE2
            DMA_ENC.ENABLE
            IFCONFIG1
            STATUS
            DPMDUR
            ADDRCONF
            CINSTRCONF
            CINSTRDAT0
            CINSTRDAT1
            IFTIMING
          Electrical specification
            Timing specification
        RADIO — 2.4 GHz radio
          Packet configuration
          Address configuration
          Data whitening
          CRC
          Radio states
          Transmit sequence
          Receive sequence
          Received signal strength indicator (RSSI)
          Interframe spacing (IFS)
          Device address match
          Bit counter
          Direction finding
            CTE format
            Mode
            Inline configuration
            Manual configuration
            Receive- and transmit sequences
            Antenna switching
            IQ sampling
          IEEE 802.15.4 operation
            Packet structure
            Operating frequencies
            Energy detection (ED)
            Clear channel assessment (CCA)
            Cyclic redundancy check (CRC)
            Transmit sequence
            Receive sequence
            Interframe spacing (IFS)
          EasyDMA
          Registers
            TASKS_TXEN
            TASKS_RXEN
            TASKS_START
            TASKS_STOP
            TASKS_DISABLE
            TASKS_RSSISTART
            TASKS_RSSISTOP
            TASKS_BCSTART
            TASKS_BCSTOP
            TASKS_EDSTART
            TASKS_EDSTOP
            TASKS_CCASTART
            TASKS_CCASTOP
            SUBSCRIBE_TXEN
            SUBSCRIBE_RXEN
            SUBSCRIBE_START
            SUBSCRIBE_STOP
            SUBSCRIBE_DISABLE
            SUBSCRIBE_RSSISTART
            SUBSCRIBE_RSSISTOP
            SUBSCRIBE_BCSTART
            SUBSCRIBE_BCSTOP
            SUBSCRIBE_EDSTART
            SUBSCRIBE_EDSTOP
            SUBSCRIBE_CCASTART
            SUBSCRIBE_CCASTOP
            EVENTS_READY
            EVENTS_ADDRESS
            EVENTS_PAYLOAD
            EVENTS_END
            EVENTS_DISABLED
            EVENTS_DEVMATCH
            EVENTS_DEVMISS
            EVENTS_RSSIEND
            EVENTS_BCMATCH
            EVENTS_CRCOK
            EVENTS_CRCERROR
            EVENTS_FRAMESTART
            EVENTS_EDEND
            EVENTS_EDSTOPPED
            EVENTS_CCAIDLE
            EVENTS_CCABUSY
            EVENTS_CCASTOPPED
            EVENTS_RATEBOOST
            EVENTS_TXREADY
            EVENTS_RXREADY
            EVENTS_MHRMATCH
            EVENTS_PHYEND
            EVENTS_CTEPRESENT
            PUBLISH_READY
            PUBLISH_ADDRESS
            PUBLISH_PAYLOAD
            PUBLISH_END
            PUBLISH_DISABLED
            PUBLISH_DEVMATCH
            PUBLISH_DEVMISS
            PUBLISH_RSSIEND
            PUBLISH_BCMATCH
            PUBLISH_CRCOK
            PUBLISH_CRCERROR
            PUBLISH_FRAMESTART
            PUBLISH_EDEND
            PUBLISH_EDSTOPPED
            PUBLISH_CCAIDLE
            PUBLISH_CCABUSY
            PUBLISH_CCASTOPPED
            PUBLISH_RATEBOOST
            PUBLISH_TXREADY
            PUBLISH_RXREADY
            PUBLISH_MHRMATCH
            PUBLISH_PHYEND
            PUBLISH_CTEPRESENT
            SHORTS
            INTENSET
            INTENCLR
            CRCSTATUS
            RXMATCH
            RXCRC
            DAI
            PDUSTAT
            CTESTATUS
            DFESTATUS
            PACKETPTR
            FREQUENCY
            TXPOWER
            MODE
            PCNF0
            PCNF1
            BASE0
            BASE1
            PREFIX0
            PREFIX1
            TXADDRESS
            RXADDRESSES
            CRCCNF
            CRCPOLY
            CRCINIT
            TIFS
            RSSISAMPLE
            STATE
            DATAWHITEIV
            BCC
            DAB[n]
            DAP[n]
            DACNF
            MHRMATCHCONF
            MHRMATCHMAS
            MODECNF0
            SFD
            EDCNT
            EDSAMPLE
            CCACTRL
            DFEMODE
            CTEINLINECONF
            DFECTRL1
            DFECTRL2
            SWITCHPATTERN
            CLEARPATTERN
            PSEL.DFEGPIO[n]
            DFEPACKET.PTR
            DFEPACKET.MAXCNT
            DFEPACKET.AMOUNT
            POWER
          Electrical specification
            General radio characteristics
            Radio current consumption (transmitter)
            Radio current consumption (Receiver)
            Transmitter specification
            Receiver operation
            RX selectivity
            RX intermodulation
            Radio timing
            Received signal strength indicator (RSSI) specifications
            Jitter
            IEEE 802.15.4 energy detection constants
        RNG — Random number generator
          Bias correction
          Speed
          Registers
            TASKS_START
            TASKS_STOP
            SUBSCRIBE_START
            SUBSCRIBE_STOP
            EVENTS_VALRDY
            PUBLISH_VALRDY
            SHORTS
            INTENSET
            INTENCLR
            CONFIG
            VALUE
          Electrical specification
            RNG Electrical Specification
        RTC — Real-time counter
          Clock source
          Resolution versus overflow and the prescaler
          Counter register
            Reading the counter register
          Overflow
          Tick event
          Event control
          Capture
          Compare
          Task and event jitter/delay
          Registers
            TASKS_START
            TASKS_STOP
            TASKS_CLEAR
            TASKS_TRIGOVRFLW
            TASKS_CAPTURE[n]
            SUBSCRIBE_START
            SUBSCRIBE_STOP
            SUBSCRIBE_CLEAR
            SUBSCRIBE_TRIGOVRFLW
            SUBSCRIBE_CAPTURE[n]
            EVENTS_TICK
            EVENTS_OVRFLW
            EVENTS_COMPARE[n]
            PUBLISH_TICK
            PUBLISH_OVRFLW
            PUBLISH_COMPARE[n]
            SHORTS
            INTENSET
            INTENCLR
            EVTEN
            EVTENSET
            EVTENCLR
            COUNTER
            PRESCALER
            CC[n]
          Electrical specification
        SAADC — Successive approximation analog-to-digital converter
          Shared resources
          Overview
          Digital output
          Analog inputs and channels
          Operation modes
            One-shot mode
            Continuous mode
            Oversampling
            Scan mode
          EasyDMA
          Resistor ladder
          Reference
          Acquisition time
          Limits event monitoring
          Registers
            TASKS_START
            TASKS_SAMPLE
            TASKS_STOP
            TASKS_CALIBRATEOFFSET
            SUBSCRIBE_START
            SUBSCRIBE_SAMPLE
            SUBSCRIBE_STOP
            SUBSCRIBE_CALIBRATEOFFSET
            EVENTS_STARTED
            EVENTS_END
            EVENTS_DONE
            EVENTS_RESULTDONE
            EVENTS_CALIBRATEDONE
            EVENTS_STOPPED
            EVENTS_CH[n].LIMITH
            EVENTS_CH[n].LIMITL
            PUBLISH_STARTED
            PUBLISH_END
            PUBLISH_DONE
            PUBLISH_RESULTDONE
            PUBLISH_CALIBRATEDONE
            PUBLISH_STOPPED
            PUBLISH_CH[n].LIMITH
            PUBLISH_CH[n].LIMITL
            INTEN
            INTENSET
            INTENCLR
            STATUS
            ENABLE
            CH[n].PSELP
            CH[n].PSELN
            CH[n].CONFIG
            CH[n].LIMIT
            RESOLUTION
            OVERSAMPLE
            SAMPLERATE
            RESULT.PTR
            RESULT.MAXCNT
            RESULT.AMOUNT
          Electrical specification
            SAADC Electrical Specification
          Performance factors
        SPIM — Serial peripheral interface master with EasyDMA
          SPI master transaction sequence
          D/CX functionality
          Pin configuration
          Shared resources
          EasyDMA
          Low power
          Registers
            TASKS_START
            TASKS_STOP
            TASKS_SUSPEND
            TASKS_RESUME
            SUBSCRIBE_START
            SUBSCRIBE_STOP
            SUBSCRIBE_SUSPEND
            SUBSCRIBE_RESUME
            EVENTS_STOPPED
            EVENTS_ENDRX
            EVENTS_END
            EVENTS_ENDTX
            EVENTS_STARTED
            PUBLISH_STOPPED
            PUBLISH_ENDRX
            PUBLISH_END
            PUBLISH_ENDTX
            PUBLISH_STARTED
            SHORTS
            INTENSET
            INTENCLR
            STALLSTAT
            ENABLE
            PSEL.SCK
            PSEL.MOSI
            PSEL.MISO
            PSEL.CSN
            FREQUENCY
            RXD.PTR
            RXD.MAXCNT
            RXD.AMOUNT
            RXD.LIST
            TXD.PTR
            TXD.MAXCNT
            TXD.AMOUNT
            TXD.LIST
            CONFIG
            IFTIMING.RXDELAY
            IFTIMING.CSNDUR
            CSNPOL
            PSELDCX
            DCXCNT
            ORC
          Electrical specification
            Timing specifications
        SPIS — Serial peripheral interface slave with EasyDMA
          Shared resources
          EasyDMA
          SPI slave operation
          Pin configuration
          Registers
            TASKS_ACQUIRE
            TASKS_RELEASE
            SUBSCRIBE_ACQUIRE
            SUBSCRIBE_RELEASE
            EVENTS_END
            EVENTS_ENDRX
            EVENTS_ACQUIRED
            PUBLISH_END
            PUBLISH_ENDRX
            PUBLISH_ACQUIRED
            SHORTS
            INTENSET
            INTENCLR
            SEMSTAT
            STATUS
            ENABLE
            PSEL.SCK
            PSEL.MISO
            PSEL.MOSI
            PSEL.CSN
            PSELSCK ( Deprecated )
            PSELMISO ( Deprecated )
            PSELMOSI ( Deprecated )
            PSELCSN ( Deprecated )
            RXDPTR ( Deprecated )
            MAXRX ( Deprecated )
            AMOUNTRX ( Deprecated )
            RXD.PTR
            RXD.MAXCNT
            RXD.AMOUNT
            RXD.LIST
            TXDPTR ( Deprecated )
            MAXTX ( Deprecated )
            AMOUNTTX ( Deprecated )
            TXD.PTR
            TXD.MAXCNT
            TXD.AMOUNT
            TXD.LIST
            CONFIG
            DEF
            ORC
          Electrical specification
            SPIS slave interface electrical specifications
            Serial Peripheral Interface Slave (SPIS) timing specifications
        SPU — System protection unit
          General concepts
            Special considerations for ARM TrustZone for Cortex-M enabled system
          Flash access control
            Non-secure callable (NSC) region definition in flash
            Flash access error reporting
            UICR and FICR protections
          RAM access control
            Non-secure callable (NSC) region definition in RAM
            RAM access error reporting
          Peripheral access control
            Peripherals with split security
            Peripheral address mapping
            Special considerations for peripherals with DMA master
            Peripheral access error reporting
          Pin access control
          DPPI access control
            Special considerations regarding the DPPIC configuration registers
          External domain access control
          TrustZone for Cortex-M ID allocation
          Registers
            EVENTS_RAMACCERR
            EVENTS_FLASHACCERR
            EVENTS_PERIPHACCERR
            PUBLISH_RAMACCERR
            PUBLISH_FLASHACCERR
            PUBLISH_PERIPHACCERR
            INTEN
            INTENSET
            INTENCLR
            CAP
            CPULOCK
            EXTDOMAIN[n].PERM
            DPPI[n].PERM
            DPPI[n].LOCK
            GPIOPORT[n].PERM
            GPIOPORT[n].LOCK
            FLASHNSC[n].REGION
            FLASHNSC[n].SIZE
            RAMNSC[n].REGION
            RAMNSC[n].SIZE
            FLASHREGION[n].PERM
            RAMREGION[n].PERM
            PERIPHID[n].PERM
        SWI — Software interrupts
          Registers
        TEMP — Temperature sensor
          Registers
            TASKS_START
            TASKS_STOP
            SUBSCRIBE_START
            SUBSCRIBE_STOP
            EVENTS_DATARDY
            PUBLISH_DATARDY
            INTENSET
            INTENCLR
            TEMP
            A0
            A1
            A2
            A3
            A4
            A5
            B0
            B1
            B2
            B3
            B4
            B5
            T0
            T1
            T2
            T3
            T4
          Electrical specification
            Temperature Sensor Electrical Specification
        TIMER — Timer/counter
          Capture
          Compare
          Task delays
          Task priority
          Registers
            TASKS_START
            TASKS_STOP
            TASKS_COUNT
            TASKS_CLEAR
            TASKS_SHUTDOWN ( Deprecated )
            TASKS_CAPTURE[n]
            SUBSCRIBE_START
            SUBSCRIBE_STOP
            SUBSCRIBE_COUNT
            SUBSCRIBE_CLEAR
            SUBSCRIBE_SHUTDOWN ( Deprecated )
            SUBSCRIBE_CAPTURE[n]
            EVENTS_COMPARE[n]
            PUBLISH_COMPARE[n]
            SHORTS
            INTEN
            INTENSET
            INTENCLR
            MODE
            BITMODE
            PRESCALER
            CC[n]
            ONESHOTEN[n]
          Electrical specification
        TWIM — I2C compatible two-wire interface master with EasyDMA
          Shared resources
          EasyDMA
          Master write sequence
          Master read sequence
          Master repeated start sequence
          Low power
          Master mode pin configuration
          Registers
            TASKS_STARTRX
            TASKS_STARTTX
            TASKS_STOP
            TASKS_SUSPEND
            TASKS_RESUME
            SUBSCRIBE_STARTRX
            SUBSCRIBE_STARTTX
            SUBSCRIBE_STOP
            SUBSCRIBE_SUSPEND
            SUBSCRIBE_RESUME
            EVENTS_STOPPED
            EVENTS_ERROR
            EVENTS_SUSPENDED
            EVENTS_RXSTARTED
            EVENTS_TXSTARTED
            EVENTS_LASTRX
            EVENTS_LASTTX
            PUBLISH_STOPPED
            PUBLISH_ERROR
            PUBLISH_SUSPENDED
            PUBLISH_RXSTARTED
            PUBLISH_TXSTARTED
            PUBLISH_LASTRX
            PUBLISH_LASTTX
            SHORTS
            INTEN
            INTENSET
            INTENCLR
            ERRORSRC
            ENABLE
            PSEL.SCL
            PSEL.SDA
            FREQUENCY
            RXD.PTR
            RXD.MAXCNT
            RXD.AMOUNT
            RXD.LIST
            TXD.PTR
            TXD.MAXCNT
            TXD.AMOUNT
            TXD.LIST
            ADDRESS
          Electrical specification
            TWIM interface electrical specifications
            Two Wire Interface Master (TWIM) timing specifications
          Pullup resistor
        TWIS — I2C compatible two-wire interface slave with EasyDMA
          Shared resources
          EasyDMA
          TWI slave responding to a read command
          TWI slave responding to a write command
          Master repeated start sequence
          Terminating an ongoing TWI transaction
          Low power
          Slave mode pin configuration
          Registers
            TASKS_STOP
            TASKS_SUSPEND
            TASKS_RESUME
            TASKS_PREPARERX
            TASKS_PREPARETX
            SUBSCRIBE_STOP
            SUBSCRIBE_SUSPEND
            SUBSCRIBE_RESUME
            SUBSCRIBE_PREPARERX
            SUBSCRIBE_PREPARETX
            EVENTS_STOPPED
            EVENTS_ERROR
            EVENTS_RXSTARTED
            EVENTS_TXSTARTED
            EVENTS_WRITE
            EVENTS_READ
            PUBLISH_STOPPED
            PUBLISH_ERROR
            PUBLISH_RXSTARTED
            PUBLISH_TXSTARTED
            PUBLISH_WRITE
            PUBLISH_READ
            SHORTS
            INTEN
            INTENSET
            INTENCLR