Processor usage patterns and availability

This section gives an overview of the processor usage patterns for features of the SoftDevice and the processor availability to the application in stated scenarios.

The SoftDevice's processor use will also affect the maximum interrupt latency for application interrupts of lower priority (higher numerical value for the interrupt priority). The maximum interrupt processing time for the different priority levels in this chapter can be used to calculate the worst-case interrupt latency the application will have to handle when the SoftDevice is used in various scenarios.

In the following scenarios, tISR(x) denotes interrupt processing time at priority level x, and tnISR(x) denotes time between interrupts at priority level x.