Interrupt latency due to System on Chip (SoC) framework

Latency, additional to ARM® Cortex® -M4 hardware architecture latency, is introduced by SoftDevice logic to manage interrupt events.

This latency occurs when an interrupt is forwarded to the application from the SoftDevice and is part of the minimum latency for each application interrupt. This is the latency added by the interrupt forwarding latency alone. The maximum application interrupt latency is dependent on SoftDevice activity, as described in section Processor usage patterns and availability.

Table 1. Additional latency due to SoftDevice and MBR forwarding interrupts
Interrupt SoftDevice enabled SoftDevice disabled
Open peripheral interrupt < 3 μs < 1 μs
Blocked or restricted peripheral interrupt (only forwarded when SoftDevice disabled) N/A < 2 μs
Application SVC interrupt < 2 μs < 2 μs