Flash API processor usage patterns

This section describes the processor availability and interrupt processing time for the SoftDevice when the Flash API is being used.

Figure 1. Flash API activity (some priority levels left out for clarity)

When using the Flash API, the pattern of SoftDevice CPU activity at interrupt priority level 0 is as follows:

  1. An interrupt at priority level 0 sets up and performs the flash activity. The CPU is halted for most of the time in this interrupt.
  2. After the first interrupt is finished, another interrupt at priority level 4 does some cleanup after the flash operation.

SoftDevice processing activity in the different priority levels during flash erase and write is outlined in the table below.

Table 1. Processor usage for the Flash API
Parameter Description Min Typical Max
tISR(0),FlashErase Interrupt processing when erasing a flash page. Note that the CPU is halted most of the length of this interrupt.     90 ms
tISR(0),FlashWrite Interrupt processing when writing one or more words to flash. Note that the CPU is halted most of the length of this interrupt. The Max time provided is for writing one word. When writing more than one word, please see the Product Specification to find out how long time is needed for per word to write, and add to the Max time provided in this table.     500 μs
tISR(4) Priority level 4 interrupt at the end of flash write or erase.   10 μs