Master Boot Record

The main functionality of the MBR is to provide an interface to allow in-system updates of the SoftDevice and bootloader firmware.

The Master Boot Record (MBR) module occupies a defined region in the SoC program memory where the System Vector table resides.

All exceptions (reset, hard fault, interrupts, SVC) are first processed by the MBR and then are forwarded to the appropriate handlers (for example the bootloader or the SoftDevice exception handlers). For more information on the interrupt forwarding scheme, see Interrupt model and processor availability.

During a firmware update process, the MBR is never erased. The MBR ensures that the bootloader can recover from any unexpected resets during an ongoing update process.

To issue the SD_MBR_COMMAND_COPY_BL or SD_MBR_COMMAND_VECTOR_TABLE_BASE_SET commands to the MBR, the UICR.NRFFW[1] register must be set to an address (see MBRPARAMADDR address in Figure 1 ) corresponding to a page in the Application Flash Region (see Memory isolation and runtime protection). If UICR.NRFFW[1] is not set, the commands will return NRF_ERROR_NO_MEM. This page will be cleared by the MBR and used to store parameters before chip reset. When the UICR.NRFFW[1] register is set, the page it refers to must not be used by the application. If the application does not want to reserve a page for the MBR parameters, it must leave the UICR.NRFFW[1] register to 0xFFFFFFFF (its default value).