WDT — Watchdog timer

A countdown watchdog timer using the low-frequency clock source (LFCLK) offers configurable and robust protection against application lock-up.

The watchdog timer is started by triggering the START task.

The watchdog can be paused during long CPU sleep periods for low power applications and when the debugger has halted the CPU. The watchdog is implemented as a down-counter that generates a TIMEOUT event when it wraps over after counting down to 0. When the watchdog timer is started through the START task, the watchdog counter is loaded with the value specified in the CRV register. This counter is also reloaded with the value specified in the CRV register when a reload request is granted.

The watchdog’s timeout period is given by:


      timeout [s] = ( CRV + 1 ) / 32768
    

When started, the watchdog will automatically force the 32.768 kHz RC oscillator on as long as no other 32.768 kHz clock source is running and generating the 32.768 kHz system clock, see chapter CLOCK — Clock control.

Reload criteria

The watchdog has eight separate reload request registers, which shall be used to request the watchdog to reload its counter with the value specified in the CRV register. To reload the watchdog counter, the special value 0x6E524635 needs to be written to all enabled reload registers.

One or more RR registers can be individually enabled through the RREN register.

Temporarily pausing the watchdog

By default, the watchdog will be active counting down the down-counter while the CPU is sleeping and when it is halted by the debugger. It is however possible to configure the watchdog to automatically pause while the CPU is sleeping as well as when it is halted by the debugger.

Watchdog reset

A TIMEOUT event will automatically lead to a watchdog reset.

See Reset for more information about reset sources. If the watchdog is configured to generate an interrupt on the TIMEOUT event, the watchdog reset will be postponed with two 32.768 kHz clock cycles after the TIMEOUT event has been generated. Once the TIMEOUT event has been generated, the impending watchdog reset will always be effectuated.

The watchdog must be configured before it is started. After it is started, the watchdog’s configuration registers, which comprise registers CRV, RREN, and CONFIG, will be blocked for further configuration.

The watchdog can be reset from several reset sources, see Reset behavior.

When the device starts running again, after a reset, or waking up from OFF mode, the watchdog configuration registers will be available for configuration again.

Registers

Table 1. Instances
Base address Peripheral Instance Description Configuration
0x40010000 WDT WDT

Watchdog timer

   
Table 2. Register overview
Register Offset Description
TASKS_START 0x000

Start the watchdog

 
EVENTS_TIMEOUT 0x100

Watchdog timeout

 
INTENSET 0x304

Enable interrupt

 
INTENCLR 0x308

Disable interrupt

 
RUNSTATUS 0x400

Run status

 
REQSTATUS 0x404

Request status

 
CRV 0x504

Counter reload value

 
RREN 0x508

Enable register for reload request registers

 
CONFIG 0x50C

Configuration register

 
RR[0] 0x600

Reload request 0

 
RR[1] 0x604

Reload request 1

 
RR[2] 0x608

Reload request 2

 
RR[3] 0x60C

Reload request 3

 
RR[4] 0x610

Reload request 4

 
RR[5] 0x614

Reload request 5

 
RR[6] 0x618

Reload request 6

 
RR[7] 0x61C

Reload request 7

 

INTENSET

Address offset: 0x304

Enable interrupt

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID RW Field Value ID Value Description
A RW

TIMEOUT

   

Write '1' to enable interrupt for TIMEOUT event

See EVENTS_TIMEOUT

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

INTENCLR

Address offset: 0x308

Disable interrupt

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID RW Field Value ID Value Description
A RW

TIMEOUT

   

Write '1' to disable interrupt for TIMEOUT event

See EVENTS_TIMEOUT

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

RUNSTATUS

Address offset: 0x400

Run status

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID RW Field Value ID Value Description
A R

RUNSTATUS

   

Indicates whether or not the watchdog is running

     

NotRunning

0

Watchdog not running

     

Running

1

Watchdog is running

REQSTATUS

Address offset: 0x404

Request status

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                 H G F E D C B A
Reset 0x00000001 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
ID RW Field Value ID Value Description
A-H R

RR[i] (i=0..7)

   

Request status for RR[i] register

     

DisabledOrRequested

0

RR[i] register is not enabled, or are already requesting reload

     

EnabledAndUnrequested

1

RR[i] register is enabled, and are not yet requesting reload

CRV

Address offset: 0x504

Counter reload value

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ID RW Field Value ID Value Description
A RW

CRV

 

[0x0000000F..0xFFFFFFFF]

Counter reload value in number of cycles of the 32.768 kHz clock

RREN

Address offset: 0x508

Enable register for reload request registers

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                 H G F E D C B A
Reset 0x00000001 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
ID RW Field Value ID Value Description
A-H RW

RR[i] (i=0..7)

   

Enable or disable RR[i] register

     

Disabled

0

Disable RR[i] register

     

Enabled

1

Enable RR[i] register

CONFIG

Address offset: 0x50C

Configuration register

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                     C   A
Reset 0x00000001 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
ID RW Field Value ID Value Description
A RW

SLEEP

   

Configure the watchdog to either be paused, or kept running, while the CPU is sleeping

     

Pause

0

Pause watchdog while the CPU is sleeping

     

Run

1

Keep the watchdog running while the CPU is sleeping

C RW

HALT

   

Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger

     

Pause

0

Pause watchdog while the CPU is halted by the debugger

     

Run

1

Keep the watchdog running while the CPU is halted by the debugger

RR[n] (n=0..7)

Address offset: 0x600 + (n × 0x4)

Reload request n

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID RW Field Value ID Value Description
A W

RR

   

Reload request register

     

Reload

0x6E524635

Value to request a reload of the watchdog timer

Electrical specification

Watchdog Timer Electrical Specification

Symbol Description Min. Typ. Max. Units
tWDT

Time out interval

458 µs 36 h  

Documentation feedback | Developer Zone | Updated 2018-03-22