USBD — Universal serial bus device

The USB device controller (USBD) implements a full speed USB device function that meets 2.0 revision of the USB specification.

Listed here are the main features for USBD:

Figure 1. USB block diagram

USB device states

The behaviour of a USB device can be modelled through a state diagram.

Chapter 9 USB Device Framework in the USB specification revision 2.0 defines a number of states for a USB device, illustrated below.

Figure 2. Device state diagram

The device must change state according to host-initiated traffic and USB bus states.

It is up to the software to implement a state machine that matches the above definition.

To detect the presence or absence of USB supply (VBUS), the POWER chapter defines two events USBDETECTED and USBREMOVED, they can be used to implement the state machine.

As a general rule when implementing the software, the host behavior shall never be assumed to be predictable, in particular the sequence of commands received during an enumeration. The software shall always react to the current bus conditions or commands sent by the host.

USB terminology

The USB specification defines bus states, rather than logic levels on the D+ and D- lines.

For a full speed device, the bus state where the D+ line is high and the D- line is low is defined as the J state. The bus state where D+ is low and D- high is called the K state.

An idle bus, where D+ and D- lines are only polarized through the pull-up on D+ and pull-downs on the host side, will be in J state.

Both lines low are called SE0 (single-ended 0), and both lines high SE1 (single-ended 1).

USB pins

The USBD peripheral features a number of dedicated pins.

For more information about the pinout, please refer to Pin assignments.

The dedicated USB pins can be grouped in two categories: signal and power.

For details on the USB power supply and VBUS detection, refer to the POWER chapter.

The signal pins consist of the D+ and D- pins, which are to be connected to the USB host. They are dedicated pins, and not available as standard GPIOs.

The USBD implements the "5V Short Circuit Withstand ECN", which amends the original USB 2.0 Specification. This means that these two pins are not 5 V tolerant.

The signal pins and the pull-up will operate only while VBUS is in its valid voltage range, and USBD is enabled through the ENABLE register.

USBD start-up sequence

The PHY of the USBD is powered separately from the rest of the device (VBUS pin), which has some implications on the USBD power up sequence.

The device is not able to properly signal its presence to the USB host, and handle traffic from the host, unless the PHY's power supply is enabled and stable.

The turning on or off of the PHY's power supply is directly linked to the ENABLE register. The device provides events that help synchronizing software to the various steps during the power up sequence.

It is recommended to enable USBD only after VBUS has been detected, and turn on the USB pull-up after a USBPWRRDY event has occurred, and after a USBEVENT has occurred with the READY condition flagged in EVENTCAUSE. This ensures that all resources in USBD are available and the dedicated USB voltage regulator has stabilized.

Below sequence chart illustrates a typical handling of VBUS power up.

Figure 3. VBUS power up sequence

Upon detection of VBUS removal, signalled by the USBREMOVED event described in the POWER chapter, it is recommended to let on-going EasyDMA transfers finish (wait for the relevant ENDEPIN[n], ENDISOIN, ENDEPOUT[n] or ENDISOOUT event, see EasyDMA), then to disable USBD through writing ENABLE = Disabled .

USB pull-up

The USB pull-up serves two purposes: it indicates to the host that the device is connected to the USB bus, and indicates the device's speed grade.

When no pull-up is connected to the USB bus, the host sees both D+ and D- lines low, as they are pulled down on the host side by 15 kOhm resistors. The device is not seen by the host, and hence defined to be in detached state, even though it could be physically connected to the host. USB spec does not allow to draw any current on VBUS in that situation.

When a full-speed device connects its 1.5 kOhm pull-up to D+, the host sees the corresponding line high. The device is then in attached state. The host may attempt to determine if the device supports higher speeds (which it does not), and will then initiate communication with the device to further identify it; this process is called enumeration.

If the host supports higher speed grades and the device is full-speed, the host may attempt to determine if that device is capable of higher speeds. The USBD peripheral implemented in this device supports only full-speed (12 Mbps), and will ignore the negotiation for higher speeds, in accordance with the USB specification revision 2.0, full speed part.

The USBPULLUP register provides means to connect or disconnect the pull-up on D+ under software control. This allows the software to control when USB enumeration takes place. It also allows to emulate a physical disconnect from the USB bus, for instance when re-enumeration is required.

USBPULLUP has to be set to Enabled to allow the USBD to handle USB traffic and generate appropriate events. This forbids the use of an external pull-up.

Note that disconnecting the pull-up through the USBPULLUP register while connected to a host will result in both D+ and D- lines to be pulled low by the host's pull-down resistors. However, as mentioned above, this will also inhibit the generation of the USBRESET event.

The pull-up is disabled by default after a chip reset.

The pull-up shall only get connected after USBD has been enabled through the ENABLE register. Attempting to access the USBPULLUP register prior to that will lead to an ACCESSFAULT event to get generated.

The USB pull-up value is automatically changed depending on bus activity, as specified in the "Resistor ECN" which amends the original USB Specification v2.0 . The user does not have access to this function, it is handled in hardware.

While they should never be used in normal traffic activity, the task DPDMDRIVE allows at any time to force the D+ and D- lines to the state specified in the DPDMVALUE register. The DPDMNODRIVE task stops driving them, and the PHY returns to normal operation.

USB reset

The USB specification defines a USB reset, which shall not be confused with a chip reset.

The USB reset results from a single-ended low state (SE0) on the D+ / D- lines for a time TDETRST, as specified in the USB specification chapter 7. Only the host is allowed to drive a USB reset condition on the bus.

The USB reset is a normal USB bus condition, and is used as part of the enumeration sequence, it does not reset the chip.

The UBSD peripheral automatically interprets a SE0 longer than tUSB,DETRST as a USB reset. When the device detects a USB reset and generates a USBRESET event, the device USB stack and related parts of the application shall re-initialize themselves, and go back to the Default state.

Some of the registers in the USBD peripheral get automatically reset to a known state, in particular all data endpoints will get disabled, and the USBADDR will be reset to 0.

After having been connected to the USB bus (i.e. after VBUS gets applied), the device shall not respond to any traffic from the time the pull-up is enabled until it has seen a USB reset condition. This is automatically ensured by the USBD.

After a USB reset, the device shall be fully responsive after at most TRSTRCY (as per USB specification chapter 7). Software shall take into account that it takes tUSB,RSTRCY for the hardware to recover from a USB reset condition.

USB suspend and resume

Normally, the host will maintain activity on the USB at least every millisecond per USB specification.

To signal that the device shall go into low power mode, the host stops activity on the USB bus, which becomes idle, only the device pull-up and host pull-downs act on D+ and D-, and the bus is thus kept at a constant J state. It is up to the device to detect this lack of activity, and enter into a low power mode within a specified time.

The USB host can decide at any moment to suspend USB activity. When this happens, the device is obligated per USB specification to enter a low power mode. The host can decide at any moment to resume USB activity, on its own initiative. If Remote WakeUp has been enabled by the host, the device may also issue a RESUME request to wake up the host.

Entering suspend

The USBD peripheral automatically detects a lack of activity for more than tUSB,SUSPEND and will generate the corresponding USBEVENT event, with SUSPEND bit set in the EVENTCAUSE register. The software shall ensure that the current drawn from the USB supply line VBUS is within the specified limits before T2SUSP as defined in chapter 7 of the USB specification.

In order to save power, and provided that no other peripheral needs it, the crystal oscillator (HFXO) in CLOCK may be disabled by software during USB suspend, while the USB pull-up is disconnected, or when VBUS is not present. Software must explicitly enable it at any other time. The USBD will not be able to respond to USB traffic unless HFXO is enabled and stable.

Host-initiated resume

If the host resumes bus activity with or without a RESUME condition (in other words: bus activity is defined as any non-J state), the USBD peripheral will generate a USBEVENT event, with RESUME bit set in the EVENTCAUSE register, and the device has to be responsive to any incoming request on the USB bus within the time TRSMRCY defined in chapter 7 of the USB specification. It is also allowed to revert to normal power consumption mode.

If the host resumes bus activity simply by restarting sending frames, the USBD peripheral will generate SOF events. Also here the device has to be responsive to any incoming request on the USB bus, and can be in normal power consumption mode.

Device-initiated remote wake-up

Assuming that remote wake-up is supported by the device and has been enabled by the host, if the device meets a wake-up condition while the device is suspended, the device can request the host to resume.

To do so, the software shall first make sure that HFXO gets enabled.

It can then instruct the USBD peripheral to drive a RESUME condition (K state) on the USB bus through the DPDMDRIVE task, and hence attempt to wake up the host. By choosing Resume in DPDMVALUE, the duration of the RESUME state is under hardware control (TUSB,DRIVEK). By choosing J or K, the duration of that state is under software control (the J or K state is maintained until a DPDMNODRIVE task is issued), and has to meet TDRSMUP from USB specification chapter 7.

The value in the DPDMVALUE register will only be captured and used when the DPDMDRIVE task is sent.

Note that the device shall ensure that it does not initiate such a remote wake-up request before TWTRSM (as per USB specification chapter 7) after the bus has entered idle state. Using the recommended Resume value in DPDMVALUE, rather than K, takes care of this, and postpones the RESUME state accordingly.

As just explained, the DPDMVALUE register contains the value at which the bus shall be forced after a DPDMDRIVE task. If the software needs to read back the actual D+ and D- lines state, it can do so at any time by reading the BUSSTATE register.

EasyDMA

The USBD peripheral includes EasyDMA so that USB buffers are located in Data RAM .

Each endpoint has an associated set of tasks, events and registers.

The EPIN[n].PTR, EPOUT[n].PTR (n=0..7), ISOIN.PTR and ISOOUT.PTR registers define the address of the buffer in Data RAM for a specific IN or OUT endpoint.

The EPIN[n].MAXCNT and ISOIN.MAXCNT registers define the amount of bytes to be sent on USB for next transaction.

The EPOUT[n].MAXCNT (n=1..7) and ISOOUT.MAXCNT registers define the length of the buffer, in bytes, for next transfer of incoming data. Since the host decides how many bytes are being sent over USB, the MAXCNT value can be copied from the respective SIZE.EPOUT[n] (n=1..7) or SIZE.ISOOUT register.

The EPOUT[0].MAXCNT register defines the length of the control endpoint OUT buffer, in bytes. If the USB host does not misbehave, the SIZE.EPOUT[0] register will indicate the same value than MaxPacketSize from the device descriptor or wLength from the SETUP command, whichever is the smallest.

The .AMOUNT registers indicate how many bytes have actually been transferred over EasyDMA during last transfer.

The STARTEPIN[n], STARTEPOUT[n] (n=0..7), STARTISOIN and STARTISOOUT tasks capture the .PTR and .MAXCNT registers values; for IN endpoints, a transaction over USB gets automatically triggered when the EasyDMA transfer is complete; for OUT endpoints, it is up to software to allow the next transaction over USB, see the examples in Control transfers, Bulk and interrupt transactions and Isochronous transactions.

The STARTED event confirms that the .PTR, .MAXCNT and .CONFIG registers values of the endpoints flagged in the EPSTATUS register have been captured; those can then be modified by software for the next transfer.

The ENDEPIN[n], ENDEPOUT[n] (n=0..7), ENDISOIN and ENDISOOUT events indicate that the whole buffer in Data RAM has been consumed. The buffer can be accessed safely by software.

Only a single EasyDMA transfer can take place in USBD at any time. It is up to the software to ensure that no STARTEPIN[n], STARTISOIN, STARTEPOUT[n] or STARTISOOUT task is sent before having received the ENDEPIN[n], ENDISOIN, ENDEPOUT[n] or ENDISOOUT event from an on-going transfer.

EasyDMA and traffic on USB are tightly related. A number of events provide insight of what is happening on the USB bus, and a number of tasks allow to somewhat automate response to traffic.

The EPDATA event indicates that a successful (acknowledged) data transaction has occurred on the data endpoint(s) flagged in the EPDATASTATUS register.

In the particular case of the control endpoint 0, OUT transactions are allowed through the EP0RCVOUT task. A successful (acknowledged) data transaction on endpoint 0 is signalled by the EP0DATADONE event. The EP0STATUS task allows a status stage to be initiated, and the EP0STALL task allows stalling further traffic (data or status stage) on the control endpoint.

The EP0SETUP event indicates that a SETUP token has been received on the control endpoint 0. EasyDMA will not copy the SETUP data to Data RAM (it will only transfer data from the data stage), they are available as separate registers in the USBD peripheral: BMREQUESTTYPE, BREQUEST, WVALUEL, WVALUEH, WINDEXL, WINDEXH, WLENGTHL and WLENGTHH.

At any time, the USBEVENT event may be sent, and the EVENTCAUSE register provides details on what happened, for instance if a CRC error is detected during a transaction, or if bus activity stops or resumes.

Enabling endpoints is controlled through the EPINEN and EPOUTEN registers.

Stalling bulk/interrupt endpoints is controlled through the EPSTALL register.

Note that due to USB specification requirements, the effect of the stalling control endpoint 0 may be overridden by hardware, in particular when a new SETUP token is received.

Control transfers

The USB specification mandates every USB device to implement endpoint 0 IN and OUT as control endpoints.

A control transfer consists of two or three stages:

  • Setup stage
  • Data stage (optional)
  • Status stage

Each control transfer can be of following type:

  • Control read
  • Control read no data
  • Control write
  • Control write no data

An EP0SETUP event indicates that the data in the setup stage (i.e. following the SETUP token) is available in the BREQUEST, BMREQUESTTYPE, WVALUEL, WVALUEH, WINDEXL, WINDEXH, WLENGTHL and WLENGTHH registers.

The data in the data stage( i.e. following the IN or OUT token) is transferred from or to the desired location in Data RAM using EasyDMA.

Note: the control endpoint buffer size in Data RAM can be of any size in bytes, and there is no constraint to keep it 32-bit aligned.

After receiving the SETUP token, the USB controller will NAK any incoming IN or OUT token until software has finished decoding the command, determined the type of transfer, and prepared the next stage (data or status) appropriately.

The software can choose to STALL the command (both data and status stages) through the EP0STALL task, for instance if the command is not supported, or its wValue, wIndex or wLength parameters are wrong. A stalled Control Read transfer is depicted below, but the same mechanism (same tasks) applies to stalling a Control Write transfer (not depicted).

Refer to the chapter 9 of the USB Specification v2.0 and relevant Class specifications for rules on when to STALL a command.

Figure 4. Control read gets STALLed

Important: the USBD peripheral handles the SetAddress transfer by itself. As a consequence, the software shall not process this command, other than updating its state machine (see Device state diagram), nor initiate a status stage. If necessary, the address assigned by the host can be read out from the USBADDR register after the command has been processed.

Control Read transfer

This section describes how the software behaves to respond to a Control Read transfer.

As mentioned earlier, the USB controller will NAK any incoming IN token until software has finished decoding the command, determined the type of transfer, and prepared the next stage (data or status) appropriately.

For a control-read, transferring the data from Data RAM memory into USBD will trigger a valid, ACKed IN transaction on USB.

The software has to prepare EasyDMA by pointing to the buffer containing the data to be transferred. If no other EasyDMA transfer is on-going with USBD, software can send the STARTEPIN0 task, which will initiate the data transfer and transaction on USB.

A STARTED event (with EPIN0 bit set in the EPSTATUS register) will get fired as soon as the EPIN[0].PTR and .MAXCNT registers have been captured. Software may then prepare them for next data transaction.

A ENDEPIN[0] event will get fired when the data has been transferred from memory to the USBD peripheral.

Finally, an EP0DATADONE event will get fired when the data has been transmitted over USB and acknowledged by the host.

The software can then either prepare and transmit the next data transaction by repeating the above sequence, or initiate the status stage through the EP0STATUS task.

Figure 5. Control read transfer

Note the possibility to enable a shortcut from the EP0DATADONE event to the EP0STATUS task, typically if the data stage is expected to take a single transfer.

If there is no data stage, the software can initiate the status stage through the EP0STATUS task right away, as depicted below.

Figure 6. Control read no data transfer

Control Write transfer

This section describes how the software behaves to respond to a Control Write transfer.

The software has to prepare EasyDMA by pointing to the buffer in Data RAM that shall contain the incoming data. If no other EasyDMA transfer is on-going with USBD, software can then send the EP0RCVOUT task, which will make the USBD to accept (ACK) the first OUT+DATA transaction from the host.

An EP0DATADONE event will get fired when a new OUT+DATA has been transmitted over USB, and is about to get acknowledged by the device.

A STARTED event (with EPOUT0 bit set in the EPSTATUS register) will get fired as soon as the EPOUT[0].PTR and .MAXCNT registers have been captured, after receiving the first transaction. Software may then prepare them for next data transaction.

A ENDEPOUT[0] event will get fired when the data has been transferred from the USBD peripheral to Data RAM.

The software can then either prepare to receive the next data transaction by repeating the above sequence, or initiate the status stage through the EP0STATUS task. Until then, further incoming OUT + DATA transactions get a NAK response by the device.

Figure 7. Control write transfer

Figure 8. Control write no data transfer

Bulk and interrupt transactions

The USBD peripheral implements seven pairs of bulk/interrupt endpoints.

The bulk/interrupt endpoints have a fixed USB endpoint number, summarized in the table below.

Table 1. Bulk/interrupt endpoint numbering
Bulk endpoint # USB IN endpoint USB OUT endpoint
[1] 0x81 0x01
[2] 0x82 0x02
[3] 0x83 0x03
[4] 0x84 0x04
[5] 0x85 0x05
[6] 0x86 0x06
[7] 0x87 0x07

A bulk/interrupt transaction consists of a single data stage. Two consecutive, successful transactions are distinguished through alternating leading PID: DATA0 follows DATA1, DATA1 follows DATA0, etc.

A repeated transaction is detected by re-using the same PID as previous transaction, i.e DATA0 follows DATA0, or DATA1 follows DATA1.

The USBD controller automatically toggles DATA0/DATA1 PIDs for every bulk/interrupt transaction, and in general software does not need to care about it.

If an incoming data is corrupted (CRC does not match), the USBD controller automatically prevents DATA0/DATA1 from toggling, to request the host to resend the data.

In specific cases, the software may want to force data toggle (usually reset) on a specific IN endpoint, or force the expected toggle on an OUT endpoint, for instance as a consequence of the host issuing a ClearFeature, SetInterface or selecting an alternate setting. Controlling the data toggle of data IN or OUT endpoint n=1..7 is done through the DTOGGLE register.

The maximum size of a bulk/interrupt transaction in USB Full Speed is 64 Bytes, and has to be a multiple of 4 bytes, and be 32-bit aligned in Data RAM. However, the amount of DATA bytes transmitted on the USB data endpoint can be of any size (up to 64 bytes).

When the transaction is done over USB, a EPDATA event is sent, and the hardware will automatically NAK further IN tokens, until software is ready to send more data and has finished configuring EasyDMA, has started it, and the whole buffer content has been moved to the USB controller (signalled by the ENDEPIN[n] event).

Each IN or OUT data endpoint has to be explicitly enabled by software through the EPINEN or EPOUTEN register, according to the configuration declared by the device and selected by the host through the SetConfig command.

A disabled data endpoint will not respond to any traffic from the host.

An enabled data endpoint will normally respond NAK or ACK (depending on the readiness of the buffers), or STALL if configured so through the EPSTALL register (in which case the endpoint is said to be halted).

The halted (or not) state of a given endpoint can be read back from the HALTED.EPIN[n] or HALTED.EPOUT[n] register. The format of the returned 16 bit value can be copied as is as response to a GetStatusEndpoint request from the host.

Note that enabling or disabling an endpoint will not change its halted state. However, a USB reset will disable and clear the halted state of all data endpoints.

The control endpoint 0 IN and OUT can also get enabled and/or halted through the same mechanisms, but due to USB specification, receiving a SETUP will override its state.

Bulk and interrupt IN transaction

The host issues IN tokens to receive bulk/interrupt data. In order to send data, the software has to enable the endpoint and prepare an EasyDMA transfer on the desired endpoint, as illustrated below.

Bulk/interrupt IN endpoints are enabled or disabled through their respective INn bit (n=1..7) in EPINEN register.

It is also possible to stall or un-stall an endpoint through the EPSTALL register.

Figure 9. Bulk/interrupt IN transaction

It is possible (and some situations mandate it) to respond to an IN with a zero-length data packet.

Note: on many USB hosts, not responding (DATA+ACK or NAK) to three IN tokens on a interrupt endpoint would have the host disable that endpoint as a consequence. Re-enumerating the device (unplug-replug) may be required to restore functionality. Make sure the relevant data endpoints are enabled for normal operation as soon as the device gets configured through a SetConfig request.

Bulk and interrupt OUT transaction

When the host wants to transmit bulk/interrupt data, it issues an OUT Token packet followed by a DATA packet on a given endpoint n.

A NAK handshake is returned until the software writes any value to SIZE.EPOUT[n], indicating that the local buffer's content can be overwritten. Upon receiving the next OUT + DATA transaction, an ACK handshake is returned to the host while a EPDATA event is sent (and EPSTATUS register flags set to indicate on which endpoint this happened), and once the EasyDMA is prepared and enabled through writing the EPOUT[n] registers and sending the STARTEPOUT[n] task, the incoming data will be transferred to Data RAM. Until that transfer is finished, the hardware will automatically NAK further incoming OUT+DATA packets. Only when the EasyDMA transfer is done (signalled by the ENDEPOUT[n] event) and the software has written any value to SIZE.EPOUT[n], the endpoint n will accept incoming OUT + DATA again.

It is allowed for the host to send out a zero-length data packet.

Bulk/interrupt OUT endpoints are enabled or disabled through their respective OUTn bit (n=1..7) in the EPOUTEN register. It is also possible to stall or un-stall an endpoint through the EPSTALL register.

Figure 10. Bulk/interrupt OUT transaction

Isochronous transactions

The USBD peripheral implements isochronous (iso) endpoints.

The iso endpoints have a fixed USB endpoint number, summarized in the table below.

Table 2. Isochronous endpoint numbering
Iso endpoint # USB IN endpoint USB OUT endpoint
[0] 0x88 0x08

A isochronous transaction consists of a single, non-acknowledged data stage. The host sends out a start of frame at a regular interval (1ms), and data follows IN or OUT tokens within each frame.

EasyDMA allows transferring iso data directly from and to Data RAM; EasyDMA transfers must be initiated by software, which can synchronize to the SOF events.

Because the timing of the start of frame is very accurate, the SOF event can be used for instance to synchronize a local timer through the SOF event and PPI. The SOF event gets synchronized to the 16 MHz clock prior to being made available to PPI.

Every Start of Frame increments a free-running counter, which can be read by software through the FRAMECNTR register.

Each IN or OUT iso data endpoint has to be explicitly enabled by software through the EPINEN or EPOUTEN register, according to the configuration declared by the device and selected by the host through the SetConfig command.

A disabled iso IN data endpoint will not respond to any traffic from the host.

A disabled iso OUT data endpoint will ignore any incoming traffic from the host.

The USBD peripheral has an internal 1 kByte buffer associated with iso endpoints. The user can either allocate the full amount to the IN or the OUT endpoint, or split the buffer allocation between the two. This is done through the ISOSPLIT register, which provides a number of pre-determined splits.

Isochronous IN transaction

When the host wants to receive isochronous (iso) data, it issues an IN token on the isochronous endpoint.

On the isochronous IN endpoint, after the data has been transferred using the EasyDMA, the USB controller responds to the IN token with the data that had been transferred, using the ISOIN.MAXCNT for the size of the packet.

The iso IN data endpoint has to be explicitly enabled by software through the ISOIN0 bit in the EPINEN register.

When the iso IN endpoint is enabled, and if no data had been transferred with EasyDMA, the response of the USBD depends on the setting of the RESPONSE field in the ISOINCONFIG register. If set to NoResp, no response to an IN token will be provided. If set to ZeroData, the USBD responds with a zero-length data.

Note: the maximum size of an isochronous IN transfer in USB Full Speed is 1023 Bytes, and the data buffer in RAM has to be a multiple of 4 bytes, and be 32-bit aligned in Data RAM. However, the amount of bytes transferred on the USB data endpoint can be of any size (up to 1023 Byte if not shared with an OUT iso endpoint).

Figure 11. Isochronous IN transfer

Isochronous OUT transaction

When the host wants to send isochronous (iso) data, it issues an OUT token on the isochronous endpoint, followed by data.

The iso OUT data endpoint has to be explicitly enabled by software through the ISOOUT0 bit in the EPOUTEN register.

The amount of last received iso OUT data is provided in the SIZE.ISOOUT register.

Software shall interpret the ZERO and SIZE fields as follows:

Table 3. Iso OUT incoming data size
ZERO SIZE last received data size
Normal 0 No data received at all
Normal 1..1023 1..1023 bytes of data received
ZeroData (don't care) Zero-length data packet received

When the EasyDMA is prepared and started, sending a STARTISOOUT task initiates an EasyDMA transfer to Data RAM. Software shall synchronize iso OUT transfers to the SOF events. If OUT data is not consumed and processed until next SOF, it will be overwritten by more recent data.

EasyDMA uses the address in ISOOUT.PTR and size in ISOOUT.MAXCNT for every new transfer.

Note: the maximum size of an isochronous OUT transfer in USB Full Speed is 1023 Bytes, and the data buffer in RAM has to be a multiple of 4 bytes, and be 32-bit aligned in Data RAM. However, the amount of bytes transferred on the USB data endpoint can be of any size (up to 1023 Byte if not shared with an IN iso endpoint).

If the last received iso data packet is corrupted (wrong CRC), the USB controller sends an USBEVENT event (at the same time as SOF) and indicates a CRC error on ISOOUTCRC in the EVENTCAUSE register. EasyDMA will transfer the data anyway if it has been set up properly.

Figure 12. Isochronous OUT transfer

USB register access limitations

Some of the registers in USBD cannot get accessed in specific conditions.

This is the case while USBD is not enabled (through the ENABLE register) and ready (signalled by the READY bit in EVENTCAUSE after the USBEVENT event), or when USBD has been placed in low power while the USB bus is suspended.

If any of the register listed below gets accessed (read or write) by software of through the debugger, an ACCESSFAULT event will get fired, and if the associated interrupt has been enabled through the INTEN or INTENSET register in USBD, an interrupt will be taken.

Following registers are affected by this behaviour:
  • firing any task, including through PPI
  • BUSSTATE
  • HALTED.EPIN[0..7]
  • HALTED.EPOUT[0..7]
  • USBADDR
  • BMREQUESTTYPE
  • BREQUEST
  • WVALUEL
  • WVALUEH
  • WINDEXL
  • WINDEXH
  • WLENGTHL
  • WLENGTHH
  • SIZE.EPOUT[0..7]
  • SIZE.ISOOUT
  • USBPULLUP
  • DTOGGLE
  • EPINEN
  • EPOUTEN
  • EPSTALL
  • ISOSPLIT
  • FRAMECNTR

Registers

Table 4. Instances
Base address Peripheral Instance Description Configuration
0x40027000 USBD USBD

Universal serial bus device

   
Table 5. Register Overview
Register Offset Description
TASKS_STARTEPIN[0] 0x004

Captures the EPIN[0].PTR, EPIN[0].MAXCNT and EPIN[0].CONFIG registers values, and enables endpoint IN 0 to respond to traffic from host

 
TASKS_STARTEPIN[1] 0x008

Captures the EPIN[1].PTR, EPIN[1].MAXCNT and EPIN[1].CONFIG registers values, and enables endpoint IN 1 to respond to traffic from host

 
TASKS_STARTEPIN[2] 0x00C

Captures the EPIN[2].PTR, EPIN[2].MAXCNT and EPIN[2].CONFIG registers values, and enables endpoint IN 2 to respond to traffic from host

 
TASKS_STARTEPIN[3] 0x010

Captures the EPIN[3].PTR, EPIN[3].MAXCNT and EPIN[3].CONFIG registers values, and enables endpoint IN 3 to respond to traffic from host

 
TASKS_STARTEPIN[4] 0x014

Captures the EPIN[4].PTR, EPIN[4].MAXCNT and EPIN[4].CONFIG registers values, and enables endpoint IN 4 to respond to traffic from host

 
TASKS_STARTEPIN[5] 0x018

Captures the EPIN[5].PTR, EPIN[5].MAXCNT and EPIN[5].CONFIG registers values, and enables endpoint IN 5 to respond to traffic from host

 
TASKS_STARTEPIN[6] 0x01C

Captures the EPIN[6].PTR, EPIN[6].MAXCNT and EPIN[6].CONFIG registers values, and enables endpoint IN 6 to respond to traffic from host

 
TASKS_STARTEPIN[7] 0x020

Captures the EPIN[7].PTR, EPIN[7].MAXCNT and EPIN[7].CONFIG registers values, and enables endpoint IN 7 to respond to traffic from host

 
TASKS_STARTISOIN 0x024

Captures the ISOIN.PTR, ISOIN.MAXCNT and ISOIN.CONFIG registers values, and enables sending data on iso endpoint

 
TASKS_STARTEPOUT[0] 0x028

Captures the EPOUT[0].PTR, EPOUT[0].MAXCNT and EPOUT[0].CONFIG registers values, and enables endpoint 0 to respond to traffic from host

 
TASKS_STARTEPOUT[1] 0x02C

Captures the EPOUT[1].PTR, EPOUT[1].MAXCNT and EPOUT[1].CONFIG registers values, and enables endpoint 1 to respond to traffic from host

 
TASKS_STARTEPOUT[2] 0x030

Captures the EPOUT[2].PTR, EPOUT[2].MAXCNT and EPOUT[2].CONFIG registers values, and enables endpoint 2 to respond to traffic from host

 
TASKS_STARTEPOUT[3] 0x034

Captures the EPOUT[3].PTR, EPOUT[3].MAXCNT and EPOUT[3].CONFIG registers values, and enables endpoint 3 to respond to traffic from host

 
TASKS_STARTEPOUT[4] 0x038

Captures the EPOUT[4].PTR, EPOUT[4].MAXCNT and EPOUT[4].CONFIG registers values, and enables endpoint 4 to respond to traffic from host

 
TASKS_STARTEPOUT[5] 0x03C

Captures the EPOUT[5].PTR, EPOUT[5].MAXCNT and EPOUT[5].CONFIG registers values, and enables endpoint 5 to respond to traffic from host

 
TASKS_STARTEPOUT[6] 0x040

Captures the EPOUT[6].PTR, EPOUT[6].MAXCNT and EPOUT[6].CONFIG registers values, and enables endpoint 6 to respond to traffic from host

 
TASKS_STARTEPOUT[7] 0x044

Captures the EPOUT[7].PTR, EPOUT[7].MAXCNT and EPOUT[7].CONFIG registers values, and enables endpoint 7 to respond to traffic from host

 
TASKS_STARTISOOUT 0x048

Captures the ISOOUT.PTR, ISOOUT.MAXCNT and ISOOUT.CONFIG registers values, and enables receiving of data on iso endpoint

 
TASKS_EP0RCVOUT 0x04C

Allows OUT data stage on control endpoint 0

 
TASKS_EP0STATUS 0x050

Allows status stage on control endpoint 0

 
TASKS_EP0STALL 0x054

STALLs data and status stage on control endpoint 0

 
TASKS_DPDMDRIVE 0x058

Forces D+ and D-lines to the state defined in the DPDMVALUE register

 
TASKS_DPDMNODRIVE 0x05C

Stops forcing D+ and D- lines to any state (USB engine takes control)

 
EVENTS_USBRESET 0x100

Signals that a USB reset condition has been detected on the USB lines

 
EVENTS_STARTED 0x104

Confirms that the EPIN[n].PTR, EPIN[n].MAXCNT, EPIN[n].CONFIG, or EPOUT[n].PTR, EPOUT[n].MAXCNT and EPOUT[n].CONFIG registers have been captured on all endpoints reported in the EPSTATUS register

 
EVENTS_ENDEPIN[0] 0x108

The whole EPIN[0] buffer has been consumed. The RAM buffer can be accessed safely by software.

 
EVENTS_ENDEPIN[1] 0x10C

The whole EPIN[1] buffer has been consumed. The RAM buffer can be accessed safely by software.

 
EVENTS_ENDEPIN[2] 0x110

The whole EPIN[2] buffer has been consumed. The RAM buffer can be accessed safely by software.

 
EVENTS_ENDEPIN[3] 0x114

The whole EPIN[3] buffer has been consumed. The RAM buffer can be accessed safely by software.

 
EVENTS_ENDEPIN[4] 0x118

The whole EPIN[4] buffer has been consumed. The RAM buffer can be accessed safely by software.

 
EVENTS_ENDEPIN[5] 0x11C

The whole EPIN[5] buffer has been consumed. The RAM buffer can be accessed safely by software.

 
EVENTS_ENDEPIN[6] 0x120

The whole EPIN[6] buffer has been consumed. The RAM buffer can be accessed safely by software.

 
EVENTS_ENDEPIN[7] 0x124

The whole EPIN[7] buffer has been consumed. The RAM buffer can be accessed safely by software.

 
EVENTS_EP0DATADONE 0x128

An acknowledged data transfer has taken place on the control endpoint

 
EVENTS_ENDISOIN 0x12C

The whole ISOIN buffer has been consumed. The RAM buffer can be accessed safely by software.

 
EVENTS_ENDEPOUT[0] 0x130

The whole EPOUT[0] buffer has been consumed. The RAM buffer can be accessed safely by software.

 
EVENTS_ENDEPOUT[1] 0x134

The whole EPOUT[1] buffer has been consumed. The RAM buffer can be accessed safely by software.

 
EVENTS_ENDEPOUT[2] 0x138

The whole EPOUT[2] buffer has been consumed. The RAM buffer can be accessed safely by software.

 
EVENTS_ENDEPOUT[3] 0x13C

The whole EPOUT[3] buffer has been consumed. The RAM buffer can be accessed safely by software.

 
EVENTS_ENDEPOUT[4] 0x140

The whole EPOUT[4] buffer has been consumed. The RAM buffer can be accessed safely by software.

 
EVENTS_ENDEPOUT[5] 0x144

The whole EPOUT[5] buffer has been consumed. The RAM buffer can be accessed safely by software.

 
EVENTS_ENDEPOUT[6] 0x148

The whole EPOUT[6] buffer has been consumed. The RAM buffer can be accessed safely by software.

 
EVENTS_ENDEPOUT[7] 0x14C

The whole EPOUT[7] buffer has been consumed. The RAM buffer can be accessed safely by software.

 
EVENTS_ENDISOOUT 0x150

The whole ISOOUT buffer has been consumed. The RAM buffer can be accessed safely by software.

 
EVENTS_SOF 0x154

Signals that a SOF (start of frame) condition has been detected on the USB lines

 
EVENTS_USBEVENT 0x158

An event or an error not covered by specific events has occurred, check EVENTCAUSE register to find the cause

 
EVENTS_EP0SETUP 0x15C

A valid SETUP token has been received (and acknowledged) on the control endpoint

 
EVENTS_EPDATA 0x160

A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register

 
EVENTS_ACCESSFAULT 0x164

Access to an unavailable USB register has been attempted (software or EasyDMA). This event can get fired even when USBD is not ENABLEd.

 
SHORTS 0x200

Shortcut register

 
INTEN 0x300

Enable or disable interrupt

 
INTENSET 0x304

Enable interrupt

 
INTENCLR 0x308

Disable interrupt

 
EVENTCAUSE 0x400

Details on event that caused the USBEVENT event

 
BUSSTATE 0x404

Provides the logic state of the D+ and D- lines

 
HALTED.EPIN[0] 0x420

IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint.

 
HALTED.EPIN[1] 0x424

IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint.

 
HALTED.EPIN[2] 0x428

IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint.

 
HALTED.EPIN[3] 0x42C

IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint.

 
HALTED.EPIN[4] 0x430

IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint.

 
HALTED.EPIN[5] 0x434

IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint.

 
HALTED.EPIN[6] 0x438

IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint.

 
HALTED.EPIN[7] 0x43C

IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint.

 
HALTED.EPOUT[0] 0x444

OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint.

 
HALTED.EPOUT[1] 0x448

OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint.

 
HALTED.EPOUT[2] 0x44C

OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint.

 
HALTED.EPOUT[3] 0x450

OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint.

 
HALTED.EPOUT[4] 0x454

OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint.

 
HALTED.EPOUT[5] 0x458

OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint.

 
HALTED.EPOUT[6] 0x45C

OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint.

 
HALTED.EPOUT[7] 0x460

OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint.

 
EPSTATUS 0x468

Provides information on which endpoint's EasyDMA registers have been captured

 
EPDATASTATUS 0x46C

Provides information on which endpoint(s) an acknowledged data transfer has occurred (EPDATA event)

 
USBADDR 0x470

Device USB address

 
BMREQUESTTYPE 0x480

SETUP data, byte 0, bmRequestType

 
BREQUEST 0x484

SETUP data, byte 1, bRequest

 
WVALUEL 0x488

SETUP data, byte 2, LSB of wValue

 
WVALUEH 0x48C

SETUP data, byte 3, MSB of wValue

 
WINDEXL 0x490

SETUP data, byte 4, LSB of wIndex

 
WINDEXH 0x494

SETUP data, byte 5, MSB of wIndex

 
WLENGTHL 0x498

SETUP data, byte 6, LSB of wLength

 
WLENGTHH 0x49C

SETUP data, byte 7, MSB of wLength

 
SIZE.EPOUT[0] 0x4A0

Amount of bytes received last in the data stage of this OUT endpoint

 
SIZE.EPOUT[1] 0x4A4

Amount of bytes received last in the data stage of this OUT endpoint

 
SIZE.EPOUT[2] 0x4A8

Amount of bytes received last in the data stage of this OUT endpoint

 
SIZE.EPOUT[3] 0x4AC

Amount of bytes received last in the data stage of this OUT endpoint

 
SIZE.EPOUT[4] 0x4B0

Amount of bytes received last in the data stage of this OUT endpoint

 
SIZE.EPOUT[5] 0x4B4

Amount of bytes received last in the data stage of this OUT endpoint

 
SIZE.EPOUT[6] 0x4B8

Amount of bytes received last in the data stage of this OUT endpoint

 
SIZE.EPOUT[7] 0x4BC

Amount of bytes received last in the data stage of this OUT endpoint

 
SIZE.ISOOUT 0x4C0

Amount of bytes received last on this iso OUT data endpoint

 
ENABLE 0x500

Enable USB

 
USBPULLUP 0x504

Control of the USB pull-up

 
DPDMVALUE 0x508

State at which the DPDMDRIVE task will force D+ and D-. The DPDMNODRIVE task reverts the control of the lines to MAC IP (no forcing).

 
DTOGGLE 0x50C

Data toggle control and status.

 
EPINEN 0x510

Endpoint IN enable

 
EPOUTEN 0x514

Endpoint OUT enable

 
EPSTALL 0x518

STALL endpoints

 
ISOSPLIT 0x51C

Controls the split of ISO buffers

 
FRAMECNTR 0x520

Returns the current value of the start of frame counter

 
LOWPOWER 0x52C

Controls USBD peripheral low-power mode during USB suspend

 
ISOINCONFIG 0x530

Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent

 
EPIN[0].PTR 0x600

Data pointer

 
EPIN[0].MAXCNT 0x604

Maximum number of bytes to transfer

 
EPIN[0].AMOUNT 0x608

Number of bytes transferred in the last transaction

 
EPIN[1].PTR 0x614

Data pointer

 
EPIN[1].MAXCNT 0x618

Maximum number of bytes to transfer

 
EPIN[1].AMOUNT 0x61C

Number of bytes transferred in the last transaction

 
EPIN[2].PTR 0x628

Data pointer

 
EPIN[2].MAXCNT 0x62C

Maximum number of bytes to transfer

 
EPIN[2].AMOUNT 0x630

Number of bytes transferred in the last transaction

 
EPIN[3].PTR 0x63C

Data pointer

 
EPIN[3].MAXCNT 0x640

Maximum number of bytes to transfer

 
EPIN[3].AMOUNT 0x644

Number of bytes transferred in the last transaction

 
EPIN[4].PTR 0x650

Data pointer

 
EPIN[4].MAXCNT 0x654

Maximum number of bytes to transfer

 
EPIN[4].AMOUNT 0x658

Number of bytes transferred in the last transaction

 
EPIN[5].PTR 0x664

Data pointer

 
EPIN[5].MAXCNT 0x668

Maximum number of bytes to transfer

 
EPIN[5].AMOUNT 0x66C

Number of bytes transferred in the last transaction

 
EPIN[6].PTR 0x678

Data pointer

 
EPIN[6].MAXCNT 0x67C

Maximum number of bytes to transfer

 
EPIN[6].AMOUNT 0x680

Number of bytes transferred in the last transaction

 
EPIN[7].PTR 0x68C

Data pointer

 
EPIN[7].MAXCNT 0x690

Maximum number of bytes to transfer

 
EPIN[7].AMOUNT 0x694

Number of bytes transferred in the last transaction

 
ISOIN.PTR 0x6A0

Data pointer

 
ISOIN.MAXCNT 0x6A4

Maximum number of bytes to transfer

 
ISOIN.AMOUNT 0x6A8

Number of bytes transferred in the last transaction

 
EPOUT[0].PTR 0x700

Data pointer

 
EPOUT[0].MAXCNT 0x704

Maximum number of bytes to transfer

 
EPOUT[0].AMOUNT 0x708

Number of bytes transferred in the last transaction

 
EPOUT[1].PTR 0x714

Data pointer

 
EPOUT[1].MAXCNT 0x718

Maximum number of bytes to transfer

 
EPOUT[1].AMOUNT 0x71C

Number of bytes transferred in the last transaction

 
EPOUT[2].PTR 0x728

Data pointer

 
EPOUT[2].MAXCNT 0x72C

Maximum number of bytes to transfer

 
EPOUT[2].AMOUNT 0x730

Number of bytes transferred in the last transaction

 
EPOUT[3].PTR 0x73C

Data pointer

 
EPOUT[3].MAXCNT 0x740

Maximum number of bytes to transfer

 
EPOUT[3].AMOUNT 0x744

Number of bytes transferred in the last transaction

 
EPOUT[4].PTR 0x750

Data pointer

 
EPOUT[4].MAXCNT 0x754

Maximum number of bytes to transfer

 
EPOUT[4].AMOUNT 0x758

Number of bytes transferred in the last transaction

 
EPOUT[5].PTR 0x764

Data pointer

 
EPOUT[5].MAXCNT 0x768

Maximum number of bytes to transfer

 
EPOUT[5].AMOUNT 0x76C

Number of bytes transferred in the last transaction

 
EPOUT[6].PTR 0x778

Data pointer

 
EPOUT[6].MAXCNT 0x77C

Maximum number of bytes to transfer

 
EPOUT[6].AMOUNT 0x780

Number of bytes transferred in the last transaction

 
EPOUT[7].PTR 0x78C

Data pointer

 
EPOUT[7].MAXCNT 0x790

Maximum number of bytes to transfer

 
EPOUT[7].AMOUNT 0x794

Number of bytes transferred in the last transaction

 
ISOOUT.PTR 0x7A0

Data pointer

 
ISOOUT.MAXCNT 0x7A4

Maximum number of bytes to transfer

 
ISOOUT.AMOUNT 0x7A8

Number of bytes transferred in the last transaction

 

SHORTS

Address offset: 0x200

Shortcut register

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                               E D C B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

EP0DATADONE_STARTEPIN0

   

Shortcut between EP0DATADONE event and STARTEPIN[0] task

See EVENTS_EP0DATADONE and TASKS_STARTEPIN[0]

     

Disabled

0

Disable shortcut

     

Enabled

1

Enable shortcut

B RW

EP0DATADONE_STARTEPOUT0

   

Shortcut between EP0DATADONE event and STARTEPOUT[0] task

See EVENTS_EP0DATADONE and TASKS_STARTEPOUT[0]

     

Disabled

0

Disable shortcut

     

Enabled

1

Enable shortcut

C RW

EP0DATADONE_EP0STATUS

   

Shortcut between EP0DATADONE event and EP0STATUS task

See EVENTS_EP0DATADONE and TASKS_EP0STATUS

     

Disabled

0

Disable shortcut

     

Enabled

1

Enable shortcut

D RW

ENDEPOUT0_EP0STATUS

   

Shortcut between ENDEPOUT[0] event and EP0STATUS task

See EVENTS_ENDEPOUT[0] and TASKS_EP0STATUS

     

Disabled

0

Disable shortcut

     

Enabled

1

Enable shortcut

E RW

ENDEPOUT0_EP0RCVOUT

   

Shortcut between ENDEPOUT[0] event and EP0RCVOUT task

See EVENTS_ENDEPOUT[0] and TASKS_EP0RCVOUT

     

Disabled

0

Disable shortcut

     

Enabled

1

Enable shortcut

 

INTEN

Address offset: 0x300

Enable or disable interrupt

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id             Z Y X W V U T S R Q P O N M L K J I H G F E D C B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

USBRESET

   

Enable or disable interrupt for USBRESET event

See EVENTS_USBRESET

     

Disabled

0

Disable

     

Enabled

1

Enable

B RW

STARTED

   

Enable or disable interrupt for STARTED event

See EVENTS_STARTED

     

Disabled

0

Disable

     

Enabled

1

Enable

C RW

ENDEPIN0

   

Enable or disable interrupt for ENDEPIN[0] event

See EVENTS_ENDEPIN[0]

     

Disabled

0

Disable

     

Enabled

1

Enable

D RW

ENDEPIN1

   

Enable or disable interrupt for ENDEPIN[1] event

See EVENTS_ENDEPIN[1]

     

Disabled

0

Disable

     

Enabled

1

Enable

E RW

ENDEPIN2

   

Enable or disable interrupt for ENDEPIN[2] event

See EVENTS_ENDEPIN[2]

     

Disabled

0

Disable

     

Enabled

1

Enable

F RW

ENDEPIN3

   

Enable or disable interrupt for ENDEPIN[3] event

See EVENTS_ENDEPIN[3]

     

Disabled

0

Disable

     

Enabled

1

Enable

G RW

ENDEPIN4

   

Enable or disable interrupt for ENDEPIN[4] event

See EVENTS_ENDEPIN[4]

     

Disabled

0

Disable

     

Enabled

1

Enable

H RW

ENDEPIN5

   

Enable or disable interrupt for ENDEPIN[5] event

See EVENTS_ENDEPIN[5]

     

Disabled

0

Disable

     

Enabled

1

Enable

I RW

ENDEPIN6

   

Enable or disable interrupt for ENDEPIN[6] event

See EVENTS_ENDEPIN[6]

     

Disabled

0

Disable

     

Enabled

1

Enable

J RW

ENDEPIN7

   

Enable or disable interrupt for ENDEPIN[7] event

See EVENTS_ENDEPIN[7]

     

Disabled

0

Disable

     

Enabled

1

Enable

K RW

EP0DATADONE

   

Enable or disable interrupt for EP0DATADONE event

See EVENTS_EP0DATADONE

     

Disabled

0

Disable

     

Enabled

1

Enable

L RW

ENDISOIN

   

Enable or disable interrupt for ENDISOIN event

See EVENTS_ENDISOIN

     

Disabled

0

Disable

     

Enabled

1

Enable

M RW

ENDEPOUT0

   

Enable or disable interrupt for ENDEPOUT[0] event

See EVENTS_ENDEPOUT[0]

     

Disabled

0

Disable

     

Enabled

1

Enable

N RW

ENDEPOUT1

   

Enable or disable interrupt for ENDEPOUT[1] event

See EVENTS_ENDEPOUT[1]

     

Disabled

0

Disable

     

Enabled

1

Enable

O RW

ENDEPOUT2

   

Enable or disable interrupt for ENDEPOUT[2] event

See EVENTS_ENDEPOUT[2]

     

Disabled

0

Disable

     

Enabled

1

Enable

P RW

ENDEPOUT3

   

Enable or disable interrupt for ENDEPOUT[3] event

See EVENTS_ENDEPOUT[3]

     

Disabled

0

Disable

     

Enabled

1

Enable

Q RW

ENDEPOUT4

   

Enable or disable interrupt for ENDEPOUT[4] event

See EVENTS_ENDEPOUT[4]

     

Disabled

0

Disable

     

Enabled

1

Enable

R RW

ENDEPOUT5

   

Enable or disable interrupt for ENDEPOUT[5] event

See EVENTS_ENDEPOUT[5]

     

Disabled

0

Disable

     

Enabled

1

Enable

S RW

ENDEPOUT6

   

Enable or disable interrupt for ENDEPOUT[6] event

See EVENTS_ENDEPOUT[6]

     

Disabled

0

Disable

     

Enabled

1

Enable

T RW

ENDEPOUT7

   

Enable or disable interrupt for ENDEPOUT[7] event

See EVENTS_ENDEPOUT[7]

     

Disabled

0

Disable

     

Enabled

1

Enable

U RW

ENDISOOUT

   

Enable or disable interrupt for ENDISOOUT event

See EVENTS_ENDISOOUT

     

Disabled

0

Disable

     

Enabled

1

Enable

V RW

SOF

   

Enable or disable interrupt for SOF event

See EVENTS_SOF

     

Disabled

0

Disable

     

Enabled

1

Enable

W RW

USBEVENT

   

Enable or disable interrupt for USBEVENT event

See EVENTS_USBEVENT

     

Disabled

0

Disable

     

Enabled

1

Enable

X RW

EP0SETUP

   

Enable or disable interrupt for EP0SETUP event

See EVENTS_EP0SETUP

     

Disabled

0

Disable

     

Enabled

1

Enable

Y RW

EPDATA

   

Enable or disable interrupt for EPDATA event

See EVENTS_EPDATA

     

Disabled

0

Disable

     

Enabled

1

Enable

Z RW

ACCESSFAULT

   

Enable or disable interrupt for ACCESSFAULT event

See EVENTS_ACCESSFAULT

     

Disabled

0

Disable

     

Enabled

1

Enable

 

INTENSET

Address offset: 0x304

Enable interrupt

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id             Z Y X W V U T S R Q P O N M L K J I H G F E D C B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

USBRESET

   

Write '1' to Enable interrupt for USBRESET event

See EVENTS_USBRESET

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

B RW

STARTED

   

Write '1' to Enable interrupt for STARTED event

See EVENTS_STARTED

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

C RW

ENDEPIN0

   

Write '1' to Enable interrupt for ENDEPIN[0] event

See EVENTS_ENDEPIN[0]

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

D RW

ENDEPIN1

   

Write '1' to Enable interrupt for ENDEPIN[1] event

See EVENTS_ENDEPIN[1]

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

E RW

ENDEPIN2

   

Write '1' to Enable interrupt for ENDEPIN[2] event

See EVENTS_ENDEPIN[2]

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

F RW

ENDEPIN3

   

Write '1' to Enable interrupt for ENDEPIN[3] event

See EVENTS_ENDEPIN[3]

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

G RW

ENDEPIN4

   

Write '1' to Enable interrupt for ENDEPIN[4] event

See EVENTS_ENDEPIN[4]

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

H RW

ENDEPIN5

   

Write '1' to Enable interrupt for ENDEPIN[5] event

See EVENTS_ENDEPIN[5]

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

I RW

ENDEPIN6

   

Write '1' to Enable interrupt for ENDEPIN[6] event

See EVENTS_ENDEPIN[6]

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

J RW

ENDEPIN7

   

Write '1' to Enable interrupt for ENDEPIN[7] event

See EVENTS_ENDEPIN[7]

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

K RW

EP0DATADONE

   

Write '1' to Enable interrupt for EP0DATADONE event

See EVENTS_EP0DATADONE

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

L RW

ENDISOIN

   

Write '1' to Enable interrupt for ENDISOIN event

See EVENTS_ENDISOIN

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

M RW

ENDEPOUT0

   

Write '1' to Enable interrupt for ENDEPOUT[0] event

See EVENTS_ENDEPOUT[0]

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

N RW

ENDEPOUT1

   

Write '1' to Enable interrupt for ENDEPOUT[1] event

See EVENTS_ENDEPOUT[1]

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

O RW

ENDEPOUT2

   

Write '1' to Enable interrupt for ENDEPOUT[2] event

See EVENTS_ENDEPOUT[2]

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

P RW

ENDEPOUT3

   

Write '1' to Enable interrupt for ENDEPOUT[3] event

See EVENTS_ENDEPOUT[3]

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

Q RW

ENDEPOUT4

   

Write '1' to Enable interrupt for ENDEPOUT[4] event

See EVENTS_ENDEPOUT[4]

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

R RW

ENDEPOUT5

   

Write '1' to Enable interrupt for ENDEPOUT[5] event

See EVENTS_ENDEPOUT[5]

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

S RW

ENDEPOUT6

   

Write '1' to Enable interrupt for ENDEPOUT[6] event

See EVENTS_ENDEPOUT[6]

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

T RW

ENDEPOUT7

   

Write '1' to Enable interrupt for ENDEPOUT[7] event

See EVENTS_ENDEPOUT[7]

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

U RW

ENDISOOUT

   

Write '1' to Enable interrupt for ENDISOOUT event

See EVENTS_ENDISOOUT

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

V RW

SOF

   

Write '1' to Enable interrupt for SOF event

See EVENTS_SOF

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

W RW

USBEVENT

   

Write '1' to Enable interrupt for USBEVENT event

See EVENTS_USBEVENT

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

X RW

EP0SETUP

   

Write '1' to Enable interrupt for EP0SETUP event

See EVENTS_EP0SETUP

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

Y RW

EPDATA

   

Write '1' to Enable interrupt for EPDATA event

See EVENTS_EPDATA

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

Z RW

ACCESSFAULT

   

Write '1' to Enable interrupt for ACCESSFAULT event

See EVENTS_ACCESSFAULT

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

 

INTENCLR

Address offset: 0x308

Disable interrupt

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id             Z Y X W V U T S R Q P O N M L K J I H G F E D C B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

USBRESET

   

Write '1' to Disable interrupt for USBRESET event

See EVENTS_USBRESET

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

B RW

STARTED

   

Write '1' to Disable interrupt for STARTED event

See EVENTS_STARTED

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

C RW

ENDEPIN0

   

Write '1' to Disable interrupt for ENDEPIN[0] event

See EVENTS_ENDEPIN[0]

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

D RW

ENDEPIN1

   

Write '1' to Disable interrupt for ENDEPIN[1] event

See EVENTS_ENDEPIN[1]

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

E RW

ENDEPIN2

   

Write '1' to Disable interrupt for ENDEPIN[2] event

See EVENTS_ENDEPIN[2]

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

F RW

ENDEPIN3

   

Write '1' to Disable interrupt for ENDEPIN[3] event

See EVENTS_ENDEPIN[3]

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

G RW

ENDEPIN4

   

Write '1' to Disable interrupt for ENDEPIN[4] event

See EVENTS_ENDEPIN[4]

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

H RW

ENDEPIN5

   

Write '1' to Disable interrupt for ENDEPIN[5] event

See EVENTS_ENDEPIN[5]

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

I RW

ENDEPIN6

   

Write '1' to Disable interrupt for ENDEPIN[6] event

See EVENTS_ENDEPIN[6]

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

J RW

ENDEPIN7

   

Write '1' to Disable interrupt for ENDEPIN[7] event

See EVENTS_ENDEPIN[7]

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

K RW

EP0DATADONE

   

Write '1' to Disable interrupt for EP0DATADONE event

See EVENTS_EP0DATADONE

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

L RW

ENDISOIN

   

Write '1' to Disable interrupt for ENDISOIN event

See EVENTS_ENDISOIN

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

M RW

ENDEPOUT0

   

Write '1' to Disable interrupt for ENDEPOUT[0] event

See EVENTS_ENDEPOUT[0]

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

N RW

ENDEPOUT1

   

Write '1' to Disable interrupt for ENDEPOUT[1] event

See EVENTS_ENDEPOUT[1]

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

O RW

ENDEPOUT2

   

Write '1' to Disable interrupt for ENDEPOUT[2] event

See EVENTS_ENDEPOUT[2]

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

P RW

ENDEPOUT3

   

Write '1' to Disable interrupt for ENDEPOUT[3] event

See EVENTS_ENDEPOUT[3]

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

Q RW

ENDEPOUT4

   

Write '1' to Disable interrupt for ENDEPOUT[4] event

See EVENTS_ENDEPOUT[4]

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

R RW

ENDEPOUT5

   

Write '1' to Disable interrupt for ENDEPOUT[5] event

See EVENTS_ENDEPOUT[5]

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

S RW

ENDEPOUT6

   

Write '1' to Disable interrupt for ENDEPOUT[6] event

See EVENTS_ENDEPOUT[6]

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

T RW

ENDEPOUT7

   

Write '1' to Disable interrupt for ENDEPOUT[7] event

See EVENTS_ENDEPOUT[7]

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

U RW

ENDISOOUT

   

Write '1' to Disable interrupt for ENDISOOUT event

See EVENTS_ENDISOOUT

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

V RW

SOF

   

Write '1' to Disable interrupt for SOF event

See EVENTS_SOF

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

W RW

USBEVENT

   

Write '1' to Disable interrupt for USBEVENT event

See EVENTS_USBEVENT

     

Clear

1