SAADC — Successive approximation analog-to-digital converter

The SAADC is a differential successive approximation register (SAR) analog-to-digital converter. It supports up to eight external analog input channels, depending on package variant.

The following lists the main features of the SAADC:

Figure 1. Block diagram
Block diagram

An input channel is enabled and connected to an analog input pin using the registers CH[n].PSELP (n=0..7) and CH[n].PSELN (n=0..7).

Before any sampling can take place, the length and the location of the memory buffer in RAM where output values shall be written needs to be configured, and the START task has to be triggered to apply the configuration. See EasyDMA for details on memory configuration and how the results are placed in memory.

Sampling of a single channel is started by triggering the SAMPLE task, and the sample results are automatically written to memory using EasyDMA. A DONE event is generated for every single completed conversion, and an END event is generated when multiple samples, as specified in RESULT.MAXCNT, have been written to memory.

When multiple channels are enabled, they are sampled successively in a sequence and in circular order (lowest to highest channel number, and then from lowest again). The SAMPLE task needs to be triggered for every individual sample to be taken, for every channel.

Input configuration

Each SAADC channel can be configured to use either single-ended or differential input mode.

The configuration is done using the registers CH[n].CONFIG (n=0..7). In single-ended mode, the negative channel input is shorted to ground internally and the setting in the corresponding register CH[n].PSELN (n=0..7) will not apply. The assumption in single-ended mode is that the internal ground of the SAADC is the same as the external ground that the measured voltage is referred to. The SAADC is thus sensitive to ground bounce on the PCB in single-ended mode. If this is a concern, using differential measurement is recommended. In differential mode, both positive and negative input has to be configured in registersCH[n].PSELP (n=0..7) and CH[n].PSELN (n=0..7) respectively.

Acquisition time

To sample input voltage, the SAADC connects a capacitor to the input.

This is illustrated in the following figure:

Figure 2. Simplified SAADC sample network
Simplified SAADC sample network

The acquisition time indicates how long the capacitor is connected, see TACQ field in CH[n].CONFIG register. The required acquisition time depends on the source resistance (Rsource). For high source resistance the acquisition time should be increased:

Table 1. Acquisition time
TACQ [µs] Maximum source resistance [kΩ]
3 10
5 40
10 100
15 200
20 400
40 800

When using VDDHDIV5 as input, the acquisition time needs to be 10 µs or higher.

Internal resistor string (resistor ladder)

The SAADC has an internal resistor string for positive and negative input. The resistors are controlled in registers CH[n].CONFIG.RESP and CH[n].CONFIG.RESN.

The following figure illustrates the resistor ladder for positive (and negative) input:

Figure 3. Resistor ladder for positive input (negative input is equivalent, using RESN instead of RESP)
Resistor ladder for positive input (negative input is equivalent, using RESN instead of RESP

Reference voltage and gain settings

Each SAADC channel can have individual reference and gain settings.

This is configured in registers CH[n].CONFIG (n=0..7). Available configuration options are:

  • VDD/4 or internal 0.6 V reference
  • Gain ranging from 1/6 to 4

The gain setting can be used to control the effective input range of the SAADC:

Input range = (±0.6 V or ±VDD/4)/gain

For example, selecting VDD as reference, single-ended input (grounded negative input), and a gain of 1/4 will result in the following input range:

Input range = (VDD/4)/(1/4) = VDD

With internal reference, single-ended input (grounded negative input) and a gain of 1/6, the input range will be:

Input range = (0.6 V)/(1/6) = 3.6 V

Inputs AIN0 through AIN7 cannot exceed VDD or be lower than VSS.

Digital output

The digital output value from the SAADC is calculated using a formula.

RESULT = (V(P) – V(N)) * (GAIN/REFERENCE) * 2(RESOLUTION - m)

where

V(P)
is the voltage at input P
V(N)
is the voltage at input N
GAIN
is the selected gain
REFERENCE
is the selected reference voltage
RESOLUTION
is output resolution in bits, as configured in register RESOLUTION
m
is 0 for single-ended channels
is 1 for differential channels

Results are sign extended to 16 bits and stored as little-endian byte order in RAM.

EasyDMA

The SAADC resources are started by triggering the START task. The SAADC is using EasyDMA to store results in a result buffer in RAM.

Registers RESULT.PTR and RESULT.MAXCNT must be configured before SAADC is started.

The result buffer is located at the address specified in register RESULT.PTR. This register is double-buffered, and it can be updated and prepared for the next START task immediately after the STARTED event is generated. The size of the result buffer is specified in register RESULT.MAXCNT, and the SAADC will generate an END event when it has filled up the result buffer, as illustrated in the following figure:

Figure 4. SAADC
SAADC

The following figure shows how results are placed in RAM when multiple channels are enabled, and value in RESULT.MAXCNT is an even number:

Figure 5. Example of RAM placement: RESULT.MAXCNT even number, channels 1, 2 and 5 enabled
Example of RAM placement: RESULT.MAXCNT even number, channels 1, 2 and 5 enabled

The following figure shows how results are placed in RAM when multiple channels are enabled and value in RESULT.MAXCNT is an odd number:

Figure 6. Example of RAM placement: RESULT.MAXCNT odd number, channels 1, 2 and 5 enabled
Example of RAM placement: RESULT.MAXCNT odd number, channels 1, 2 and 5 enabled

The last 32-bit word is populated only with one 16-bit result. In both examples, channels 1, 2 and 5 are enabled, and all others are disabled.

See Memory for more information about the different memory regions.

EasyDMA is finished with accessing RAM when events END or STOPPED are generated. The register RESULT.AMOUNT can then be read, to see how many results have been transferred to the result buffer in RAM since the START task was triggered.

Continuous sampling

When using continuous sampling, new samples are automatically taken at a fixed sample rate.

Continuous sampling of both single and multiple channels can be implemented using a general purpose timer connecting a timer event to SAADC's SAMPLE task via PPI.

Alternatively, continuous sampling can be implemented by using the internal timer in the SAADC by setting the MODE field in register SAMPLERATE to Timers. The sample rate (frequency at which the SAMPLE task is triggered) is configured in the same register. The internal timer and the continuous sampling are started by triggering the START task and stopped using the STOP task.

Note: Note that the internal timer can only be used when a single input channel is enabled.

For continuous sampling, ensure that the sample rate fullfills the following criteria:

fSAMPLE < 1/[tACQ + tconv]

Oversampling

An accumulator in the SAADC can be used to find the average of several analog input samples. In general, oversampling improves the signal-to-noise ratio (SNR). Oversampling does not improve the integral non-linearity (INL) or differential non-linearity (DNL).

The accumulator is controlled in the OVERSAMPLE register. When using oversampling, 2OVERSAMPLE input samples are averaged before the sample result is transferred to memory. Hence, the SAMPLE task must be triggered 2OVERSAMPLE times for each output value. The following events are relevant:

  • DONE event is generated for every input sample taken
  • RESULTDONE event is generated for every averaged value ready to be transferred into RAM
  • END event is generated when averaged values defined in RESULT.MAXCNT have been written to memory. END event is generated every 2OVERSAMPLE time the DONE event is generated.

If value in OVERSAMPLE is set to 0, the DONE and RESULTDONE events will be generated at the same rate.

Note: Oversampling should only be used when a single input channel is enabled, as averaging is performed over all enabled channels.

Event monitoring using limits

A channel can be event monitored by using limits.

Limits are configured in CH[n].LIMIT register, with high limit and low limit.

Note: High limit shall always be higher than or equal to low limit.

Appropriate events are generated whenever the conversion results (sampled input signals) are outside of the two defined limits. It is not possible to generate an event when the input signal is inside a defined range by swapping high and low limits. An example of event montitoring using limits is illustrated in the following figure:

Figure 7. Example: Event monitoring on channel n using limits
Example: Event monitoring on channel n using limits

The comparison to limits always takes place, it does not need to be specifically enabled. If comparison is not required on a channel, the software ignores the related events. In that situation, the value of the limits defined in register is irrelevant, i.e. it does not matter if the low limit is lower than the high limit or not.

Calibration

The SAADC has a temperature dependent offset.

Therefore, it is recommended to calibrate the SAADC at least once before use, and to re-run calibration every time the ambient temperature has changed by more than 10 °C.

Offset calibration is started by triggering the CALIBRATEOFFSET task, and the CALIBRATEDONE event is generated when calibration is done.

Registers

Table 2. Instances
Base address Peripheral Instance Description Configuration
0x40007000 SAADC SAADC

Analog to digital converter

   
Table 3. Register overview
Register Offset Description
TASKS_START 0x000

Starts the SAADC and prepares the result buffer in RAM

 
TASKS_SAMPLE 0x004

Takes one SAADC sample

 
TASKS_STOP 0x008

Stops the SAADC and terminates all on-going conversions

 
TASKS_CALIBRATEOFFSET 0x00C

Starts offset auto-calibration

 
EVENTS_STARTED 0x100

The SAADC has started

 
EVENTS_END 0x104

The SAADC has filled up the result buffer

 
EVENTS_DONE 0x108

A conversion task has been completed. Depending on the configuration, multiple conversions might be needed for a result to be transferred to RAM.

 
EVENTS_RESULTDONE 0x10C

Result ready for transfer to RAM

 
EVENTS_CALIBRATEDONE 0x110

Calibration is complete

 
EVENTS_STOPPED 0x114

The SAADC has stopped

 
EVENTS_CH[0].LIMITH 0x118

Last result is equal or above CH[0].LIMIT.HIGH

 
EVENTS_CH[0].LIMITL 0x11C

Last result is equal or below CH[0].LIMIT.LOW

 
EVENTS_CH[1].LIMITH 0x120

Last result is equal or above CH[1].LIMIT.HIGH

 
EVENTS_CH[1].LIMITL 0x124

Last result is equal or below CH[1].LIMIT.LOW

 
EVENTS_CH[2].LIMITH 0x128

Last result is equal or above CH[2].LIMIT.HIGH

 
EVENTS_CH[2].LIMITL 0x12C

Last result is equal or below CH[2].LIMIT.LOW

 
EVENTS_CH[3].LIMITH 0x130

Last result is equal or above CH[3].LIMIT.HIGH

 
EVENTS_CH[3].LIMITL 0x134

Last result is equal or below CH[3].LIMIT.LOW

 
EVENTS_CH[4].LIMITH 0x138

Last result is equal or above CH[4].LIMIT.HIGH

 
EVENTS_CH[4].LIMITL 0x13C

Last result is equal or below CH[4].LIMIT.LOW

 
EVENTS_CH[5].LIMITH 0x140

Last result is equal or above CH[5].LIMIT.HIGH

 
EVENTS_CH[5].LIMITL 0x144

Last result is equal or below CH[5].LIMIT.LOW

 
EVENTS_CH[6].LIMITH 0x148

Last result is equal or above CH[6].LIMIT.HIGH

 
EVENTS_CH[6].LIMITL 0x14C

Last result is equal or below CH[6].LIMIT.LOW

 
EVENTS_CH[7].LIMITH 0x150

Last result is equal or above CH[7].LIMIT.HIGH

 
EVENTS_CH[7].LIMITL 0x154

Last result is equal or below CH[7].LIMIT.LOW

 
INTEN 0x300

Enable or disable interrupt

 
INTENSET 0x304

Enable interrupt

 
INTENCLR 0x308

Disable interrupt

 
STATUS 0x400

Status

 
ENABLE 0x500

Enable or disable SAADC

 
CH[0].PSELP 0x510

Input positive pin selection for CH[0]

 
CH[0].PSELN 0x514

Input negative pin selection for CH[0]

 
CH[0].CONFIG 0x518

Input configuration for CH[0]

 
CH[0].LIMIT 0x51C

High/low limits for event monitoring of a channel

 
CH[1].PSELP 0x520

Input positive pin selection for CH[1]

 
CH[1].PSELN 0x524

Input negative pin selection for CH[1]

 
CH[1].CONFIG 0x528

Input configuration for CH[1]

 
CH[1].LIMIT 0x52C

High/low limits for event monitoring of a channel

 
CH[2].PSELP 0x530

Input positive pin selection for CH[2]

 
CH[2].PSELN 0x534

Input negative pin selection for CH[2]

 
CH[2].CONFIG 0x538

Input configuration for CH[2]

 
CH[2].LIMIT 0x53C

High/low limits for event monitoring of a channel

 
CH[3].PSELP 0x540

Input positive pin selection for CH[3]

 
CH[3].PSELN 0x544

Input negative pin selection for CH[3]

 
CH[3].CONFIG 0x548

Input configuration for CH[3]

 
CH[3].LIMIT 0x54C

High/low limits for event monitoring of a channel

 
CH[4].PSELP 0x550

Input positive pin selection for CH[4]

 
CH[4].PSELN 0x554

Input negative pin selection for CH[4]

 
CH[4].CONFIG 0x558

Input configuration for CH[4]

 
CH[4].LIMIT 0x55C

High/low limits for event monitoring of a channel

 
CH[5].PSELP 0x560

Input positive pin selection for CH[5]

 
CH[5].PSELN 0x564

Input negative pin selection for CH[5]

 
CH[5].CONFIG 0x568

Input configuration for CH[5]

 
CH[5].LIMIT 0x56C

High/low limits for event monitoring of a channel

 
CH[6].PSELP 0x570

Input positive pin selection for CH[6]

 
CH[6].PSELN 0x574

Input negative pin selection for CH[6]

 
CH[6].CONFIG 0x578

Input configuration for CH[6]

 
CH[6].LIMIT 0x57C

High/low limits for event monitoring of a channel

 
CH[7].PSELP 0x580

Input positive pin selection for CH[7]

 
CH[7].PSELN 0x584

Input negative pin selection for CH[7]

 
CH[7].CONFIG 0x588

Input configuration for CH[7]

 
CH[7].LIMIT 0x58C

High/low limits for event monitoring of a channel

 
RESOLUTION 0x5F0

Resolution configuration

 
OVERSAMPLE 0x5F4

Oversampling configuration. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used.

 
SAMPLERATE 0x5F8

Controls normal or continuous sample rate

 
RESULT.PTR 0x62C

Data pointer

 
RESULT.MAXCNT 0x630

Maximum number of 16-bit samples to be written to output RAM buffer

 
RESULT.AMOUNT 0x634

Number of 16-bit samples written to output RAM buffer since the previous START task

 

INTEN

Address offset: 0x300

Enable or disable interrupt

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                     V U T S R Q P O N M L K J I H G F E D C B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID RW Field Value ID Value Description
A RW

STARTED

   

Enable or disable interrupt for STARTED event

See EVENTS_STARTED

     

Disabled

0

Disable

     

Enabled

1

Enable

B RW

END

   

Enable or disable interrupt for END event

See EVENTS_END

     

Disabled

0

Disable

     

Enabled

1

Enable

C RW

DONE

   

Enable or disable interrupt for DONE event

See EVENTS_DONE

     

Disabled

0

Disable

     

Enabled

1

Enable

D RW

RESULTDONE

   

Enable or disable interrupt for RESULTDONE event

See EVENTS_RESULTDONE

     

Disabled

0

Disable

     

Enabled

1

Enable

E RW

CALIBRATEDONE

   

Enable or disable interrupt for CALIBRATEDONE event

See EVENTS_CALIBRATEDONE

     

Disabled

0

Disable

     

Enabled

1

Enable

F RW

STOPPED

   

Enable or disable interrupt for STOPPED event

See EVENTS_STOPPED

     

Disabled

0

Disable

     

Enabled

1

Enable

G RW

CH0LIMITH

   

Enable or disable interrupt for CH[0].LIMITH event

See EVENTS_CH[0].LIMITH

     

Disabled

0

Disable

     

Enabled

1

Enable

H RW

CH0LIMITL

   

Enable or disable interrupt for CH[0].LIMITL event

See EVENTS_CH[0].LIMITL

     

Disabled

0

Disable

     

Enabled

1

Enable

I RW

CH1LIMITH

   

Enable or disable interrupt for CH[1].LIMITH event

See EVENTS_CH[1].LIMITH

     

Disabled

0

Disable

     

Enabled

1

Enable

J RW

CH1LIMITL

   

Enable or disable interrupt for CH[1].LIMITL event

See EVENTS_CH[1].LIMITL

     

Disabled

0

Disable

     

Enabled

1

Enable

K RW

CH2LIMITH

   

Enable or disable interrupt for CH[2].LIMITH event

See EVENTS_CH[2].LIMITH

     

Disabled

0

Disable

     

Enabled

1

Enable

L RW

CH2LIMITL

   

Enable or disable interrupt for CH[2].LIMITL event

See EVENTS_CH[2].LIMITL

     

Disabled

0

Disable

     

Enabled

1

Enable

M RW

CH3LIMITH

   

Enable or disable interrupt for CH[3].LIMITH event

See EVENTS_CH[3].LIMITH

     

Disabled

0

Disable

     

Enabled

1

Enable

N RW

CH3LIMITL

   

Enable or disable interrupt for CH[3].LIMITL event

See EVENTS_CH[3].LIMITL

     

Disabled

0

Disable

     

Enabled

1

Enable

O RW

CH4LIMITH

   

Enable or disable interrupt for CH[4].LIMITH event

See EVENTS_CH[4].LIMITH

     

Disabled

0

Disable

     

Enabled

1

Enable

P RW

CH4LIMITL

   

Enable or disable interrupt for CH[4].LIMITL event

See EVENTS_CH[4].LIMITL

     

Disabled

0

Disable

     

Enabled

1

Enable

Q RW

CH5LIMITH

   

Enable or disable interrupt for CH[5].LIMITH event

See EVENTS_CH[5].LIMITH

     

Disabled

0

Disable

     

Enabled

1

Enable

R RW

CH5LIMITL

   

Enable or disable interrupt for CH[5].LIMITL event

See EVENTS_CH[5].LIMITL

     

Disabled

0

Disable

     

Enabled

1

Enable

S RW

CH6LIMITH

   

Enable or disable interrupt for CH[6].LIMITH event

See EVENTS_CH[6].LIMITH

     

Disabled

0

Disable

     

Enabled

1

Enable

T RW

CH6LIMITL

   

Enable or disable interrupt for CH[6].LIMITL event

See EVENTS_CH[6].LIMITL

     

Disabled

0

Disable

     

Enabled

1

Enable

U RW

CH7LIMITH

   

Enable or disable interrupt for CH[7].LIMITH event

See EVENTS_CH[7].LIMITH

     

Disabled

0

Disable

     

Enabled

1

Enable

V RW

CH7LIMITL

   

Enable or disable interrupt for CH[7].LIMITL event

See EVENTS_CH[7].LIMITL

     

Disabled

0

Disable

     

Enabled

1

Enable

INTENSET

Address offset: 0x304

Enable interrupt

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                     V U T S R Q P O N M L K J I H G F E D C B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID RW Field Value ID Value Description
A RW

STARTED

   

Write '1' to enable interrupt for STARTED event

See EVENTS_STARTED

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

B RW

END

   

Write '1' to enable interrupt for END event

See EVENTS_END

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

C RW

DONE

   

Write '1' to enable interrupt for DONE event

See EVENTS_DONE

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

D RW

RESULTDONE

   

Write '1' to enable interrupt for RESULTDONE event

See EVENTS_RESULTDONE

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

E RW

CALIBRATEDONE

   

Write '1' to enable interrupt for CALIBRATEDONE event

See EVENTS_CALIBRATEDONE

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

F RW

STOPPED

   

Write '1' to enable interrupt for STOPPED event

See EVENTS_STOPPED

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

G RW

CH0LIMITH

   

Write '1' to enable interrupt for CH[0].LIMITH event

See EVENTS_CH[0].LIMITH

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

H RW

CH0LIMITL

   

Write '1' to enable interrupt for CH[0].LIMITL event

See EVENTS_CH[0].LIMITL

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

I RW

CH1LIMITH

   

Write '1' to enable interrupt for CH[1].LIMITH event

See EVENTS_CH[1].LIMITH

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

J RW

CH1LIMITL

   

Write '1' to enable interrupt for CH[1].LIMITL event

See EVENTS_CH[1].LIMITL

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

K RW

CH2LIMITH

   

Write '1' to enable interrupt for CH[2].LIMITH event

See EVENTS_CH[2].LIMITH

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

L RW

CH2LIMITL

   

Write '1' to enable interrupt for CH[2].LIMITL event

See EVENTS_CH[2].LIMITL

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

M RW

CH3LIMITH

   

Write '1' to enable interrupt for CH[3].LIMITH event

See EVENTS_CH[3].LIMITH

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

N RW

CH3LIMITL

   

Write '1' to enable interrupt for CH[3].LIMITL event

See EVENTS_CH[3].LIMITL

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

O RW

CH4LIMITH

   

Write '1' to enable interrupt for CH[4].LIMITH event

See EVENTS_CH[4].LIMITH

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

P RW

CH4LIMITL

   

Write '1' to enable interrupt for CH[4].LIMITL event

See EVENTS_CH[4].LIMITL

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

Q RW

CH5LIMITH

   

Write '1' to enable interrupt for CH[5].LIMITH event

See EVENTS_CH[5].LIMITH

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

R RW

CH5LIMITL

   

Write '1' to enable interrupt for CH[5].LIMITL event

See EVENTS_CH[5].LIMITL

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

S RW

CH6LIMITH

   

Write '1' to enable interrupt for CH[6].LIMITH event

See EVENTS_CH[6].LIMITH

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

T RW

CH6LIMITL

   

Write '1' to enable interrupt for CH[6].LIMITL event

See EVENTS_CH[6].LIMITL

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

U RW

CH7LIMITH

   

Write '1' to enable interrupt for CH[7].LIMITH event

See EVENTS_CH[7].LIMITH

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

V RW

CH7LIMITL

   

Write '1' to enable interrupt for CH[7].LIMITL event

See EVENTS_CH[7].LIMITL

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

INTENCLR

Address offset: 0x308

Disable interrupt

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                     V U T S R Q P O N M L K J I H G F E D C B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID RW Field Value ID Value Description
A RW

STARTED

   

Write '1' to disable interrupt for STARTED event

See EVENTS_STARTED

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

B RW

END

   

Write '1' to disable interrupt for END event

See EVENTS_END

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

C RW

DONE

   

Write '1' to disable interrupt for DONE event

See EVENTS_DONE

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

D RW

RESULTDONE

   

Write '1' to disable interrupt for RESULTDONE event

See EVENTS_RESULTDONE

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

E RW

CALIBRATEDONE

   

Write '1' to disable interrupt for CALIBRATEDONE event

See EVENTS_CALIBRATEDONE

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

F RW

STOPPED

   

Write '1' to disable interrupt for STOPPED event

See EVENTS_STOPPED

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

G RW

CH0LIMITH

   

Write '1' to disable interrupt for CH[0].LIMITH event

See EVENTS_CH[0].LIMITH

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

H RW

CH0LIMITL

   

Write '1' to disable interrupt for CH[0].LIMITL event

See EVENTS_CH[0].LIMITL

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

I RW

CH1LIMITH

   

Write '1' to disable interrupt for CH[1].LIMITH event

See EVENTS_CH[1].LIMITH

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

J RW

CH1LIMITL

   

Write '1' to disable interrupt for CH[1].LIMITL event

See EVENTS_CH[1].LIMITL

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

K RW

CH2LIMITH

   

Write '1' to disable interrupt for CH[2].LIMITH event

See EVENTS_CH[2].LIMITH

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

L RW

CH2LIMITL

   

Write '1' to disable interrupt for CH[2].LIMITL event

See EVENTS_CH[2].LIMITL

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

M RW

CH3LIMITH

   

Write '1' to disable interrupt for CH[3].LIMITH event

See EVENTS_CH[3].LIMITH

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

N RW

CH3LIMITL

   

Write '1' to disable interrupt for CH[3].LIMITL event

See EVENTS_CH[3].LIMITL

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

O RW

CH4LIMITH

   

Write '1' to disable interrupt for CH[4].LIMITH event

See EVENTS_CH[4].LIMITH

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

P RW

CH4LIMITL

   

Write '1' to disable interrupt for CH[4].LIMITL event

See EVENTS_CH[4].LIMITL

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

Q RW

CH5LIMITH

   

Write '1' to disable interrupt for CH[5].LIMITH event

See EVENTS_CH[5].LIMITH

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

R RW

CH5LIMITL

   

Write '1' to disable interrupt for CH[5].LIMITL event

See EVENTS_CH[5].LIMITL

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

S RW

CH6LIMITH

   

Write '1' to disable interrupt for CH[6].LIMITH event

See EVENTS_CH[6].LIMITH

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

T RW

CH6LIMITL

   

Write '1' to disable interrupt for CH[6].LIMITL event

See EVENTS_CH[6].LIMITL

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

U RW

CH7LIMITH

   

Write '1' to disable interrupt for CH[7].LIMITH event

See EVENTS_CH[7].LIMITH

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

V RW

CH7LIMITL

   

Write '1' to disable interrupt for CH[7].LIMITL event

See EVENTS_CH[7].LIMITL

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

STATUS

Address offset: 0x400

Status

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID RW Field Value ID Value Description
A R

STATUS

   

Status

     

Ready

0

SAADC is ready. No on-going conversions.

     

Busy

1

SAADC is busy. Conversion in progress.

ENABLE

Address offset: 0x500

Enable or disable SAADC

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID RW Field Value ID Value Description
A RW

ENABLE

   

Enable or disable SAADC

     

Disabled

0

Disable SAADC

     

Enabled

1

Enable SAADC

When enabled, the SAADC will acquire access to analog input pins specified in registers CH[n].PSELP and CH[n].PSELN

CH[n].PSELP (n=0..7)

Address offset: 0x510 + (n × 0x10)

Input positive pin selection for CH[n]

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                       A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID RW Field Value ID Value Description
A RW

PSELP

   

Analog positive input channel

     

NC

0

Not connected

     

AnalogInput0

1

AIN0

     

AnalogInput1

2

AIN1

     

AnalogInput2

3

AIN2

     

AnalogInput3

4

AIN3

     

AnalogInput4

5

AIN4

     

AnalogInput5

6

AIN5

     

AnalogInput6

7

AIN6

     

AnalogInput7

8

AIN7

     

VDD

9

VDD

     

VDDHDIV5

0x0D

VDDH/5

CH[n].PSELN (n=0..7)

Address offset: 0x514 + (n × 0x10)

Input negative pin selection for CH[n]

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID                                                       A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID RW Field Value ID Value Description
A RW

PSELN

   

Analog negative input, enables differential channel

     

NC

0

Not connected

     

AnalogInput0

1

AIN0

     

AnalogInput1

2

AIN1

     

AnalogInput2

3

AIN2

     

AnalogInput3

4

AIN3

     

AnalogInput4

5

AIN4

     

AnalogInput5

6

AIN5

     

AnalogInput6

7

AIN6

     

AnalogInput7

8

AIN7

     

VDD

9

VDD

     

VDDHDIV5

0x0D

VDDH/5

CH[n].CONFIG (n=0..7)

Address offset: 0x518 + (n × 0x10)

Input configuration for CH[n]

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID               G       F   E E E   D   C C C     B B     A A
Reset 0x00020000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ID RW Field Value ID Value Description
A RW

RESP

   

Positive channel resistor control

     

Bypass

0

Bypass resistor ladder

     

Pulldown

1

Pull-down to GND

     

Pullup

2

Pull-up to VDD

     

VDD1_2

3

Set input at VDD/2

B RW

RESN

   

Negative channel resistor control

     

Bypass

0

Bypass resistor ladder

     

Pulldown

1

Pull-down to GND

     

Pullup

2

Pull-up to VDD

     

VDD1_2

3

Set input at VDD/2

C RW

GAIN

   

Gain control

     

Gain1_6

0

1/6

     

Gain1_5

1

1/5

     

Gain1_4

2

1/4

     

Gain1_3

3

1/3

     

Gain1_2

4

1/2

     

Gain1

5

1

     

Gain2

6

2

     

Gain4

7

4

D RW

REFSEL

   

Reference control

     

Internal

0

Internal reference (0.6 V)

     

VDD1_4

1

VDD/4 as reference

E RW

TACQ

   

Acquisition time, the time the SAADC uses to sample the input voltage

     

3us

0

3 µs

     

5us

1

5 µs

     

10us

2

10 µs