RADIO — 2.4 GHz Radio

The 2.4 GHz radio transceiver is compatible with multiple radio standards such as 1 Mbps, 2 Mbps and long range Bluetooth® low energy. IEEE 802.15.4 250 kbps mode is fully supported as well as Nordic's proprietary 1 Mbps and 2 Mbps modes of operation.

Listed here are main features for the RADIO:
  • Multi-domain 2.4 GHz radio transceiver:
    • 1 Mbps, 2Mbps and long range (125kbps and 500kbps mode) Bluetooth® low energy modes
    • 250kbps IEEE 802.15.4 mode
    • 1Mbps and 2Mbps Nordic proprietary modes
  • Best in class link budget and low power operation
  • Efficient data interface with EasyDMA support
  • Automatic address filtering and pattern matching

EasyDMA in combination with an automated packet assembler and packet disassembler, and an automated CRC generator and CRC checker, makes it very easy to configure and use the RADIO. See Figure 1 for details.

Figure 1. RADIO block diagram

The RADIO includes a Device Address match unit and an interframe spacing control unit that can be utilized to simplify address whitelisting and interframe spacing respectively in Bluetooth Smart and similar applications.

The RADIO also includes a Received Signal Strength Indicator (RSSI) and a bit counter. The bit counter generates events when a preconfigured number of bits have been sent or received by the RADIO.

Packet configuration

RADIO packet contains the following fields: PREAMBLE, ADDRESS, S0, LENGTH, S1, PAYLOAD and CRC.

The content of a RADIO packet is illustrated in Figure 2. The RADIO sends the different fields in the packet in the order they are illustrated below, from left to right:

Figure 2. On-air packet layout

Not shown in the figure above is the static payload add-on (the length of which is defined in PCNF1.STATLEN, and which is 0 bytes long in a standard BLE packet). The static payload add-on is sent between the PAYLOAD and CRC fields.

PREAMBLE is sent with least significant bit first on-air. The size of the PREAMBLE depends on the mode selected in the MODE register:

  • For all Nordic proprietary radio modes (Nrf_1Mbit, Nrf_2Mbit and Nrf_250Kbit) and for the Ble_1Mbit mode, the PREAMBLE is one byte long. The PLEN field in the PCNF0 register has to be set accordingly. If the first bit of the ADDRESS is 0, the PREAMBLE is set to 0xAA. Otherwise the PREAMBLE is set to 0x55.
  • For the Ble_2Mbit mode, the PREAMBLE is 2 bytes long. The PLEN field in the PCNF0 register has to be set to 2 bytes accordingly. If the first bit of the ADDRESS is 0, the PREAMBLE is set to 0xAAAA. Otherwise the PREAMBLE is set to 0x5555.
  • For the modes Ble_LR125Kbit and Ble_LR500Kbit, the PREAMBLE is 10 repetitions of 0x3C.
  • For the Ieee802154_250Kbit mode, the PREAMBLE is 4 bytes long and set to all zeros.

Radio packets are stored in memory, inside instances of a radio packet data structure as illustrated in Figure 3. The PREAMBLE, ADDRESS, CI, TERM1, TERM2 and CRC fields are omitted in this data structure.

Figure 3. In-RAM representation of radio packet - S0, LENGTH and S1 are optional

The byte ordering on the air is always:

  • Least significant byte first for the fields ADDRESS and PAYLOAD. The ADDRESS fields are also always transmitted and received least significant bit first on-air.
  • Most significant byte first for the CRC field. The CRC field is also always transmitted and received most significant bit first.

The bit endianness, i.e. the order in which the bits are sent and received, is configured in PCNF1.ENDIAN for the fields S0, LENGTH, S1 and PAYLOAD.

The sizes of the fields S0, LENGTH and S1 can be individually configured in the S0LEN, LFLEN and S1LEN fields of the PCNF0 register respectively. If any of these fields are configured to be less than 8 bit long, the least significant bits of the fields are used, as seen from the RAM representation.

If S0, LENGTH or S1 are specified with zero length, their fields will be omitted in memory. Otherwise each field will be represented as a separate byte, regardless of the number of bits in their on-air counterpart.

The combined length of S0, LENGTH, S1 and PAYLOAD cannot exceed 258 bytes, independent of the configuration in PCNF1.MAXLEN.

Address configuration

The on-air radio ADDRESS field is composed of two parts, the base address field and the address prefix field.

The size of the base address field is configurable via BALEN in PCNF1. The base address is truncated from LSByte if the BALEN is less than 4. See Table 1.

Table 1. Definition of logical addresses
Logical address Base address Prefix byte
0 BASE0 PREFIX0.AP0
1 BASE1 PREFIX0.AP1
2 BASE1 PREFIX0.AP2
3 BASE1 PREFIX0.AP3
4 BASE1 PREFIX1.AP4
5 BASE1 PREFIX1.AP5
6 BASE1 PREFIX1.AP6
7 BASE1 PREFIX1.AP7

The on-air addresses are defined in the BASEn and PREFIXn registers, and it is only when writing these registers the user will have to relate to actual on-air addresses. For other radio address registers such as the TXADDRESS, RXADDRESSES and RXMATCH registers, logical radio addresses ranging from 0 to 7 are being used. The relationship between the on-air radio addresses and the logical addresses is described in Table 1.

Data whitening

The RADIO is able to do packet whitening and de-whitening.

See WHITEEN in PCNF1 register for how to enable whitening. When enabled, whitening and de-whitening will be handled by the RADIO automatically as packets are sent and received.

The whitening word is generated using polynomial g(D) = D7+ D4 + 1, which then is XORed with the data packet that is to be whitened, or de-whitened. See the figure below.

Figure 4. Data whitening and de-whitening

Whitening and de-whitening will be performed over the whole packet (except for the preamble and the address field).

The linear feedback shift register, illustrated in Figure 4 can be initialised via the DATAWHITEIV register.

CRC

The CRC generator in the RADIO calculates the CRC over the whole packet excluding the preamble. If desirable, the address field can be excluded from the CRC calculation as well

See CRCCNF register for more information.

The CRC polynomial is configurable as illustrated in Figure 5 where bit 0 in the CRCPOLY register corresponds to X0 and bit 1 corresponds to X1 etc. See CRCPOLY for more information.

Figure 5. CRC generation of an n bit CRC

As illustrated in Figure 5, the CRC is calculated by feeding the packet serially through the CRC generator. Before the packet is clocked through the CRC generator, the CRC generator's latches b0 through bn will be initialized with a predefined value specified in the CRCINIT register. When the whole packet is clocked through the CRC generator, latches b0 through bn will hold the resulting CRC. This value will be used by the RADIO during both transmission and reception but it is not available to be read by the CPU at any time. A received CRC can however be read by the CPU via the RXCRC register independent of whether or not it has passed the CRC check.

The length (n) of the CRC is configurable, see CRCCNF for more information.

After the whole packet including the CRC has been received, the RADIO will generate a CRCOK event if no CRC errors were detected, or alternatively generate a CRCERROR event if CRC errors were detected.

The status of the CRC check can be read from the CRCSTATUS register after a packet has been received.

Radio states

Tasks and events are used to control the operating state of the RADIO.

The RADIO can enter the states described the table below.
Table 2. RADIO state diagram
State Description
DISABLED No operations are going on inside the radio and the power consumption is at a minimum
RXRU The radio is ramping up and preparing for reception
RXIDLE The radio is ready for reception to start
RX Reception has been started and the addresses enabled in the RXADDRESSES register are being monitored
TXRU The radio is ramping up and preparing for transmission
TXIDLE The radio is ready for transmission to start
TX The radio is transmitting a packet
RXDISABLE The radio is disabling the receiver
TXDISABLE The radio is disabling the transmitter
An overview state diagram for the RADIO is illustrated in Figure 6.
Note: PHYEND is only generated in Ble_LR125Kbit, Ble_LR500Kbit and Ieee802154_250Kbit modes.
Note: The END to START shortcut should not be used with Ble_LR125Kbit, Ble_LR500Kbit and Ieee802154_250Kbit modes. Rather the PHYEND to START shortcut.
Figure 6. Radio states

This figure shows how the tasks and events relate to the RADIO's operation. The RADIO does not prevent a task from being triggered from the wrong state. If a task is triggered from the wrong state, for example if the RXEN task is triggered from the RXDISABLE state, this may lead to incorrect behaviour. As illustrated in Figure 6, the PAYLOAD event is always generated even if the payload is zero.

Transmit sequence

Before the RADIO is able to transmit a packet, it must first ramp-up in TX mode.

See TXRU in Figure 6 and Figure 7. A TXRU ramp-up sequence is initiated when the TXEN task is triggered. After the radio has successfully ramped up it will generate the READY event indicating that a packet transmission can be initiate. A packet transmission is initiated by triggering the START task. As illustrated in Figure 6 the START task can first be triggered after the RADIO has entered into the TXIDLE state.

Figure 7. Transmit sequence

Figure 7 illustrates a single packet transmission where the CPU manually triggers the different tasks needed to control the flow of the RADIO, i.e. no shortcuts are used. If shortcuts are not used, a certain amount of delay caused by CPU execution is expected between READY and START, and between END and DISABLE. As illustrated in Figure 7 the RADIO will by default transmit '1's between READY and START, and between END and DISABLED. What is transmitted can be programmed through the DTX field in the MODECNF0 register.

A slightly modified version of the transmit sequence from Figure 7 is illustrated in Figure 8 where the RADIO is configured to use shortcuts between READY and START, and between END and DISABLE, which means that no delay is introduced.

Figure 8. Transmit sequence using shortcuts to avoid delays

The RADIO is able to send multiple packets one after the other without having to disable and re-enable the RADIO between packets, this is illustrated in Figure 9.

Figure 9. Transmission of multiple packets

Receive sequence

Before the RADIO is able to receive a packet, it must first ramp up in RX mode

See RXRU in Figure 6 and Figure 10.

Figure 10. Receive sequence

An RXRU ramp-up sequence is initiated when the RXEN task is triggered. After the radio has successfully ramped up it will generate the READY event indicating that a packet reception can be initiated. A packet reception is initiated by triggering the START task. As illustrated in Figure 6 the START task can first be triggered after the RADIO has entered into the RXIDLE state.

Figure 10 illustrates a single packet reception where the CPU manually triggers the different tasks needed to control the flow of the RADIO, i.e. no shortcuts are used. If shortcuts are not used, a certain amount of delay, caused by CPU execution, is expected between READY and START, and between END and DISABLE. As illustrated Figure 10 the RADIO will be listening and possibly receiving undefined data, represented with an 'X', from START and until a packet with valid preamble (P) is received.

A slightly modified version of the receive sequence from Figure 10 is illustrated in Figure 11 where the RADIO is configured to use shortcuts between READY and START, and between END and DISABLE, which means that no delay is introduced.

Figure 11. Receive sequence using shortcuts to avoid delays

The RADIO is able to receive multiple packets one after the other without having to disable and re-enable the RADIO between packets as illustrated in Figure 12.

Figure 12. Reception of multiple packets

Received Signal Strength Indicator (RSSI)

The radio implements a mechanism for measuring the power in the received radio signal. This feature is called Received Signal Strength Indicator (RSSI).

Sampling of the received signal strength is started by using the RSSISTART task. The sample can be read from the RSSISAMPLE register.

The sample period of the RSSI is defined by RSSIPERIOD. The RSSI sample will hold the average received signal strength during this sample period.

For the RSSI sample to be valid the radio has to be enabled in receive mode (RXEN task) and the reception has to be started (READY event followed by START task).

Interframe spacing

Interframe spacing is the time interval between two consecutive packets.

It is defined as the time, in micro seconds, from the end of the last bit of the previous packet received and to the start of the first bit of the subsequent packet that is transmitted. The RADIO is able to enforce this interval as specified in the TIFS register as long as TIFS is not specified to be shorter than the RADIO’s turn-around time, i.e. the time needed to switch off the receiver, and switch back on the transmitter. The TIFS register can be written any time before the last bit on air is received.

This timing is illustrated in the Figure 13. As depicted the TIFS duration starts after the last bit on air, just before the END event, and elapses with first bit being transmitted on air (Just after READY event).
Figure 13. IFS Timing Detail

TIFS is only enforced if END_DISABLE and DISABLED_TXEN or END_DISABLE and DISABLED_RXEN shortcuts are enabled. TIFS is qualified for use in BLE_1MBIT, BLE_2MBIT, BLE_LR125KBIT, BLE_LR500KBIT and Ieee802154_250Kbit mode using default ramp-up mode. SHORTS and TIFS are not double buffered and can be updated at any point in time before the last bit on air is received. The MODE register is double buffered and sampled at the TXEN or RXEN task.

Device address match

The device address match feature is tailored for address white listing in a Bluetooth Smart and similar implementations.

This feature enables on-the-fly device address matching while receiving a packet on air. This feature only works in receive mode and as long as RADIO is configured for little endian, see PCNF1.ENDIAN.

The Device Address match unit assumes that the 48 first bits of the payload is the device address and that bit number 6 in S0 is the TxAdd bit. See the Bluetooth Core Specification for more information about device addresses, TxAdd and whitelisting.

The RADIO is able to listen for eight different device addresses at the same time. These addresses are specified in a DAB/DAP register pair, one pair per address, in addition to a TxAdd bit configured in the DACNF register. The DAB register specifies the 32 least significant bits of the device address, while the DAP register specifies the 16 most significant bits of the device address.

Each of the device addresses can be individually included or excluded from the matching mechanism. This is configured in the DACNF register.

Bit counter

The RADIO implements a simple counter that can be configured to generate an event after a specific number of bits have been transmitted or received.

By using shortcuts, this counter can be started from different events generated by the RADIO and hence count relative to these.

The bit counter is started by triggering the BCSTART task, and stopped by triggering the BCSTOP task. A BCMATCH event will be generated when the bit counter has counted the number of bits specified in the BCC register. The bit counter will continue to count bits until the DISABLED event is generated or until the BCSTOP task is triggered. The CPU can therefore, after a BCMATCH event, reconfigure the BCC value for new BCMATCH events within the same packet.

The bit counter can only be started after the RADIO has received the ADDRESS event.

The bit counter will stop and reset on BCSTOP, STOP, END and DISABLE tasks.

The figure below illustrates how the bit counter can be used to generate a BCMATCH event in the beginning of the packet payload, and again generate a second BCMATCH event after sending 2 bytes (16 bits) of the payload.

Figure 14. Bit counter example

IEEE 802.15.4 Operation

With the MODE=Ieee802154_250kbit the radio module will comply with the IEEE 802.15.4-2006 standard implementing its 250 kbps 2450MHz O-QPSK PHY.

The IEEE 802.15.4 standard differs from Nordic's proprietary and Bluetooth Smart modes. Obvious differences are modulation scheme and channel structure, but also packet structure, security and medium access control.

The main features of the IEEE 802.15.4 mode are:
  • Ultra Low power 250 kbps 2450MHz IEEE 802.15.4-2006 compliant link
  • Clear Channel Assessment
  • Energy detection scan
  • CRC Generation

Packet Structure

The IEEE 802.15.4 standard defines an on the air frame/packet that is different from what is used in BTLE mode.

Figure 15 provides an overview of the physical frame structure and its timing.

Figure 15. IEEE 802.15.4 Frame Format - PHY-Layer Frame Structure (PPDU)

The standard uses the term octet as storage unit for 8-bits within the PPDU. For timing the value symbol is used and it has the duration of 16usec.

The total usable payload (PSDU) is 127 octets - but when CRC is being used this is reduced to 125 octets of usable payload.

The preamble sequence consists of four octets that are all zero. These are used for the radio receiver to synchronize on. Following the four octets is a single octet named start of frame delimiter (SFD) with a fixed value of 0xA7. The user can program an alternative SFD through the SFD register. This feature is provided for an initial level of frame filtering for those who choose non standard compliance. It is a valuable feature when operating in a congested or private network. The preamble sequence and SFD is generated by the radio module and is not programmed by the user into the frame buffer.

The PHY header (PHR) is a single octet following the SHR. The least significant seven bits denote the frame length of the following PSDU. The most significant bit is reserved and shall be set to zero for frames that wishes to be standards compliant. The radio module will report all eight bits and it can potentially be used to carry some information. The PHR is the first byte that will be written to the frame Data Memory pointed to by PACKETPTR. Frames with zero length will be discarded and the FRAMESTART event will not be generated in this case.

The next N octets will carry the data of the PHY packet - where N equals the value of the PHR. For an implementation also using the IEEE 802.15.4 MAC layer, the PHY data will be a MAC frame of N-2 octets since two octets will occupy a CRC field.

An IEEE 802.15.4 MAC frame will always consist of a header (The frame control field (FCF), Sequence Number and Addressing Fields), a payload and the 16-bit Frame Control Sequence (FCS) as seen in Figure 16.

Figure 16. IEEE 802.15.4 Frame Format - MAC-Layer Frame Structure (MPDU)

The two FCF octets contains information about what type of frame this is, what addressing it uses and other control flags. This field is decoded when using the assisted operating modes offered by the radio.

The sequence number is a single octet in size and is unique for a frame. It will be used in the associated acknowledgement frame sent upon successful frame reception.

The addressing field can be zero (Acknowledgement Frame) or up to 20 octets in size. The field is used to direct packets to the correct recipient as well as denoting its origin. IEEE 802.15.4 bases it's addressing on networks being organized in PANs with 16-bit identifier and nodes having a 16 or 64-bit address. In the assisted receive mode these parameters are analyzed for address matching and acknowledgement.

The MAC payload carries the data of the next higher layer or in the case of a MAC command frame information used by the MAC layer itself.

The two last octets contain the 16-bit ITU-T CRC. The FCS is calculated over the MAC header (MHR) and MAC payload (MSDU) parts of the frame. This field is calculated automatically when sending a frame - or indicated in the CRCSTATUS register when a frame is received. This feature is taken care of autonomously by the CRC module if configured.

Operating Frequencies

The IEEE 802.15.4 standard defines 16 channels [11 - 26] in the 2450MHz frequency band of 5MHz each.

The FREQUENCY register of the radio module must be programmed according to Table 3 for correct operation on the center frequency defined for each channel.

Table 3. IEEE 802.15.4 Center Frequency Definition
IEEE 802.15.4 Channel Center Frequency (MHz) FREQUENCY Setting
Channel 11 2405 5
Channel 12 2410 10
Channel 13 2415 15
Channel 14 2420 20
Channel 15 2425 25
Channel 16 2430 30
Channel 17 2435 35
Channel 18 2440 40
Channel 19 2445 45
Channel 20 2450 50
Channel 21 2455 55
Channel 22 2460 60
Channel 23 2465 65
Channel 24 2470 70
Channel 25 2475 75
Channel 26 2480 80

Energy Detection

The IEEE 802.15.4 standard requires that it is possible to sample the received signal power within the bandwidth of a channel for the purpose of determining presence of activity.

There should be no attempt made to decode the signals on the channel, and this is done by disabling the shortcut between READY event and START task before putting the radio in receive mode. The energy detection (ED) measurement time where RSSI samples are averaged over is 8 symbol periods (128 microseconds). The standard further specifies the measurement to be a number between 0 and 0xFF - where 0 shall indicate received power less than 10dB above the selected receiver sensitivity. The power range of the ED values must be at least 40dB with a linear mapping with accuracy of +-6dB. See section 6.9.7 Receiver ED in the standard for further details. An example of an ED scan is given below.

Below is a code snippet showing how to perform a single energy detection measurement.

    	
    	uint8_t sample_ed(void)
    	{
    		NRF_RADIO->TASKS_EDSTART = 1;              //Start
    		while (NRF_RADIO->EVENTS_EDEND != 1) {
          //CPU can sleep here or do something else
          //Use of interrupts are encouraged 
        }
    		return (uint8_t)NRF_RADIO->EDSAMPLE; //Read level				
    	}
        
    

It is the mlme-scan.req primitive of the MAC layer that is using the ED measurement to detect channels where there might be wireless activity. To assist this primitive a taylored mode of operation is available where the ED measurement runs for a defined number of iterations where it keeps track of the maximum ED level. This is enganged by writing the ED_CNT register to a value different from 0, it will then run the specified number of iterations reporting the maximum energy measurement in the EDSAMPLE register. The scan is started with EDSTART task and its end indicated with the EDEND event. This greatly reduces the interrupt frequency and hence power consumtion. Figure 17 shows how the ED measurement will operate depending on the ED_CNT register.

Figure 17. Energy Detection Measurement Examples

An ongoing scan can always be stopped by writing the EDSTOP task. It will be followed by the EDSTOPPED event when the module has terminated.

Clear Channel Assessment

IEEE 802.15.4 implements a listen-before-talk channel access method to avoid collisions when transmitting - namely Carrier Sense Multiple Access with Collision Avoidance (CSMA-CA). The key part of this is measuring if the wireless medium is busy or not.

At least three methods must be supported:

  • Mode 1 (Energy above threshold): The medium is reported busy upon detecting any energy above the ED threshold
  • Mode 2 (Carrier sense only): The medium is reported busy upon detection of a signal compliant with the IEEE 802.15.4 standard with the same modulation and spreading characteristics.
  • Mode 3 (Carrier sense and threshold): The medium is reported busy by logically ANDing or ORing the results from Mode 1 and Mode 2.

It is furthermore specified that the clear channel assessment should survey a period equal to 8 symbols or 128usec.

The radio module has to be in receive mode and be able to recived correct packets when performing the CCA. The shortcut between READY and START must be disabled if baseband processing is not to be performed while the measurement is running.

Mode 1 is enabled by first configuring the CCA_MODE=EdMode and writing the CCA_EDTHRES to a chosen value. When the CCA_START task is written the radio module will perform a ED measurement for 8 symbols and compare the measured level with that found in the CCA_EDTHRES register. If the measured value is higher than or equal to this threshold the CCABUSY event is generated - the CCAIDLE event is generated if the measured level is less than the threshold.

Mode 2 is enabled by configuring the CCA_MODE=CarrierMode. In carrier mode the module will sample to see if a valid SFD is found during the 8 symbols. If a valid SFD is seen the CCABUSY event is generated and the node should not send any data. The CCABUSY event is also generated if the scan was performed during an ongoing frame reception. In the case where the measurement period completes with no SFD detection the CCAIDLE task is generated. With the CCA_CORR_COUNT unequal to zero the algorithm will look at the correlator output in addition to the SFD detection signal. If a SFD is reported during the scan period it will terminate immidiately indicating busy medium. Similarly, if the number of peaks above CCA_CORRTHRES crosses the CCA_CORR_COUNT the CCABUSY event is generated. If less than CCA_CORR_COUNT crossings are found and no SFD is reported the CCAIDLE signal will be generated and it is ok for the node to commence sending data.

With the CCA_MODE=CarrierAndEdMode or CCA_MODE=CarrierOrEdMode a logical combination of the result from running both Mode 1 and Mode 2 is performed. The CCABUSY or CCAIDLE signal will be generated based on an ANDing or ORing of the internal signals from performing both the energy detection and carrier detection scans.

An ongoing CCA can always be stopped by issuing the CCASTOP task. This will trigger the associated CCASTOPPED event.

For CCA mode automation there are three shortcuts available. One is between CCAIDLE and TXEN. This short must always be used in conjunction with the short between CCAIDLE and STOP. This automation is provided so that the radio can automatically switch between RX (When performing the CCA) and to TX where the packet is sent. The last shortcut associated with the CCA mode is between CCABUSY and DISABLE. This will cause the radio to be disabled whenever the CCA reports a busy medium.

Another handy shortcut is between RXREADY and CCASTART. When the radio has ramped up into RX mode it can immidiately start a CCA.

Cyclic Redundancy Check

IEEE 802.15.4 uses a 16-bit ITU-T cyclic redundancy check (CRC) calculated over the MHR and MSDU.

The standard defines the following generator polynomial:

G(x) = x16 + x12 + x5 + 1

In receive mode the radio will trigger the CRC module when the first octet after the frame length (PHR) is received. The CRC will then update on each consecutive octet received. When a complete frame is received the CRCSTATUS register will be updated accordingly and the EVENTS_CRCOK or EVENTS_CRCERROR generated. When the CRC module is enabled it will not write the two last octets (CRC) to the frame Data RAM. When transmitting the CRC will be computed on the fly, starting with the first octet after PHR, and inserted as the two last octets in the frame. The EasyDMA will fetch frame length - 2 octets from DataRAM and insert the CRC octets insitu.

Below is a code snippet for configuring the CRC module for correct operation when in IEEE 802.15.4 mode. The CRCCNF is written to 16-bit CRC and the CRCPOLY is written to 0x121. The start value used by IEEE 802.15.4 is zero and CRCINIT is configured to reflect this.

        
		/* 16-bit CRC with ITU-T polynomial with 0 as start condition*/
		write_reg(NRFRADIO_REG(CRCCNF), 0x202);
		write_reg(NRFRADIO_REG(CRCPOLY), 0x11021);
		write_reg(NRFRADIO_REG(CRCINIT), 0);
        
      

The ENDIANESS subregister must be set to LittleEndian since the FCS field is transmitted leftmost bit first.

Transmit Sequence

The transmission is started by first putting the radio in receive mode sending the RXEN task.

Figure 18. IEEE 802.15.4 Transmit Sequence

The receiver will ramp up and enter the RXIDLE state where the READY event is generated. Upon receiving the ready event the CCA is started by writing to the CCASTART task register. The chosen mode of assessment (CCA_MODE register) will be performed and signal the CCAIDLE or CCABUSY event 128usec later. If the CCABUSY is received the radio will have to retry the CCA after a specific back off period as outlined in the IEEE 802.15.4 standard (See Figure 69 in section 7.5.1.4 The CSMA-CA algorithm of the standard). An outline of the IEEE 802.15.4 transmission can be found in the figure below.

When the CCAIDLE event on the other hand is generated the user shall write to the TXEN task register to enter the TXRU state. The READY event will be generated when the radio is in TXIDLE state and ready to transmit. With the PACKETPTR pointing to the length (PHR) field of the frame the START task can be written. The radio will send the four octet preamble sequence followed by the start of frame delimiter (SFD register). The first byte read from the DataRAM is the length field (PHR) followed by the transmission of the number of bytes indicated as the frame length. If the CRC module is configured it will run for PHR-2 octets. The last two octets will be substituted with the results from running the CRC. The necessary CRC parameters are sampled on the START task. The FCS field of the frame is little endian.

In addition to the already available shortcuts, one is provided between READY event and CCASTART task so that a CCA can automatically start when the receiver is ready. And a second shortcut has been added between CCAIDLE event and the TXEN task so that upon detecting a clear channel the radio can immediately enter transmit mode.

Receive Sequence

The reception is started by first putting the radio in receive mode. Writing to the RXEN task the radio will start ramping up and enter the RXRU state.

When the READY event is generated the radio has entered the RXIDLE mode. For the baseband processing to be enabled the START task must be written. An outline of the IEEE 802.15.4 reception can be found in Figure 19

Figure 19. IEEE 802.15.4 Receive Sequence

When a valid SHR is received the radio will start storing future octets (Starting with PHR) to the DataMemory pointed to by PACKETPTR. After the SFD octet is received the FRAMESTART event is generated. If the CRC module is enabled it will start updating with the second byte received (First byte in payload) and run for the full frame length. The two last bytes in the frame is not written to DataRAM when CRC is configured. However, if the result of the CRC after running the full frame is zero the CRCOK event will be generated. The END event is generated when the last octet has been received and is available in DataRAM.

When a packet is received a link quality indicator (LQI) is also generated and appended immediately after the last received octet. When using IEEE 802.15.4 compliant frame this will be just after the MSDU since the FCS is not reported. In the case of a non-complient frame it will be appended after the full frame. The LQI is a number ranging from 0 (lowest link quality) to 255 (highest link quality). The LQI is only valid for frames equal to or longer than three octets. When receiving a frame the RSSI (Reported as negative dB) will be measured at three points during the reception. These three values will be sorted and the middle one selected (Median 3) for then to be remapped within the LQI range. See Figure 20 for further detail on the LQI measurement and how the data is arranged in the DataRAM.

Figure 20. IEEE 802.15.4 Frame In DataRAM

A shortcut has been added between FRAMESTART event and the BCSTART task. This can be used to trig a BCMATCH event after N bits - such as when inspecting the MAC addressing fields.

Interframe Spacing

The IEEE 802.15.4 standard defines a specific time that is alotted for the MAC sublayer to process received data. Usage of this interframe spacing (IFS) comes into play to avoid that two frames are transmitted too close to eachother in time. If the a transmission is requesting an acknowledgement, the speration to the second frame shall be at least an IFS period.

The IFS is determined to be:
  • IFS equals macMinSIFSPeriod (12 symbols) if the MPDU is less than or equal to aMaxSIFSFrameSize (18 octets) octets
  • IFS equals macMinLIFSPeriod (40 symbols) if the MPDU is larger than aMaxSIFSFrameSize

The TIFS register must be manually updated by the user based upon the above mentioned length rules. Figure 21 provides further detail on what IFS period is valid in both acknowledged and unacknowledged transmissions.

Figure 21. Interframe Spacing Examples

EasyDMA

The RADIO peripheral uses EasyDMA for reading of data packets from and writing to RAM, without CPU involvement.

As illustrated in Figure 1, the RADIO's EasyDMA utilizes the same PACKETPTR for receiving and transmitting packets. This pointer should be reconfigured by the CPU each time before RADIO is started by the START task. Both the PACKETPTR and MAXLEN registers are double-buffered, meaning that they can be updated and prepared for the next transmission.

Important: If the PACKETPTR is not pointing to the Data RAM region, an EasyDMA transfer may result in a HardFault or RAM corruption. See Memory for more information about the different memory regions.

The END event indicates that the last bit has been processed by the radio. The DISABLED event is issued to acknowledge that a DISABLE task is done.

The structure of a radio packet is described in detail in Packet configuration. The data that is stored in Data RAM and transported by EasyDMA consists of the following fields:

  • S0
  • LENGTH
  • S1
  • PAYLOAD

In addition, a static add-on is sent immediately after the payload.

The size of each of the above fields in the frame is configurable, and the space occupied in RAM depends on these settings. A size of zero is possible for any of the fields, it is up to the user to make sure that the resulting frame complies with the RF protocol chosen. All fields are extended in size to align with a byte boundary in RAM. For instance a 3 bit long field on air will occupy 1 byte in RAM while a 9 bit long field will be extended to 2 bytes.

The radio packet fields can be configured as follows:
  • The fields CI, TERM1 and TERM2 are only present in Bluetooth Smart Long Range mode
  • S0 is configured in the S0LEN field of the PCNF0 register
  • LENGTH is configured in the LFLEN field of the PCNF0 register
  • S1 is configured in the S1LEN field of the PCNF0 register
  • The size of the payload is configured by the value in RAM corresponding to the LENGTH field
  • The size of the static add-on to the payload is configured in the STATLEN field of the PCNF1 register

The MAXLEN field in the PCNF1 register configures the maximum packet payload plus add-on size in number of bytes that can be transmitted or received by the RADIO. This feature can be used to ensure that the RADIO does not overwrite, or read beyond, the RAM assigned to the packet payload. This means that if the packet payload length defined by the PCNF1.STATLEN and the LENGTH field in the packet specify a packet larger than MAXLEN, the payload will be truncated at MAXLEN. The packet's LENGTH field will not be altered when the payload is truncated. The RADIO will calculate CRC as if the packet length is equal to MAXLEN.

Important: The MAXLEN includes the size of the payload and the add-on, but excludes the size occupied by the fields S0, LENGTH and S1. This has to be taken into account when allocating RAM.

Registers

Table 4. Instances
Base address Peripheral Instance Description Configuration
0x40001000 RADIO RADIO

2.4 GHz radio

   
Table 5. Register Overview
Register Offset Description
TASKS_TXEN 0x000

Enable RADIO in TX mode

 
TASKS_RXEN 0x004

Enable RADIO in RX mode

 
TASKS_START 0x008

Start RADIO

 
TASKS_STOP 0x00C

Stop RADIO

 
TASKS_DISABLE 0x010

Disable RADIO

 
TASKS_RSSISTART 0x014

Start the RSSI and take one single sample of the receive signal strength.

 
TASKS_RSSISTOP 0x018

Stop the RSSI measurement

 
TASKS_BCSTART 0x01C

Start the bit counter

 
TASKS_BCSTOP 0x020

Stop the bit counter

 
TASKS_EDSTART 0x024

Start the Energy Detect measurement used in IEEE 802.15.4 mode

 
TASKS_EDSTOP 0x028

Stop the Energy Detect measurement

 
TASKS_CCASTART 0x02C

Start the Clear Channel Assessment used in IEEE 802.15.4 mode

 
TASKS_CCASTOP 0x030

Stop the Clear Channel Assessment

 
EVENTS_READY 0x100

RADIO has ramped up and is ready to be started

 
EVENTS_ADDRESS 0x104

Address sent or received

 
EVENTS_PAYLOAD 0x108

Packet payload sent or received

 
EVENTS_END 0x10C

Packet sent or received

 
EVENTS_DISABLED 0x110

RADIO has been disabled

 
EVENTS_DEVMATCH 0x114

A device address match occurred on the last received packet

 
EVENTS_DEVMISS 0x118

No device address match occurred on the last received packet

 
EVENTS_RSSIEND 0x11C

Sampling of receive signal strength complete.

 
EVENTS_BCMATCH 0x128

Bit counter reached bit count value.

 
EVENTS_CRCOK 0x130

Packet received with CRC ok

 
EVENTS_CRCERROR 0x134

Packet received with CRC error

 
EVENTS_FRAMESTART 0x138

IEEE 802.15.4 length field received

 
EVENTS_EDEND 0x13C

Sampling of Energy Detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register

 
EVENTS_EDSTOPPED 0x140

The sampling of Energy Detection has stopped

 
EVENTS_CCAIDLE 0x144

Wireless medium in idle - clear to send

 
EVENTS_CCABUSY 0x148

Wireless medium busy - do not send

 
EVENTS_CCASTOPPED 0x14C

The CCA has stopped

 
EVENTS_RATEBOOST 0x150

Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit.

 
EVENTS_TXREADY 0x154

RADIO has ramped up and is ready to be started TX path

 
EVENTS_RXREADY 0x158

RADIO has ramped up and is ready to be started RX path

 
EVENTS_MHRMATCH 0x15C

MAC Header match found.

 
EVENTS_PHYEND 0x16C

Generated in Ble_LR125Kbit, Ble_LR500Kbit and BleIeee802154_250Kbit modes when last bit is sent on air.

 
SHORTS 0x200

Shortcut register

 
INTENSET 0x304

Enable interrupt

 
INTENCLR 0x308

Disable interrupt

 
CRCSTATUS 0x400

CRC status

 
RXMATCH 0x408

Received address

 
RXCRC 0x40C

CRC field of previously received packet

 
DAI 0x410

Device address match index

 
PDUSTAT 0x414

Payload status

 
PACKETPTR 0x504

Packet pointer

 
FREQUENCY 0x508

Frequency

 
TXPOWER 0x50C

Output power

 
MODE 0x510

Data rate and modulation

 
PCNF0 0x514

Packet configuration register 0

 
PCNF1 0x518

Packet configuration register 1

 
BASE0 0x51C

Base address 0

 
BASE1 0x520

Base address 1

 
PREFIX0 0x524

Prefixes bytes for logical addresses 0-3

 
PREFIX1 0x528

Prefixes bytes for logical addresses 4-7

 
TXADDRESS 0x52C

Transmit address select

 
RXADDRESSES 0x530

Receive address select

 
CRCCNF 0x534

CRC configuration

 
CRCPOLY 0x538

CRC polynomial

 
CRCINIT 0x53C

CRC initial value

 
TIFS 0x544

Inter Frame Spacing in us

 
RSSISAMPLE 0x548

RSSI sample

 
STATE 0x550

Current radio state

 
DATAWHITEIV 0x554

Data whitening initial value

 
BCC 0x560

Bit counter compare

 
DAB[0] 0x600

Device address base segment 0

 
DAB[1] 0x604

Device address base segment 1

 
DAB[2] 0x608

Device address base segment 2

 
DAB[3] 0x60C

Device address base segment 3

 
DAB[4] 0x610

Device address base segment 4

 
DAB[5] 0x614

Device address base segment 5

 
DAB[6] 0x618

Device address base segment 6

 
DAB[7] 0x61C

Device address base segment 7

 
DAP[0] 0x620

Device address prefix 0

 
DAP[1] 0x624

Device address prefix 1

 
DAP[2] 0x628

Device address prefix 2

 
DAP[3] 0x62C

Device address prefix 3

 
DAP[4] 0x630

Device address prefix 4

 
DAP[5] 0x634

Device address prefix 5

 
DAP[6] 0x638

Device address prefix 6

 
DAP[7] 0x63C

Device address prefix 7

 
DACNF 0x640

Device address match configuration

 
MHRMATCHCONF 0x644

Search Pattern Configuration

 
MHRMATCHMAS 0x648

Pattern mask

 
MODECNF0 0x650

Radio mode configuration register 0

 
SFD 0x660

IEEE 802.15.4 Start of Frame Delimiter

 
EDCNT 0x664

IEEE 802.15.4 Energy Detect Loop Count

 
EDSAMPLE 0x668

IEEE 802.15.4 Energy Detect Level

 
CCACTRL 0x66C

IEEE 802.15.4 Clear Channel Assessment Control

 
POWER 0xFFC

Peripheral power control

 

SHORTS

Address offset: 0x200

Shortcut register

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                    

U

T

S

R

Q

P

O

N

M

L

K

H

 

G

F

E

D

C

B

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

READY_START

   

Shortcut between READY event and START task

See EVENTS_READY and TASKS_START

     

Disabled

0

Disable shortcut

     

Enabled

1

Enable shortcut

B RW

END_DISABLE

   

Shortcut between END event and DISABLE task

See EVENTS_END and TASKS_DISABLE

     

Disabled

0

Disable shortcut

     

Enabled

1

Enable shortcut

C RW

DISABLED_TXEN

   

Shortcut between DISABLED event and TXEN task

See EVENTS_DISABLED and TASKS_TXEN

     

Disabled

0

Disable shortcut

     

Enabled

1

Enable shortcut

D RW

DISABLED_RXEN

   

Shortcut between DISABLED event and RXEN task

See EVENTS_DISABLED and TASKS_RXEN

     

Disabled

0

Disable shortcut

     

Enabled

1

Enable shortcut

E RW

ADDRESS_RSSISTART

   

Shortcut between ADDRESS event and RSSISTART task

See EVENTS_ADDRESS and TASKS_RSSISTART

     

Disabled

0

Disable shortcut

     

Enabled

1

Enable shortcut

F RW

END_START

   

Shortcut between END event and START task

See EVENTS_END and TASKS_START

     

Disabled

0

Disable shortcut

     

Enabled

1

Enable shortcut

G RW

ADDRESS_BCSTART

   

Shortcut between ADDRESS event and BCSTART task

See EVENTS_ADDRESS and TASKS_BCSTART

     

Disabled

0

Disable shortcut

     

Enabled

1

Enable shortcut

H RW

DISABLED_RSSISTOP

   

Shortcut between DISABLED event and RSSISTOP task

See EVENTS_DISABLED and TASKS_RSSISTOP

     

Disabled

0

Disable shortcut

     

Enabled

1

Enable shortcut

K RW

RXREADY_CCASTART

   

Shortcut between RXREADY event and CCASTART task

See EVENTS_RXREADY and TASKS_CCASTART

     

Disabled

0

Disable shortcut

     

Enabled

1

Enable shortcut

L RW

CCAIDLE_TXEN

   

Shortcut between CCAIDLE event and TXEN task

See EVENTS_CCAIDLE and TASKS_TXEN

     

Disabled

0

Disable shortcut

     

Enabled

1

Enable shortcut

M RW

CCABUSY_DISABLE

   

Shortcut between CCABUSY event and DISABLE task

See EVENTS_CCABUSY and TASKS_DISABLE

     

Disabled

0

Disable shortcut

     

Enabled

1

Enable shortcut

N RW

FRAMESTART_BCSTART

   

Shortcut between FRAMESTART event and BCSTART task

See EVENTS_FRAMESTART and TASKS_BCSTART

     

Disabled

0

Disable shortcut

     

Enabled

1

Enable shortcut

O RW

READY_EDSTART

   

Shortcut between READY event and EDSTART task

See EVENTS_READY and TASKS_EDSTART

     

Disabled

0

Disable shortcut

     

Enabled

1

Enable shortcut

P RW

EDEND_DISABLE

   

Shortcut between EDEND event and DISABLE task

See EVENTS_EDEND and TASKS_DISABLE

     

Disabled

0

Disable shortcut

     

Enabled

1

Enable shortcut

Q RW

CCAIDLE_STOP

   

Shortcut between CCAIDLE event and STOP task

See EVENTS_CCAIDLE and TASKS_STOP

     

Disabled

0

Disable shortcut

     

Enabled

1

Enable shortcut

R RW

TXREADY_START

   

Shortcut between TXREADY event and START task

See EVENTS_TXREADY and TASKS_START

     

Disabled

0

Disable shortcut

     

Enabled

1

Enable shortcut

S RW

RXREADY_START

   

Shortcut between RXREADY event and START task

See EVENTS_RXREADY and TASKS_START

     

Disabled

0

Disable shortcut

     

Enabled

1

Enable shortcut

T RW

PHYEND_DISABLE

   

Shortcut between PHYEND event and DISABLE task

See EVENTS_PHYEND and TASKS_DISABLE

     

Disabled

0

Disable shortcut

     

Enabled

1

Enable shortcut

U RW

PHYEND_START

   

Shortcut between PHYEND event and START task

See EVENTS_PHYEND and TASKS_START

     

Disabled

0

Disable shortcut

     

Enabled

1

Enable shortcut

 

INTENSET

Address offset: 0x304

Enable interrupt

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id        

Z

V

U

T

S

R

Q

P

O

N

M

L

K

I

   

H

G

F

E

D

C

B

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

READY

   

Write '1' to Enable interrupt for READY event

See EVENTS_READY

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

B RW

ADDRESS

   

Write '1' to Enable interrupt for ADDRESS event

See EVENTS_ADDRESS

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

C RW

PAYLOAD

   

Write '1' to Enable interrupt for PAYLOAD event

See EVENTS_PAYLOAD

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

D RW

END

   

Write '1' to Enable interrupt for END event

See EVENTS_END

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

E RW

DISABLED

   

Write '1' to Enable interrupt for DISABLED event

See EVENTS_DISABLED

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

F RW

DEVMATCH

   

Write '1' to Enable interrupt for DEVMATCH event

See EVENTS_DEVMATCH

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

G RW

DEVMISS

   

Write '1' to Enable interrupt for DEVMISS event

See EVENTS_DEVMISS

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

H RW

RSSIEND

   

Write '1' to Enable interrupt for RSSIEND event

See EVENTS_RSSIEND

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

I RW

BCMATCH

   

Write '1' to Enable interrupt for BCMATCH event

See EVENTS_BCMATCH

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

K RW

CRCOK

   

Write '1' to Enable interrupt for CRCOK event

See EVENTS_CRCOK

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

L RW

CRCERROR

   

Write '1' to Enable interrupt for CRCERROR event

See EVENTS_CRCERROR

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

M RW

FRAMESTART

   

Write '1' to Enable interrupt for FRAMESTART event

See EVENTS_FRAMESTART

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

N RW

EDEND

   

Write '1' to Enable interrupt for EDEND event

See EVENTS_EDEND

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

O RW

EDSTOPPED

   

Write '1' to Enable interrupt for EDSTOPPED event

See EVENTS_EDSTOPPED

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

P RW

CCAIDLE

   

Write '1' to Enable interrupt for CCAIDLE event

See EVENTS_CCAIDLE

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

Q RW

CCABUSY

   

Write '1' to Enable interrupt for CCABUSY event

See EVENTS_CCABUSY

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

R RW

CCASTOPPED

   

Write '1' to Enable interrupt for CCASTOPPED event

See EVENTS_CCASTOPPED

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

S RW

RATEBOOST

   

Write '1' to Enable interrupt for RATEBOOST event

See EVENTS_RATEBOOST

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

T RW

TXREADY

   

Write '1' to Enable interrupt for TXREADY event

See EVENTS_TXREADY

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

U RW

RXREADY

   

Write '1' to Enable interrupt for RXREADY event

See EVENTS_RXREADY

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

V RW

MHRMATCH

   

Write '1' to Enable interrupt for MHRMATCH event

See EVENTS_MHRMATCH

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

Z RW

PHYEND

   

Write '1' to Enable interrupt for PHYEND event

See EVENTS_PHYEND

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

 

INTENCLR

Address offset: 0x308

Disable interrupt

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id        

Z

V

U

T

S

R

Q

P

O

N

M

L

K

I

   

H

G

F

E

D

C

B

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

READY

   

Write '1' to Disable interrupt for READY event

See EVENTS_READY

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

B RW

ADDRESS

   

Write '1' to Disable interrupt for ADDRESS event

See EVENTS_ADDRESS

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

C RW

PAYLOAD

   

Write '1' to Disable interrupt for PAYLOAD event

See EVENTS_PAYLOAD

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

D RW

END

   

Write '1' to Disable interrupt for END event

See EVENTS_END

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

E RW

DISABLED

   

Write '1' to Disable interrupt for DISABLED event

See EVENTS_DISABLED

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

F RW

DEVMATCH

   

Write '1' to Disable interrupt for DEVMATCH event

See EVENTS_DEVMATCH

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

G RW

DEVMISS

   

Write '1' to Disable interrupt for DEVMISS event

See EVENTS_DEVMISS

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

H RW

RSSIEND

   

Write '1' to Disable interrupt for RSSIEND event

See EVENTS_RSSIEND

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

I RW

BCMATCH

   

Write '1' to Disable interrupt for BCMATCH event

See EVENTS_BCMATCH

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

K RW

CRCOK

   

Write '1' to Disable interrupt for CRCOK event

See EVENTS_CRCOK

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

L RW

CRCERROR

   

Write '1' to Disable interrupt for CRCERROR event

See EVENTS_CRCERROR

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

M RW

FRAMESTART

   

Write '1' to Disable interrupt for FRAMESTART event

See EVENTS_FRAMESTART

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

N RW

EDEND

   

Write '1' to Disable interrupt for EDEND event

See EVENTS_EDEND

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

O RW

EDSTOPPED

   

Write '1' to Disable interrupt for EDSTOPPED event

See EVENTS_EDSTOPPED

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

P RW

CCAIDLE

   

Write '1' to Disable interrupt for CCAIDLE event

See EVENTS_CCAIDLE

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

Q RW

CCABUSY

   

Write '1' to Disable interrupt for CCABUSY event

See EVENTS_CCABUSY

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

R RW

CCASTOPPED

   

Write '1' to Disable interrupt for CCASTOPPED event

See EVENTS_CCASTOPPED

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

S RW

RATEBOOST

   

Write '1' to Disable interrupt for RATEBOOST event

See EVENTS_RATEBOOST

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

T RW

TXREADY

   

Write '1' to Disable interrupt for TXREADY event

See EVENTS_TXREADY

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

U RW

RXREADY

   

Write '1' to Disable interrupt for RXREADY event

See EVENTS_RXREADY

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

V RW

MHRMATCH

   

Write '1' to Disable interrupt for MHRMATCH event

See EVENTS_MHRMATCH

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

Z RW

PHYEND

   

Write '1' to Disable interrupt for PHYEND event

See EVENTS_PHYEND

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

 

CRCSTATUS

Address offset: 0x400

CRC status

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                                              

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A R

CRCSTATUS

   

CRC status of packet received

     

CRCError

0

Packet received with CRC error

     

CRCOk

1

Packet received with CRC ok

 

RXMATCH

Address offset: 0x408

Received address

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                                          

A

A

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A R

RXMATCH

   

Received address

Logical address of which previous packet was received

 

RXCRC

Address offset: 0x40C

CRC field of previously received packet

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A R

RXCRC

   

CRC field of previously received packet

CRC field of previously received packet

 

DAI

Address offset: 0x410

Device address match index

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                                          

A

A

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A R

DAI

   

Device address match index

Index (n) of device address, see DAB[n] and DAP[n], that got an address match.

 

PDUSTAT

Address offset: 0x414

Payload status

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                                          

B

B

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A R

PDUSTAT

   

Status on payload length vs. PCNF1.MAXLEN

     

LessThan

0

Payload less than PCNF1.MAXLEN

     

GreaterThan

1

Payload greater than PCNF1.MAXLEN

B R

CISTAT

   

Status on what rate packet is received with in Long Range

     

LR125kbit

0

Frame is received at 125kbps

     

LR500kbit

1

Frame is received at 500kbps

 

PACKETPTR

Address offset: 0x504

Packet pointer

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

PACKETPTR

   

Packet pointer

Packet address to be used for the next transmission or reception. When transmitting, the packet pointed to by this address will be transmitted and when receiving, the received packet will be written to this address. This address is a byte aligned ram address.

 

FREQUENCY

Address offset: 0x508

Frequency

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                              

B

 

A

A

A

A

A

A

A

Reset 0x00000002 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Id RW Field Value Id Value Description
A RW

FREQUENCY

 

[0..100]

Radio channel frequency

Frequency = 2400 + FREQUENCY (MHz).

B RW

MAP

   

Channel map selection.

     

Default

0

Channel map between 2400 MHZ .. 2500 MHz

Frequency = 2400 + FREQUENCY (MHz)

     

Low

1

Channel map between 2360 MHZ .. 2460 MHz

Frequency = 2360 + FREQUENCY (MHz)

 

TXPOWER

Address offset: 0x50C

Output power

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                              

A

A

A

A

A

A

A

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

TXPOWER

   

RADIO output power.

Output power in number of dBm, i.e. if the value -20 is specified the output power will be set to -20dBm.

     

Pos8dBm

0x8

+8 dBm

     

Pos7dBm

0x7

+7 dBm

     

Pos6dBm

0x6

+6 dBm

     

Pos5dBm

0x5

+5 dBm

     

Pos4dBm