PPI — Programmable peripheral interconnect

The Programmable peripheral interconnect (PPI) enables peripherals to interact autonomously with each other using tasks and events independent of the CPU. The PPI allows precise synchronization between peripherals when real-time application constraints exist and eliminates the need for CPU activity to implement behavior which can be predefined using PPI.

Figure 1. PPI block diagram

The PPI system has, in addition to the fully programmable peripheral interconnections, a set of channels where the event end point (EEP) and task end points (TEP) are fixed in hardware. These fixed channels can be individually enabled, disabled, or added to PPI channel groups in the same way as ordinary PPI channels.

Table 1. Configurable and fixed PPI channels
Instance Channel Number of channels Number of groups
PPI 0-19 20 6
PPI (fixed) 20-31 12

The PPI provides a mechanism to automatically trigger a task in one peripheral as a result of an event occurring in another peripheral. A task is connected to an event through a PPI channel. The PPI channel is composed of three end point registers, one EEP and two TEPs. A peripheral task is connected to a TEP using the address of the task register associated with the task. Similarly, a peripheral event is connected to an EEP using the address of the event register associated with the event.

On each PPI channel, the signals are synchronized to the 16 MHz clock, to avoid any internal violation of setup and hold timings. As a consequence, events that are synchronous to the 16 MHz clock will be delayed by one clock period, while other asynchronous events will be delayed by up to one 16 MHz clock period.

Note that shortcuts (as defined in the SHORTS register in each peripheral) are not affected by this 16 MHz synchronization, and are therefore not delayed.

Each TEP implements a fork mechanism that enables a second task to be triggered at the same time as the task specified in the TEP is triggered. This second task is configured in the task end point register in the FORK registers groups, e.g. FORK.TEP[0] is associated with PPI channel CH[0].

There are two ways of enabling and disabling PPI channels:

Note that when a channel belongs to two groups m and n, and CHG[m].EN and CHG[n].DIS occur simultaneously (m and n can be equal or different), EN on that channel has priority.

PPI tasks (for example, CHG[0].EN) can be triggered through the PPI like any other task, which means they can be hooked up to a PPI channel as a TEP. One event can trigger multiple tasks by using multiple channels and one task can be triggered by multiple events in the same way.

Pre-programmed channels

Some of the PPI channels are pre-programmed. These channels cannot be configured by the CPU, but can be added to groups and enabled and disabled like the general purpose PPI channels. The FORK TEP for these channels are still programmable and can be used by the application.

For a list of pre-programmed PPI channels, see the table below.

Table 2. Pre-programmed channels
Channel EEP TEP
20 TIMER0->EVENTS_COMPARE[0] RADIO->TASKS_TXEN
21 TIMER0->EVENTS_COMPARE[0] RADIO->TASKS_RXEN
22 TIMER0->EVENTS_COMPARE[1] RADIO->TASKS_DISABLE
23 RADIO->EVENTS_BCMATCH AAR->TASKS_START
24 RADIO->EVENTS_READY CCM->TASKS_KSGEN
25 RADIO->EVENTS_ADDRESS CCM->TASKS_CRYPT
26 RADIO->EVENTS_ADDRESS TIMER0->TASKS_CAPTURE[1]
27 RADIO->EVENTS_END TIMER0->TASKS_CAPTURE[2]
28 RTC0->EVENTS_COMPARE[0] RADIO->TASKS_TXEN
29 RTC0->EVENTS_COMPARE[0] RADIO->TASKS_RXEN
30 RTC0->EVENTS_COMPARE[0] TIMER0->TASKS_CLEAR
31 RTC0->EVENTS_COMPARE[0] TIMER0->TASKS_START

Registers

Table 3. Instances
Base address Peripheral Instance Description Configuration
0x4001F000 PPI PPI

Programmable peripheral interconnect

   
Table 4. Register Overview
Register Offset Description
TASKS_CHG[0].EN 0x000

Enable channel group 0

 
TASKS_CHG[0].DIS 0x004

Disable channel group 0

 
TASKS_CHG[1].EN 0x008

Enable channel group 1

 
TASKS_CHG[1].DIS 0x00C

Disable channel group 1

 
TASKS_CHG[2].EN 0x010

Enable channel group 2

 
TASKS_CHG[2].DIS 0x014

Disable channel group 2

 
TASKS_CHG[3].EN 0x018

Enable channel group 3

 
TASKS_CHG[3].DIS 0x01C

Disable channel group 3

 
TASKS_CHG[4].EN 0x020

Enable channel group 4

 
TASKS_CHG[4].DIS 0x024

Disable channel group 4

 
TASKS_CHG[5].EN 0x028

Enable channel group 5

 
TASKS_CHG[5].DIS 0x02C

Disable channel group 5

 
CHEN 0x500

Channel enable register

 
CHENSET 0x504

Channel enable set register

 
CHENCLR 0x508

Channel enable clear register

 
CH[0].EEP 0x510

Channel 0 event end-point

 
CH[0].TEP 0x514

Channel 0 task end-point

 
CH[1].EEP 0x518

Channel 1 event end-point

 
CH[1].TEP 0x51C

Channel 1 task end-point

 
CH[2].EEP 0x520

Channel 2 event end-point

 
CH[2].TEP 0x524

Channel 2 task end-point

 
CH[3].EEP 0x528

Channel 3 event end-point

 
CH[3].TEP 0x52C

Channel 3 task end-point

 
CH[4].EEP 0x530

Channel 4 event end-point

 
CH[4].TEP 0x534

Channel 4 task end-point

 
CH[5].EEP 0x538

Channel 5 event end-point

 
CH[5].TEP 0x53C

Channel 5 task end-point

 
CH[6].EEP 0x540

Channel 6 event end-point

 
CH[6].TEP 0x544

Channel 6 task end-point

 
CH[7].EEP 0x548

Channel 7 event end-point

 
CH[7].TEP 0x54C

Channel 7 task end-point

 
CH[8].EEP 0x550

Channel 8 event end-point

 
CH[8].TEP 0x554

Channel 8 task end-point

 
CH[9].EEP 0x558

Channel 9 event end-point

 
CH[9].TEP 0x55C

Channel 9 task end-point

 
CH[10].EEP 0x560

Channel 10 event end-point

 
CH[10].TEP 0x564

Channel 10 task end-point

 
CH[11].EEP 0x568

Channel 11 event end-point

 
CH[11].TEP 0x56C

Channel 11 task end-point

 
CH[12].EEP 0x570

Channel 12 event end-point

 
CH[12].TEP 0x574

Channel 12 task end-point

 
CH[13].EEP 0x578

Channel 13 event end-point

 
CH[13].TEP 0x57C

Channel 13 task end-point

 
CH[14].EEP 0x580

Channel 14 event end-point

 
CH[14].TEP 0x584

Channel 14 task end-point

 
CH[15].EEP 0x588

Channel 15 event end-point

 
CH[15].TEP 0x58C

Channel 15 task end-point

 
CH[16].EEP 0x590

Channel 16 event end-point

 
CH[16].TEP 0x594

Channel 16 task end-point

 
CH[17].EEP 0x598

Channel 17 event end-point

 
CH[17].TEP 0x59C

Channel 17 task end-point

 
CH[18].EEP 0x5A0

Channel 18 event end-point

 
CH[18].TEP 0x5A4

Channel 18 task end-point

 
CH[19].EEP 0x5A8

Channel 19 event end-point

 
CH[19].TEP 0x5AC

Channel 19 task end-point

 
CHG[0] 0x800

Channel group 0

 
CHG[1] 0x804

Channel group 1

 
CHG[2] 0x808

Channel group 2

 
CHG[3] 0x80C

Channel group 3

 
CHG[4] 0x810

Channel group 4

 
CHG[5] 0x814

Channel group 5

 
FORK[0].TEP 0x910

Channel 0 task end-point

 
FORK[1].TEP 0x914

Channel 1 task end-point

 
FORK[2].TEP 0x918

Channel 2 task end-point

 
FORK[3].TEP 0x91C

Channel 3 task end-point

 
FORK[4].TEP 0x920

Channel 4 task end-point

 
FORK[5].TEP 0x924

Channel 5 task end-point

 
FORK[6].TEP 0x928

Channel 6 task end-point

 
FORK[7].TEP 0x92C

Channel 7 task end-point

 
FORK[8].TEP 0x930

Channel 8 task end-point

 
FORK[9].TEP 0x934

Channel 9 task end-point

 
FORK[10].TEP 0x938

Channel 10 task end-point

 
FORK[11].TEP 0x93C

Channel 11 task end-point

 
FORK[12].TEP 0x940

Channel 12 task end-point

 
FORK[13].TEP 0x944

Channel 13 task end-point

 
FORK[14].TEP 0x948

Channel 14 task end-point

 
FORK[15].TEP 0x94C

Channel 15 task end-point

 
FORK[16].TEP 0x950

Channel 16 task end-point

 
FORK[17].TEP 0x954

Channel 17 task end-point

 
FORK[18].TEP 0x958

Channel 18 task end-point

 
FORK[19].TEP 0x95C

Channel 19 task end-point

 
FORK[20].TEP 0x960

Channel 20 task end-point

 
FORK[21].TEP 0x964

Channel 21 task end-point

 
FORK[22].TEP 0x968

Channel 22 task end-point

 
FORK[23].TEP 0x96C

Channel 23 task end-point

 
FORK[24].TEP 0x970

Channel 24 task end-point

 
FORK[25].TEP 0x974

Channel 25 task end-point

 
FORK[26].TEP 0x978

Channel 26 task end-point

 
FORK[27].TEP 0x97C

Channel 27 task end-point

 
FORK[28].TEP 0x980

Channel 28 task end-point

 
FORK[29].TEP 0x984

Channel 29 task end-point

 
FORK[30].TEP 0x988

Channel 30 task end-point

 
FORK[31].TEP 0x98C

Channel 31 task end-point

 

CHEN

Address offset: 0x500

Channel enable register

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id f e d c b a Z Y X W V U T S R Q P O N M L K J I H G F E D C B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

CH0

   

Enable or disable channel 0

     

Disabled

0

Disable channel

     

Enabled

1

Enable channel

B RW

CH1

   

Enable or disable channel 1

     

Disabled

0

Disable channel

     

Enabled

1

Enable channel

C RW

CH2

   

Enable or disable channel 2

     

Disabled

0

Disable channel

     

Enabled

1

Enable channel

D RW

CH3

   

Enable or disable channel 3

     

Disabled

0

Disable channel

     

Enabled

1

Enable channel

E RW

CH4

   

Enable or disable channel 4

     

Disabled

0

Disable channel

     

Enabled

1

Enable channel

F RW

CH5

   

Enable or disable channel 5

     

Disabled

0

Disable channel

     

Enabled

1

Enable channel

G RW

CH6

   

Enable or disable channel 6

     

Disabled

0

Disable channel

     

Enabled

1

Enable channel

H RW

CH7

   

Enable or disable channel 7

     

Disabled

0

Disable channel

     

Enabled

1

Enable channel

I RW

CH8

   

Enable or disable channel 8

     

Disabled

0

Disable channel

     

Enabled

1

Enable channel

J RW

CH9

   

Enable or disable channel 9

     

Disabled

0

Disable channel

     

Enabled

1

Enable channel

K RW

CH10

   

Enable or disable channel 10

     

Disabled

0

Disable channel

     

Enabled

1

Enable channel

L RW

CH11

   

Enable or disable channel 11

     

Disabled

0

Disable channel

     

Enabled

1

Enable channel

M RW

CH12

   

Enable or disable channel 12

     

Disabled

0

Disable channel

     

Enabled

1

Enable channel

N RW

CH13

   

Enable or disable channel 13

     

Disabled

0

Disable channel

     

Enabled

1

Enable channel

O RW

CH14

   

Enable or disable channel 14

     

Disabled

0

Disable channel

     

Enabled

1

Enable channel

P RW

CH15

   

Enable or disable channel 15

     

Disabled

0

Disable channel

     

Enabled

1

Enable channel

Q RW

CH16

   

Enable or disable channel 16

     

Disabled

0

Disable channel

     

Enabled

1

Enable channel

R RW

CH17

   

Enable or disable channel 17

     

Disabled

0

Disable channel

     

Enabled

1

Enable channel

S RW

CH18

   

Enable or disable channel 18

     

Disabled

0

Disable channel

     

Enabled

1

Enable channel

T RW

CH19

   

Enable or disable channel 19

     

Disabled

0

Disable channel

     

Enabled

1

Enable channel

U RW

CH20

   

Enable or disable channel 20

     

Disabled

0

Disable channel

     

Enabled

1

Enable channel

V RW

CH21

   

Enable or disable channel 21

     

Disabled

0

Disable channel

     

Enabled

1

Enable channel

W RW

CH22

   

Enable or disable channel 22

     

Disabled

0

Disable channel

     

Enabled

1

Enable channel

X RW

CH23

   

Enable or disable channel 23

     

Disabled

0

Disable channel

     

Enabled

1

Enable channel

Y RW

CH24

   

Enable or disable channel 24

     

Disabled

0

Disable channel

     

Enabled

1

Enable channel

Z RW

CH25

   

Enable or disable channel 25

     

Disabled

0

Disable channel

     

Enabled

1

Enable channel

a RW

CH26

   

Enable or disable channel 26

     

Disabled

0

Disable channel

     

Enabled

1

Enable channel

b RW

CH27

   

Enable or disable channel 27

     

Disabled

0

Disable channel

     

Enabled

1

Enable channel

c RW

CH28

   

Enable or disable channel 28

     

Disabled

0

Disable channel

     

Enabled

1

Enable channel

d RW

CH29

   

Enable or disable channel 29

     

Disabled

0

Disable channel

     

Enabled

1

Enable channel

e RW

CH30

   

Enable or disable channel 30

     

Disabled

0

Disable channel

     

Enabled

1

Enable channel

f RW

CH31

   

Enable or disable channel 31

     

Disabled

0

Disable channel

     

Enabled

1

Enable channel

 

CHENSET

Address offset: 0x504

Channel enable set register

Read: reads value of CH{i} field in CHEN register.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id f e d c b a Z Y X W V U T S R Q P O N M L K J I H G F E D C B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

CH0

   

Channel 0 enable set register. Writing '0' has no effect

     

Disabled

0

Read: channel disabled

     

Enabled

1

Read: channel enabled

     

Set

1

Write: Enable channel

B RW

CH1

   

Channel 1 enable set register. Writing '0' has no effect

     

Disabled

0

Read: channel disabled

     

Enabled

1

Read: channel enabled

     

Set

1

Write: Enable channel

C RW

CH2

   

Channel 2 enable set register. Writing '0' has no effect

     

Disabled

0

Read: channel disabled

     

Enabled

1

Read: channel enabled

     

Set

1

Write: Enable channel

D RW

CH3

   

Channel 3 enable set register. Writing '0' has no effect

     

Disabled

0

Read: channel disabled

     

Enabled

1

Read: channel enabled

     

Set

1

Write: Enable channel

E RW

CH4

   

Channel 4 enable set register. Writing '0' has no effect

     

Disabled

0

Read: channel disabled

     

Enabled

1

Read: channel enabled

     

Set

1

Write: Enable channel

F RW

CH5

   

Channel 5 enable set register. Writing '0' has no effect

     

Disabled

0

Read: channel disabled

     

Enabled

1

Read: channel enabled

     

Set

1

Write: Enable channel

G RW

CH6

   

Channel 6 enable set register. Writing '0' has no effect

     

Disabled

0

Read: channel disabled

     

Enabled

1

Read: channel enabled

     

Set

1

Write: Enable channel

H RW

CH7

   

Channel 7 enable set register. Writing '0' has no effect

     

Disabled

0

Read: channel disabled

     

Enabled

1

Read: channel enabled

     

Set

1

Write: Enable channel

I RW

CH8

   

Channel 8 enable set register. Writing '0' has no effect

     

Disabled

0

Read: channel disabled

     

Enabled

1

Read: channel enabled

     

Set

1

Write: Enable channel

J RW

CH9

   

Channel 9 enable set register. Writing '0' has no effect

     

Disabled

0

Read: channel disabled

     

Enabled

1

Read: channel enabled

     

Set

1

Write: Enable channel

K RW

CH10

   

Channel 10 enable set register. Writing '0' has no effect

     

Disabled

0

Read: channel disabled

     

Enabled

1

Read: channel enabled

     

Set

1

Write: Enable channel

L RW

CH11

   

Channel 11 enable set register. Writing '0' has no effect

     

Disabled

0

Read: channel disabled

     

Enabled

1

Read: channel enabled

     

Set

1

Write: Enable channel

M RW

CH12

   

Channel 12 enable set register. Writing '0' has no effect

     

Disabled

0

Read: channel disabled

     

Enabled

1

Read: channel enabled

     

Set

1

Write: Enable channel

N RW

CH13

   

Channel 13 enable set register. Writing '0' has no effect

     

Disabled

0

Read: channel disabled

     

Enabled

1

Read: channel enabled

     

Set

1

Write: Enable channel

O RW

CH14

   

Channel 14 enable set register. Writing '0' has no effect

     

Disabled

0

Read: channel disabled

     

Enabled

1

Read: channel enabled

     

Set

1

Write: Enable channel

P RW

CH15

   

Channel 15 enable set register. Writing '0' has no effect

     

Disabled

0

Read: channel disabled

     

Enabled

1

Read: channel enabled

     

Set

1

Write: Enable channel

Q RW

CH16

   

Channel 16 enable set register. Writing '0' has no effect

     

Disabled

0

Read: channel disabled

     

Enabled

1

Read: channel enabled

     

Set

1

Write: Enable channel

R RW

CH17

   

Channel 17 enable set register. Writing '0' has no effect

     

Disabled

0

Read: channel disabled

     

Enabled

1

Read: channel enabled

     

Set

1

Write: Enable channel

S RW

CH18

   

Channel 18 enable set register. Writing '0' has no effect

     

Disabled

0

Read: channel disabled

     

Enabled

1

Read: channel enabled

     

Set

1

Write: Enable channel

T RW

CH19

   

Channel 19 enable set register. Writing '0' has no effect

     

Disabled

0

Read: channel disabled

     

Enabled

1

Read: channel enabled

     

Set

1

Write: Enable channel

U RW

CH20

   

Channel 20 enable set register. Writing '0' has no effect

     

Disabled

0

Read: channel disabled

     

Enabled

1

Read: channel enabled

     

Set

1

Write: Enable channel

V RW

CH21

   

Channel 21 enable set register. Writing '0' has no effect

     

Disabled

0

Read: channel disabled

     

Enabled

1

Read: channel enabled

     

Set

1

Write: Enable channel

W RW

CH22

   

Channel 22 enable set register. Writing '0' has no effect

     

Disabled

0

Read: channel disabled

     

Enabled

1

Read: channel enabled

     

Set

1

Write: Enable channel

X RW

CH23

   

Channel 23 enable set register. Writing '0' has no effect

     

Disabled

0

Read: channel disabled

     

Enabled

1

Read: channel enabled

     

Set

1

Write: Enable channel

Y RW

CH24

   

Channel 24 enable set register. Writing '0' has no effect

     

Disabled

0

Read: channel disabled

     

Enabled

1

Read: channel enabled

     

Set

1

Write: Enable channel

Z RW

CH25

   

Channel 25 enable set register. Writing '0' has no effect

     

Disabled

0

Read: channel disabled

     

Enabled

1

Read: channel enabled

     

Set

1

Write: Enable channel

a RW

CH26

   

Channel 26 enable set register. Writing '0' has no effect

     

Disabled

0

Read: channel disabled

     

Enabled

1

Read: channel enabled

     

Set

1

Write: Enable channel

b RW

CH27

   

Channel 27 enable set register. Writing '0' has no effect

     

Disabled

0

Read: channel disabled

     

Enabled

1

Read: channel enabled

     

Set

1

Write: Enable channel

c RW

CH28

   

Channel 28 enable set register. Writing '0' has no effect

     

Disabled

0

Read: channel disabled

     

Enabled

1

Read: channel enabled

     

Set

1

Write: Enable channel

d RW

CH29

   

Channel 29 enable set register. Writing '0' has no effect

     

Disabled

0

Read: channel disabled

     

Enabled

1

Read: channel enabled

     

Set

1

Write: Enable channel

e RW

CH30

   

Channel 30 enable set register. Writing '0' has no effect

     

Disabled

0

Read: channel disabled

     

Enabled

1

Read: channel enabled

     

Set

1

Write: Enable channel

f RW

CH31

   

Channel 31 enable set register. Writing '0' has no effect

     

Disabled

0

Read: channel disabled

     

Enabled

1

Read: channel enabled

     

Set

1

Write: Enable channel

 

CHENCLR

Address offset: 0x508

Channel enable clear register

Read: reads value of CH{i} field in CHEN register.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id f e d c b a Z Y X W V U T S R Q P O N M L K J I H G F E D C B A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

CH0

   

Channel 0 enable clear register. Writing '0' has no effect

     

Disabled

0

Read: channel disabled

     

Enabled

1

Read: channel enabled

     

Clear

1

Write: disable channel

B RW

CH1

   

Channel 1 enable clear register. Writing '0' has no effect

     

Disabled

0

Read: channel disabled

     

Enabled

1

Read: channel enabled

     

Clear

1

Write: disable channel

C RW

CH2

   

Channel 2 enable clear register. Writing '0' has no effect

     

Disabled

0

Read: channel disabled

     

Enabled

1

Read: channel enabled

     

Clear

1

Write: disable channel

D RW

CH3

   

Channel 3 enable clear register. Writing '0' has no effect

     

Disabled

0

Read: channel disabled

     

Enabled

1

Read: channel enabled

     

Clear

1

Write: disable channel

E RW

CH4

   

Channel 4 enable clear register. Writing '0' has no effect

     

Disabled

0

Read: channel disabled

     

Enabled

1

Read: channel enabled

     

Clear

1

Write: disable channel

F RW

CH5

   

Channel 5 enable clear register. Writing '0' has no effect

     

Disabled

0

Read: channel disabled

     

Enabled

1

Read: channel enabled

     

Clear

1

Write: disable channel

G RW

CH6

   

Channel 6 enable clear register. Writing '0' has no effect

     

Disabled

0

Read: channel disabled

     

Enabled

1

Read: channel enabled

     

Clear

1

Write: disable channel

H RW

CH7

   

Channel 7 enable clear register. Writing '0' has no effect

     

Disabled

0

Read: channel disabled

     

Enabled

1

Read: channel enabled

     

Clear

1

Write: disable channel

I RW

CH8

   

Channel 8 enable clear register. Writing '0' has no effect

     

Disabled

0

Read: channel disabled

     

Enabled

1

Read: channel enabled

     

Clear

1

Write: disable channel

J RW

CH9

   

Channel 9 enable clear register. Writing '0' has no effect

     

Disabled

0

Read: channel disabled

     

Enabled

1

Read: channel enabled

     

Clear

1

Write: disable channel

K RW

CH10

   

Channel 10 enable clear register. Writing '0' has no effect

     

Disabled

0

Read: channel disabled

     

Enabled

1

Read: channel enabled

     

Clear

1

Write: disable channel

L RW

CH11

   

Channel 11 enable clear register. Writing '0' has no effect

     

Disabled

0

Read: channel disabled

     

Enabled

1

Read: channel enabled

     

Clear

1

Write: disable channel

M RW

CH12

   

Channel 12 enable clear register. Writing '0' has no effect

     

Disabled

0

Read: channel disabled

     

Enabled

1

Read: channel enabled

     

Clear

1

Write: disable channel

N RW

CH13

   

Channel 13 enable clear register. Writing '0' has no effect

     

Disabled

0

Read: channel disabled

     

Enabled

1

Read: channel enabled

     

Clear

1

Write: disable channel

O RW

CH14

   

Channel 14 enable clear register. Writing '0' has no effect

     

Disabled

0

Read: channel disabled

     

Enabled

1

Read: channel enabled

     

Clear

1

Write: disable channel

P RW

CH15

   

Channel 15 enable clear register. Writing '0' has no effect

     

Disabled

0

Read: channel disabled

     

Enabled

1

Read: channel enabled

     

Clear

1

Write: disable channel

Q RW

CH16

   

Channel 16 enable clear register. Writing '0' has no effect

     

Disabled

0

Read: channel disabled

     

Enabled

1

Read: channel enabled

     

Clear

1

Write: disable channel

R RW

CH17

   

Channel 17 enable clear register. Writing '0' has no effect

     

Disabled

0

Read: channel disabled

     

Enabled

1

Read: channel enabled

     

Clear

1

Write: disable channel

S RW

CH18

   

Channel 18 enable clear register. Writing '0' has no effect

     

Disabled

0

Read: channel disabled

     

Enabled

1

Read: channel enabled

     

Clear

1

Write: disable channel

T RW

CH19

   

Channel 19 enable clear register. Writing '0' has no effect

     

Disabled

0

Read: channel disabled

     

Enabled

1

Read: channel enabled

     

Clear

1

Write: disable channel

U RW

CH20

   

Channel 20 enable clear register. Writing '0' has no effect

     

Disabled

0

Read: channel disabled

     

Enabled

1

Read: channel enabled

     

Clear

1

Write: disable channel

V RW

CH21

   

Channel 21 enable clear register. Writing '0' has no effect

     

Disabled

0

Read: channel disabled

     

Enabled

1

Read: channel enabled

     

Clear

1

Write: disable channel

W RW

CH22

   

Channel 22 enable clear register. Writing '0' has no effect

     

Disabled

0

Read: channel disabled

     

Enabled

1

Read: channel enabled

     

Clear

1

Write: disable channel

X RW

CH23

   

Channel 23 enable clear register. Writing '0' has no effect

     

Disabled

0

Read: channel disabled

     

Enabled

1

Read: channel enabled

     

Clear

1

Write: disable channel

Y RW

CH24

   

Channel 24 enable clear register. Writing '0' has no effect

     

Disabled

0

Read: channel disabled

     

Enabled

1

Read: channel enabled

     

Clear

1

Write: disable channel

Z RW

CH25

   

Channel 25 enable clear register. Writing '0' has no effect

     

Disabled

0

Read: channel disabled

     

Enabled

1

Read: channel enabled

     

Clear

1