NFCT — Near field communication tag

The NFCT peripheral is an implementation of an NFC Forum compliant listening device NFC-A.

With appropriate software, the NFCT peripheral can be used as the listening device NFC-A as specified by the NFC Forum.

Listed here are the main features for the NFCT peripheral:

Figure 1. NFCT block diagram

Overview

The NFCT peripheral contains a 13.56 MHz AM receiver and a 13.56 MHz load modulator with 106 kbps data rate as defined by the NFC Forum.

Figure 2. NFCT overview

When transmitting, the frame data will be transferred directly from RAM and transmitted with configurable frame type and delay timing. The system will be notified by an event whenever a complete frame is received or sent. The received frames will be automatically disassembled and the data part of the frame transferred to RAM.

The NFCT peripheral also supports the collision detection and resolution ("anticollision") as defined by the NFC Forum.

Wake-on-field is supported in SENSE mode while the device is either in System OFF or System ON mode. When the antenna enters an NFC field, an event will be triggered notifying the system to activate the NFCT functionality for incoming frames. In System ON, if the energy detected at the antenna increases beyond a threshold value, the module will generate a FIELDDETECTED event. When the strength of the field no longer supports NFC communication, the module will generate a FIELDLOST event. For the Low Power Field Detect threshold values, refer to NFCT Electrical Specification.

In System OFF, the NFCT Low Power Field Detect function can wake the system up through a reset. The NFC bit in the RESETREAS register in POWER — Power supply will be set as the cause of the wake-up.

If the system is put into System OFF mode while a field is already present, the NFCT Low Power Field Detect function will wake the system up right away and generate a reset.

Important: As a consequence of a reset, NFCT is disabled, and therefore the reset handler will have to activate NFCT again and set it up properly.

The HFXO must be running before the NFCT peripheral goes into ACTIVATED state. Note that the NFCT peripheral calibration is automatically done on ACTIVATE task. The HFXO can be turned off when the NFCT peripheral goes into SENSE mode. The shortcut FIELDDETECTED_ACTIVATE can be used when the HFXO is already running while in SENSE mode.

Outgoing data will be collected from RAM with the EasyDMA function and assembled according to theTXD.FRAMECONFIG register. Incoming data will be disassembled according to the RXD.FRAMECONFIG register and the data section in the frame will be written to RAM via the EasyDMA function.

The NFCT peripheral includes a frame timing controller that can be used to accurately control the inter-frame delay between the incoming frame and a corresponding outgoing frame. It also includes optional CRC functionality.

Operating states

Tasks and events are used to control the operating state of the peripheral. The module can change state by triggering a task, or when specific operations are finalized. Events and tasks allow software to keep track of and change the current state.

See Figure 1 and Figure 3 for more information.

Figure 3. NFCT state diagram, automatic collision resolution enabled

Figure 4. NFCT state diagram, automatic collision resolution disabled

Important:
  • FIELDLOST event will not be reflected in the state machine (for instance by going back to the DISABLE state). It is up to software to decide on the actions to take when a field lost occurs.
  • FIELDLOST event is not generated in SENSE mode.
  • Sending SENSE task while field is still present does not generate FIELDDETECTED event.
  • If the FIELDDETECTED event is cleared before sending the ACTIVATE task, then the FIELDDETECTED event shows up again after sending the ACTIVATE task. The shortcut FIELDDETECTED_ACTIVATE can be used to avoid this condition.

Pin configuration

NFCT uses two pins to connect the antenna and these pins are shared with GPIOs.

The PROTECT field in the NFCPINS register in UICR defines the usage of these pins and their protection level against excessive voltages. The content of the NFCPINS register is reloaded at every reset. See Pin assignments for the pins used by the NFCT peripheral.

When NFCPINS.PROTECT=NFC, a protection circuit will be enabled on the dedicated pins, preventing the chip from being damaged in the presence of a strong NFC field. The protection circuit will short the two pins together if voltage difference exceeds approximately 2V. The GPIO function on those pins will also be disabled.

When NFCPINS.PROTECT=Disabled, the device will not be protected against strong NFC field damages caught by a connected NFCT antenna, and the NFCT peripheral will not operate as expected, as it will never leave the DISABLE state.

The pins dedicated to the NFCT antenna function will have some limitation when the pins are configured for normal GPIO operation. The pin capacitance will be higher on those (refer to CPAD_NFC in the Electrical Specification of GPIO — General purpose input/output), and some increased leakage current between the two pins is to be expected if they are used in GPIO mode, and are driven to different logical values. To save power, the two pins should always be set to the same logical value whenever entering one of the device power saving modes. For details, refer to INFC_LEAK in the Electrical Specification of GPIO — General purpose input/output.

EasyDMA

The NFCT peripheral implements EasyDMA for reading and writing of data packets from and to the Data RAM.

The NFCT EasyDMA utilizes a pointer called PACKETPTR for receiving and transmitting packets.

The NFCT peripheral uses EasyDMA to read or write RAM, but not both at the same time. The event RXFRAMESTART indicates that the EasyDMA has started writing to the RAM for a receive frame and the event RXFRAMEND indicates that the EasyDMA has completed writing to the RAM. Similarly, the event TXFRAMESTART indicates that the EasyDMA has started reading from the RAM for a transmit frame and the event TXFRAMEND indicates that the EasyDMA has completed reading from the RAM. If a transmit and a receive operation is issued at the same time, the transmit operation would be prioritized.

Starting a transmit operation while the EasyDMA is writing a receive frame to the RAM will result in unpredictable behavior. Starting an EasyDMA operation when there is an ongoing EasyDMA operation may result in unpredictable behavior. It is recommended to wait for the TXFRAMEEND or RXFRAMEEND event for the ongoing transmit or receive before starting a new receive or transmit operation.

The MAXLEN register determines the maximum number of bytes that can be read from or written to the RAM. This feature can be used to ensure that the NFCT peripheral does not overwrite, or read beyond, the RAM assigned to a packet. Note that if the RXD.AMOUNT or TXD.AMOUNT register indicates longer data packets than set in MAXLEN, the frames sent to or received from the physical layer will be incomplete. In that situation, in RX, the OVERRUN bit in the FRAMESTATUS.RX register will be set and an RXERROR event will be triggered.

Important: The RXD.AMOUNT and TXD.AMOUNT define a frame length in bytes and bits excluding start of frame (SoF), end of frame (EoF), and parity, but including CRC for RXD.AMOUNT only. Make sure to take potential additional bits into account when setting MAXLEN.

Only sending task ENABLERXDATA ensures that a new value in PACKETPTR pointing to the RX buffer in Data RAM is taken into account.

If PACKETPTR is not pointing to the Data RAM region, an EasyDMA transfer may result in a hard fault or RAM corruption. For more information about the different memory regions, see Chapter Memory.

The NFCT peripherals normally do alternative receive and transmit frames. Therefore, to prepare for the next frame, the PACKETPTR, MAXLEN, TXD.FRAMECONFIG and TXD.AMOUNT can be updated while the receive is in progress, and, similarly, the PACKETPTR, MAXLEN and RXD.FRAMECONFIG can be updated while the transmit is in progress. They can be updated and prepared for the next NFC frame immediately after the STARTED event of the current frame has been received. Updating the TXD.FRAMECONFIG and TXD.AMOUNT during the current transmit frame or updating RXD.FRAMECONFIG during current receive frame may cause unpredictable behaviour.

In accordance with NFC Forum, NFC Digital Protocol Technical Specification, the least significant bit (LSB) from the least significant byte (LSByte) is sent on air first. The bytes are stored in increasing order, starting at the lowest address in the EasyDMA buffer in RAM.

Frame assembler

The NFCT peripheral implements a frame assembler in hardware.

When the NFCT peripheral is in the ACTIVE_A state, the software can decide to enter RX or TX mode. For RX, see Frame disassembler. For TX, the software must indicate the address of the source buffer in Data RAM and its size through programming the PACKETPTR and MAXLEN registers respectively, then issuing a STARTTX task.

MAXLEN must be set so that it matches the size of the frame to be sent.

The STARTED event indicates that the PACKETPTR and MAXLEN registers have been captured by the frame assembler EasyDMA.

When asserting the STARTTX task, the frame assembler module will start reading TXD.AMOUNT.TXDATABYTES bytes (plus one additional byte if TXD.AMOUNT.TXDATABITS > 0) from the RAM position set by the PACKETPTR.

The NFCT peripheral transmits the data as read from RAM, adding framing and the CRC calculated on the fly if set in TXD.FRAMECONFIG. The NFCT peripheral will take (8*TXD.AMOUNT.TXDATABYTES + TXD.AMOUNT.TXDATABITS) bits and assemble a frame according to the settings in TXD.FRAMECONFIG. Both short frames, standard frames, and bit-oriented SDD frames as specified in the NFC Forum, NFC Digital Protocol Technical Specification can be assembled by the correct setting of the TXD.FRAMECONFIG register.

The bytes will be transmitted on air in the same order as they are read from RAM with a rising bit order within each byte, least significant bit (LSB) first. That is, b0 will be transmitted on air before b1, and so on. The bits read from RAM will be coded into symbols as defined in the NFC Forum, NFC Digital Protocol Technical Specification.

Important: Some NFC Forum documents, such as NFC Forum, NFC Digital Protocol Technical Specification, define bit numbering in a byte from b1 (LSB) to b8 (most significant bit (MSB)), while most other technical documents from the NFC Forum, and also the Nordic Semiconductor documentation, traditionally number them from b0 to b7. The present document uses the b0–b7 numbering scheme. Be aware of this when comparing the NFC Forum, NFC Digital Protocol Technical Specification to others.

The frame assembler can be configured in TXD.FRAMECONFIG to add SoF symbol, calculate and add parity bits, and calculate and add CRC to the data read from RAM when assembling the frame. The total frame will then be longer than what is defined by TXD.AMOUNT.TXDATABYTES. TXDATABITS. DISCARDMODE will select if the first bits in the first byte read from RAM or the last bits in the last byte read from RAM will be discarded if TXD.AMOUNT.TXDATABITS are not equal to zero. Note that if TXD.FRAMECONFIG.PARITY = Parity and TXD.FRAMECONFIG.DISCARDMODE=DiscardStart, a parity bit will be included after the non-complete first byte. No parity will be added after a non-complete last byte.

The frame assemble operation is illustrated in Figure 5 for different settings in TXD.FRAMECONFIG. All shaded bit fields are added by the frame assembler. Some of these bits are optional and appearances are configured in TXD.FRAMECONFIG. Note that the frames illustrated do not necessarily comply with the NFC specification. The figure is only to illustrate the behavior of the NFCT peripheral.

Figure 5. Frame assemble illustration

The accurate timing for transmitting the frame on air is set using the frame timing controller settings.

Frame disassembler

The NFCT peripheral implements a frame disassembler in hardware.

When the NFCT peripheral is in the ACTIVE_A state, the software can decide to enter RX or TX mode. For TX, see Frame assembler. For RX, the software must indicate the address and size of the destination buffer in Data RAM through programming the PACKETPTR and MAXLEN registers before issuing an ENABLERXDATA task.

The STARTED event indicates that the PACKETPTR and MAXLEN registers have been captured by the frame disassembler EasyDMA.

When an incoming frame starts, the RXFRAMESTART event will get issued and data will be written to the buffer in Data RAM. The frame disassembler will verify and remove any parity bits, start of frame (SoF) and end of frame (EoF) symbols on the fly based on RXD.FRAMECONFIG register configuration. It will, however, verify and transfer the CRC bytes into RAM, if the CRC is enabled through RXD.FRAMECONFIG.

When an EoF symbol is detected, the NFCT peripheral will assert the RXFRAMEEND event and write the RXD.AMOUNT register to indicate numbers of received bytes and bits in the data packet. The module does not interpret the content of the data received from the remote NFC device, except for SoF, EoF, parity, and CRC checking, as described above. The frame disassemble operation is illustrated below.

Figure 6. Frame disassemble illustration

Per NFC specification, the time between EoF to the next SoF can be as short as 86 μs, and thefore care must be taken that PACKETPTR and MAXLEN are ready and ENABLERXDATA is issued on time after the end of previous frame. The use of a PPI shortcut from TXFRAMEEND to ENABLERXDATA is recommended.

Frame timing controller

The NFCT peripheral includes a frame timing controller that continuously keeps track of the number of the 13.56 MHz RF carrier clock periods since the end of the EoF of the last received frame.

The NFCT peripheral can be programmed to send a responding frame within a time window or at an exact count of RF carrier periods. In case of FRAMEDELAYMODE = Window, a STARTTX task triggered before the frame timing controller counter is equal to FRAMEDELAYMIN will force the transmission to halt until the counter is equal to FRAMEDELAYMIN. If the counter is within FRAMEDELAYMIN and FRAMEDELAYMAX when the STARTTX task is triggered, the NFCT peripheral will start the transmission straight away. In case of FRAMEDELAYMODE = ExactVal, a STARTTX task triggered before the frame delay counter is equal to FRAMEDELAYMAX will halt the actual transmission start until the counter is equal to FRAMEDELAYMAX.

In case of FRAMEDELAYMODE = WindowGrid, the behaviour is similar to the FRAMEDELAYMODE = Window, but the actual transmission between FRAMEDELAYMIN and FRAMEDELAYMAX starts on a bit grid as defined for NFC-A Listen frames (slot duration of 128 RF carrier periods).

An ERROR event (with FRAMEDELAYTIMEOUT cause in ERRORSTATUS) will be asserted if the frame timing controller counter reaches FRAMEDELAYMAX without any STARTTX task triggered. This may happen even when the response is not required as per NFC Forum, NFC Digital Protocol Technical Specification. Any commands handled by the automatic collision resolution that don't involve a response being generated may also result in an ERROR event (with FRAMEDELAYTIMEOUT cause in ERRORSTATUS). The FRAMEDELAYMIN and FRAMEDELAYMAX values shall only be updated before the STARTTX task is triggered. Failing to do so may cause unpredictable behaviour.

The frame timing controller operation is illustrated in Figure 7. The frame timing controller automatically adjusts the frame timing counter based on the last received data bit according to NFC-A technology in the NFC Forum, NFC Digital Protocol Technical Specification.

Figure 7. Frame timing controller (FRAMEDELAYMODE=Window)

Collision resolution

The NFCT peripheral implements an automatic collision resolution function as defined by the NFC Forum.

Automatic collision resolution is enabled by default, and it is recommended that the feature is used since it is power efficient and reduces the complexity of software handling the collision resolution sequence. This feature can be disabled through the MODE field in the AUTOCOLRESCONFIG register. When the automatic collision resolution is disabled, all commands will be sent over EasyDMA as defined in frame disassembler.

The SENSRES and SELRES registers need to be programmed upfront in order for the collision resolution to behave correctly. Depending on the NFCIDSIZE field in SENSRES, the following registers also need to be programmed upfront:
  • NFCID1_LAST if NFCID1SIZE=NFCID1Single (ID = 4 bytes);
  • NFCID1_2ND_LAST and NFCID1_LAST if NFCID1SIZE=NFCID1Double (ID = 7 bytes);
  • NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST if NFCID1SIZE=NFCID1Triple (ID = 10 bytes);

A pre-defined set of registers, NFC.TAGHEADER0..3, containing a valid NFCID1 value, is available in FICR and can be used by software to populate the NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST registers.

Table 1 explains the position of the ID bytes in NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST, depending on the ID size, and as compared to the definition used in the NFC Forum, NFC Digital Protocol Technical Specification.

Table 1. NFCID1 byte allocation (top sent first on air)
  ID = 4 bytes ID = 7 bytes ID = 10 bytes
NFCID1_Q     nfcid10
NFCID1_R     nfcid11
NFCID1_S     nfcid12
NFCID1_T   nfcid10 nfcid13
NFCID1_U   nfcid11 nfcid14
NFCID1_V   nfcid12 nfcid15
NFCID1_W nfcid10 nfcid13 nfcid16
NFCID1_X nfcid11 nfcid14 nfcid17
NFCID1_Y nfcid12 nfcid15 nfcid18
NFCID1_Z nfcid13 nfcid16 nfcid19

The hardware implementation can handle the states from IDLE to ACTIVE_A automatically as defined in the NFC Forum, NFC Activity Technical Specification, and the other states are to be handled by software. The software keeps track of the state through events. The collision resolution will trigger an AUTOCOLRESSTARTED event when it has started. Reaching the ACTIVE_A state is indicated by the SELECTED event.

If collision resolution fails, a COLLISION event is triggered. Note that errors occurring during automatic collision resolution may also cause ERROR and/or RXERROR events to be generated. Other events may also get generated. It is recommended that the software ignores any event except COLLISION, SELECTED and FIELDLOST during automatic collision resolution. Software shall also make sure that any unwanted SHORT or PPI shortcut is disabled during automatic collision resolution.

The automatic collision resolution will be restarted, if the packets are received with CRC or parity errors while in ACTIVE_A state. The automatic collision resolution feature can be disabled while in ACTIVE_A state to avoid this.

The SLP_REQ is automatically handled by the NFCT peripheral when the automatic collision resolution is enabled. However, this results in an ERROR event (with FRAMEDELAYTIMEOUT cause in ERRORSTATUS) since the SLP_REQ has no response. This error must be ignored until the SELECTED event is triggered and this error should be cleared by the software when the SELECTED event is triggered.

Antenna interface

In ACTIVATED state, an amplitude regulator will adjust the voltage swing on the antenna pins to a value that is within the Vswing limit.

Refer to NFCT Electrical Specification.

NFCT antenna recommendations

The NFCT antenna coil must be connected differential between NFC1 and NFC2 pins of the device.

Two external capacitors should be used to tune the resonance of the antenna circuit to 13.56 MHz.

Figure 8. NFCT antenna recommendations

The required tuning capacitor value is given by the below equations:


Equations for calculating the required tuning capacitor value

An antenna inductance of Lant = 2 μH will give tuning capacitors in the range of 130 pF on each pin. The total capacitance on NFC1 and NFC2 must be matched.

Battery protection

If the antenna is exposed to a strong NFC field, current may flow in the opposite direction on the supply due to parasitic diodes and ESD structures.

If the battery used does not tolerate return current, a series diode must be placed between the battery and the device in order to protect the battery.

References

NFC Forum, NFC Analog Specification version 1.0, www.nfc-forum.org

NFC Forum, NFC Digital Protocol Technical Specification version 1.1, www.nfc-forum.org

NFC Forum, NFC Activity Technical Specification version 1.1, www.nfc-forum.org

Registers

Table 2. Instances
Base address Peripheral Instance Description Configuration
0x40005000 NFCT NFCT

Near field communication tag

   
Table 3. Register Overview
Register Offset Description
TASKS_ACTIVATE 0x000

Activate NFCT peripheral for incoming and outgoing frames, change state to activated

 
TASKS_DISABLE 0x004

Disable NFCT peripheral

 
TASKS_SENSE 0x008

Enable NFC sense field mode, change state to sense mode

 
TASKS_STARTTX 0x00C

Start transmission of an outgoing frame, change state to transmit

 
TASKS_ENABLERXDATA 0x01C

Initializes the EasyDMA for receive.

 
TASKS_GOIDLE 0x024

Force state machine to IDLE state

 
TASKS_GOSLEEP 0x028

Force state machine to SLEEP_A state

 
EVENTS_READY 0x100

The NFCT peripheral is ready to receive and send frames

 
EVENTS_FIELDDETECTED 0x104

Remote NFC field detected

 
EVENTS_FIELDLOST 0x108

Remote NFC field lost

 
EVENTS_TXFRAMESTART 0x10C

Marks the start of the first symbol of a transmitted frame

 
EVENTS_TXFRAMEEND 0x110

Marks the end of the last transmitted on-air symbol of a frame

 
EVENTS_RXFRAMESTART 0x114

Marks the end of the first symbol of a received frame

 
EVENTS_RXFRAMEEND 0x118

Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer

 
EVENTS_ERROR 0x11C

NFC error reported. The ERRORSTATUS register contains details on the source of the error.

 
EVENTS_RXERROR 0x128

NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error.

 
EVENTS_ENDRX 0x12C

RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full.

 
EVENTS_ENDTX 0x130

Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer

 
EVENTS_AUTOCOLRESSTARTED 0x138

Auto collision resolution process has started

 
EVENTS_COLLISION 0x148

NFC auto collision resolution error reported.

 
EVENTS_SELECTED 0x14C

NFC auto collision resolution successfully completed

 
EVENTS_STARTED 0x150

EasyDMA is ready to receive or send frames.

 
SHORTS 0x200

Shortcut register

 
INTEN 0x300

Enable or disable interrupt

 
INTENSET 0x304

Enable interrupt

 
INTENCLR 0x308

Disable interrupt

 
ERRORSTATUS 0x404

NFC Error Status register

 
FRAMESTATUS.RX 0x40C

Result of last incoming frame

 
NFCTAGSTATE 0x410

NfcTag state register

 
FIELDPRESENT 0x43C

Indicates the presence or not of a valid field

 
FRAMEDELAYMIN 0x504

Minimum frame delay

 
FRAMEDELAYMAX 0x508

Maximum frame delay

 
FRAMEDELAYMODE 0x50C

Configuration register for the Frame Delay Timer

 
PACKETPTR 0x510

Packet pointer for TXD and RXD data storage in Data RAM

 
MAXLEN 0x514

Size of the RAM buffer allocated to TXD and RXD data storage each

 
TXD.FRAMECONFIG 0x518

Configuration of outgoing frames

 
TXD.AMOUNT 0x51C

Size of outgoing frame

 
RXD.FRAMECONFIG 0x520

Configuration of incoming frames

 
RXD.AMOUNT 0x524

Size of last incoming frame

 
NFCID1_LAST 0x590

Last NFCID1 part (4, 7 or 10 bytes ID)

 
NFCID1_2ND_LAST 0x594

Second last NFCID1 part (7 or 10 bytes ID)

 
NFCID1_3RD_LAST 0x598

Third last NFCID1 part (10 bytes ID)

 
AUTOCOLRESCONFIG 0x59C

Controls the auto collision resolution function. This setting must be done before the NFCT peripheral is enabled.

 
SENSRES 0x5A0

NFC-A SENS_RES auto-response settings

 
SELRES 0x5A4

NFC-A SEL_RES auto-response settings

 

SHORTS

Address offset: 0x200

Shortcut register

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                                  

F

B

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

FIELDDETECTED_ACTIVATE

   

Shortcut between FIELDDETECTED event and ACTIVATE task

See EVENTS_FIELDDETECTED and TASKS_ACTIVATE

     

Disabled

0

Disable shortcut

     

Enabled

1

Enable shortcut

B RW

FIELDLOST_SENSE

   

Shortcut between FIELDLOST event and SENSE task

See EVENTS_FIELDLOST and TASKS_SENSE

     

Disabled

0

Disable shortcut

     

Enabled

1

Enable shortcut

F RW

TXFRAMEEND_ENABLERXDATA

   

Shortcut between TXFRAMEEND event and ENABLERXDATA task

See EVENTS_TXFRAMEEND and TASKS_ENABLERXDATA

     

Disabled

0

Disable shortcut

     

Enabled

1

Enable shortcut

 

INTEN

Address offset: 0x300

Enable or disable interrupt

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                      

T

S

R

N

 

M

L

K

H

G

F

E

D

C

B

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

READY

   

Enable or disable interrupt for READY event

See EVENTS_READY

     

Disabled

0

Disable

     

Enabled

1

Enable

B RW

FIELDDETECTED

   

Enable or disable interrupt for FIELDDETECTED event

See EVENTS_FIELDDETECTED

     

Disabled

0

Disable

     

Enabled

1

Enable

C RW

FIELDLOST

   

Enable or disable interrupt for FIELDLOST event

See EVENTS_FIELDLOST

     

Disabled

0

Disable

     

Enabled

1

Enable

D RW

TXFRAMESTART

   

Enable or disable interrupt for TXFRAMESTART event

See EVENTS_TXFRAMESTART

     

Disabled

0

Disable

     

Enabled

1

Enable

E RW

TXFRAMEEND

   

Enable or disable interrupt for TXFRAMEEND event

See EVENTS_TXFRAMEEND

     

Disabled

0

Disable

     

Enabled

1

Enable

F RW

RXFRAMESTART

   

Enable or disable interrupt for RXFRAMESTART event

See EVENTS_RXFRAMESTART

     

Disabled

0

Disable

     

Enabled

1

Enable

G RW

RXFRAMEEND

   

Enable or disable interrupt for RXFRAMEEND event

See EVENTS_RXFRAMEEND

     

Disabled

0

Disable

     

Enabled

1

Enable

H RW

ERROR

   

Enable or disable interrupt for ERROR event

See EVENTS_ERROR

     

Disabled

0

Disable

     

Enabled

1

Enable

K RW

RXERROR

   

Enable or disable interrupt for RXERROR event

See EVENTS_RXERROR

     

Disabled

0

Disable

     

Enabled

1

Enable

L RW

ENDRX

   

Enable or disable interrupt for ENDRX event

See EVENTS_ENDRX

     

Disabled

0

Disable

     

Enabled

1

Enable

M RW

ENDTX

   

Enable or disable interrupt for ENDTX event

See EVENTS_ENDTX

     

Disabled

0

Disable

     

Enabled

1

Enable

N RW

AUTOCOLRESSTARTED

   

Enable or disable interrupt for AUTOCOLRESSTARTED event

See EVENTS_AUTOCOLRESSTARTED

     

Disabled

0

Disable

     

Enabled

1

Enable

R RW

COLLISION

   

Enable or disable interrupt for COLLISION event

See EVENTS_COLLISION

     

Disabled

0

Disable

     

Enabled

1

Enable

S RW

SELECTED

   

Enable or disable interrupt for SELECTED event

See EVENTS_SELECTED

     

Disabled

0

Disable

     

Enabled

1

Enable

T RW

STARTED

   

Enable or disable interrupt for STARTED event

See EVENTS_STARTED

     

Disabled

0

Disable

     

Enabled

1

Enable

 

INTENSET

Address offset: 0x304

Enable interrupt

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                      

T

S

R

N

 

M

L

K

H

G

F

E

D

C

B

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

READY

   

Write '1' to Enable interrupt for READY event

See EVENTS_READY

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

B RW

FIELDDETECTED

   

Write '1' to Enable interrupt for FIELDDETECTED event

See EVENTS_FIELDDETECTED

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

C RW

FIELDLOST

   

Write '1' to Enable interrupt for FIELDLOST event

See EVENTS_FIELDLOST

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

D RW

TXFRAMESTART

   

Write '1' to Enable interrupt for TXFRAMESTART event

See EVENTS_TXFRAMESTART

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

E RW

TXFRAMEEND

   

Write '1' to Enable interrupt for TXFRAMEEND event

See EVENTS_TXFRAMEEND

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

F RW

RXFRAMESTART

   

Write '1' to Enable interrupt for RXFRAMESTART event

See EVENTS_RXFRAMESTART

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

G RW

RXFRAMEEND

   

Write '1' to Enable interrupt for RXFRAMEEND event

See EVENTS_RXFRAMEEND

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

H RW

ERROR

   

Write '1' to Enable interrupt for ERROR event

See EVENTS_ERROR

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

K RW

RXERROR

   

Write '1' to Enable interrupt for RXERROR event

See EVENTS_RXERROR

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

L RW

ENDRX

   

Write '1' to Enable interrupt for ENDRX event

See EVENTS_ENDRX

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

M RW

ENDTX

   

Write '1' to Enable interrupt for ENDTX event

See EVENTS_ENDTX

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

N RW

AUTOCOLRESSTARTED

   

Write '1' to Enable interrupt for AUTOCOLRESSTARTED event

See EVENTS_AUTOCOLRESSTARTED

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

R RW

COLLISION

   

Write '1' to Enable interrupt for COLLISION event

See EVENTS_COLLISION

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

S RW

SELECTED

   

Write '1' to Enable interrupt for SELECTED event

See EVENTS_SELECTED

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

T RW

STARTED

   

Write '1' to Enable interrupt for STARTED event

See EVENTS_STARTED

     

Set

1

Enable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

 

INTENCLR

Address offset: 0x308

Disable interrupt

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                      

T

S

R

N

 

M

L

K

H

G

F

E

D

C

B

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

READY

   

Write '1' to Disable interrupt for READY event

See EVENTS_READY

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

B RW

FIELDDETECTED

   

Write '1' to Disable interrupt for FIELDDETECTED event

See EVENTS_FIELDDETECTED

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

C RW

FIELDLOST

   

Write '1' to Disable interrupt for FIELDLOST event

See EVENTS_FIELDLOST

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

D RW

TXFRAMESTART

   

Write '1' to Disable interrupt for TXFRAMESTART event

See EVENTS_TXFRAMESTART

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

E RW

TXFRAMEEND

   

Write '1' to Disable interrupt for TXFRAMEEND event

See EVENTS_TXFRAMEEND

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

F RW

RXFRAMESTART

   

Write '1' to Disable interrupt for RXFRAMESTART event

See EVENTS_RXFRAMESTART

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

G RW

RXFRAMEEND

   

Write '1' to Disable interrupt for RXFRAMEEND event

See EVENTS_RXFRAMEEND

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

H RW

ERROR

   

Write '1' to Disable interrupt for ERROR event

See EVENTS_ERROR

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

K RW

RXERROR

   

Write '1' to Disable interrupt for RXERROR event

See EVENTS_RXERROR

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

L RW

ENDRX

   

Write '1' to Disable interrupt for ENDRX event

See EVENTS_ENDRX

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

M RW

ENDTX

   

Write '1' to Disable interrupt for ENDTX event

See EVENTS_ENDTX

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

N RW

AUTOCOLRESSTARTED

   

Write '1' to Disable interrupt for AUTOCOLRESSTARTED event

See EVENTS_AUTOCOLRESSTARTED

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

R RW

COLLISION

   

Write '1' to Disable interrupt for COLLISION event

See EVENTS_COLLISION

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

S RW

SELECTED

   

Write '1' to Disable interrupt for SELECTED event

See EVENTS_SELECTED

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

T RW

STARTED

   

Write '1' to Disable interrupt for STARTED event

See EVENTS_STARTED

     

Clear

1

Disable

     

Disabled

0

Read: Disabled

     

Enabled

1

Read: Enabled

 

ERRORSTATUS

Address offset: 0x404

NFC Error Status register

Write a bit to '1' to clear it. Writing '0' has no effect.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                                          

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

FRAMEDELAYTIMEOUT

   

No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX

 

FRAMESTATUS.RX

Address offset: 0x40C

Result of last incoming frame

Write a bit to '1' to clear it. Writing '0' has no effect.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                                    

C

B

 

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

CRCERROR

   

No valid end of frame (EoF) detected

     

CRCCorrect

0

Valid CRC detected

     

CRCError

1

CRC received does not match local check

B RW

PARITYSTATUS

   

Parity status of received frame

     

ParityOK

0

Frame received with parity OK

     

ParityError

1

Frame received with parity error

C RW

OVERRUN

   

Overrun detected

     

NoOverrun

0

No overrun detected

     

Overrun

1

Overrun error

 

NFCTAGSTATE

Address offset: 0x410

NfcTag state register

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                                          

A

A

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A R

NFCTAGSTATE

   

NfcTag state

     

Disabled

0

Disabled or sense

     

RampUp

2

RampUp

     

Idle

3

Idle

     

Receive

4

Receive

     

FrameDelay

5

FrameDelay

     

Transmit

6

Transmit

 

FIELDPRESENT

Address offset: 0x43C

Indicates the presence or not of a valid field

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                                            

B

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A R

FIELDPRESENT

   

Indicates if a valid field is present. Available only in the activated state.

     

NoField

0

No valid field detected

     

FieldPresent

1

Valid field detected

B R

LOCKDETECT

   

Indicates if the low level has locked to the field

     

NotLocked

0

Not locked to field

     

Locked

1

Locked to field

 

FRAMEDELAYMIN

Address offset: 0x504

Minimum frame delay

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

Reset 0x00000480 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

FRAMEDELAYMIN

   

Minimum frame delay in number of 13.56 MHz clocks

 

FRAMEDELAYMAX

Address offset: 0x508

Maximum frame delay

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

Reset 0x00001000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

FRAMEDELAYMAX

   

Maximum frame delay in number of 13.56 MHz clocks

 

FRAMEDELAYMODE

Address offset: 0x50C

Configuration register for the Frame Delay Timer

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                                            

A

A

Reset 0x00000001 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Id RW Field Value Id Value Description
A RW

FRAMEDELAYMODE

   

Configuration register for the Frame Delay Timer

     

FreeRun

0

Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout.

     

Window

1

Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX

     

ExactVal

2

Frame is transmitted exactly at FRAMEDELAYMAX

     

WindowGrid

3

Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX

 

PACKETPTR

Address offset: 0x510

Packet pointer for TXD and RXD data storage in Data RAM

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

PTR

   

Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte-aligned RAM address.

 

MAXLEN

Address offset: 0x514

Size of the RAM buffer allocated to TXD and RXD data storage each

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                              

A

A

A

A

A

A

A

A

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

MAXLEN

 

[0..257]

Size of the RAM buffer allocated to TXD and RXD data storage each

 

TXD.FRAMECONFIG

Address offset: 0x518

Configuration of outgoing frames

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                                      

D

 

C

B

A

Reset 0x00000017 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1
Id RW Field Value Id Value Description
A RW

PARITY

   

Indicates if parity is added to the frame

     

NoParity

0

Parity is not added to TX frames

     

Parity

1

Parity is added to TX frames

B RW

DISCARDMODE

   

Discarding unused bits at start or end of a frame

     

DiscardEnd

0

Unused bits are discarded at end of frame (EoF)

     

DiscardStart

1

Unused bits are discarded at start of frame (SoF)

C RW

SOF

   

Adding SoF or not in TX frames

     

NoSoF

0

SoF symbol not added

     

SoF

1

SoF symbol added

D RW

CRCMODETX

   

CRC mode for outgoing frames

     

NoCRCTX

0

CRC is not added to the frame

     

CRC16TX

1

16 bit CRC added to the frame based on all the data read from RAM that is used in the frame

 

TXD.AMOUNT

Address offset: 0x51C

Size of outgoing frame

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                        

B

B

B

B

B

B

B

B

B

A

A

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

TXDATABITS

 

[0..7]

Number of bits in the last or first byte read from RAM that shall be included in the frame (excluding parity bit).

The DISCARDMODE field in FRAMECONFIG.TX selects if unused bits is discarded at the start or at the end of a frame. A value of 0 data bytes and 0 data bits is invalid.

B RW

TXDATABYTES

 

[0..257]

Number of complete bytes that shall be included in the frame, excluding CRC, parity and framing

 

RXD.FRAMECONFIG

Address offset: 0x520

Configuration of incoming frames

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                                      

C

 

B

 

A

Reset 0x00000015 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1
Id RW Field Value Id Value Description
A RW

PARITY

   

Indicates if parity expected in RX frame

     

NoParity

0

Parity is not expected in RX frames

     

Parity

1

Parity is expected in RX frames

B RW

SOF

   

SoF expected or not in RX frames

     

NoSoF

0

SoF symbol is not expected in RX frames

     

SoF

1

SoF symbol is expected in RX frames

C RW

CRCMODERX

   

CRC mode for incoming frames

     

NoCRCRX

0

CRC is not expected in RX frames

     

CRC16RX

1

Last 16 bits in RX frame is CRC, CRC is checked and CRCSTATUS updated

 

RXD.AMOUNT

Address offset: 0x524

Size of last incoming frame

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                        

B

B

B

B

B

B

B

B

B

A

A

A

Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A R

RXDATABITS

   

Number of bits in the last byte in the frame, if less than 8 (including CRC, but excluding parity and SoF/EoF framing).

Frames with 0 data bytes and less than 7 data bits are invalid and are not received properly.

B R

RXDATABYTES

   

Number of complete bytes received in the frame (including CRC, but excluding parity and SoF/EoF framing)

 

NFCID1_LAST

Address offset: 0x590

Last NFCID1 part (4, 7 or 10 bytes ID)

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id

D

D

D

D

D

D

D

D

C

C

C

C

C

C

C

C

B

B

B

B

B

B

B

B

A

A

A

A

A

A

A

A

Reset 0x00006363 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1
Id RW Field Value Id Value Description
A RW

NFCID1_Z

   

NFCID1 byte Z (very last byte sent)

B RW

NFCID1_Y

   

NFCID1 byte Y

C RW

NFCID1_X

   

NFCID1 byte X

D RW

NFCID1_W

   

NFCID1 byte W