Debug and trace

The debug and trace system offers a flexible and powerful mechanism for non-intrusive debugging.

Figure 1. Overview

The main features of the debug and trace system are:

DAP - Debug access port

An external debugger can access the device via the DAP.

The DAP implements a standard ARM® CoreSight™ SW-DP (serial wire debug port).

The SW-DP implements the SWD (serial wire debug) protocol that is a two-pin serial interface, see SWDCLK and SWDIO in Debug and trace.

In addition to the default access port in the CPU (AHB-AP), the DAP includes a custom control access port (CTRL-AP). The CTRL-AP is described in more detail in CTRL-AP - Control access port.

Important:
  • The SWDIO line has an internal pull-up resistor.
  • The SWDCLK line has an internal pull-down resistor.

CTRL-AP - Control access port

The control access port (CTRL-AP) is a custom access port that enables control of the device even if the other access ports in the DAP are being disabled by the access port protection.

Access port protection blocks the debugger from read and write access to all CPU registers and memory-mapped addresses. See the UICR register APPROTECT for more information about enabling access port protection.

This access port enables the following features:

  • Soft reset, see Reset for more information
  • Disable access port protection

Access port protection can only be disabled by issuing an ERASEALL command via CTRL-AP. This command will erase flash, UICR, and RAM.

Registers

Table 1. Register Overview
Register Offset Description
RESET 0x000

Soft reset triggered through CTRL-AP

 
ERASEALL 0x004

Erase all

 
ERASEALLSTATUS 0x008

Status register for the ERASEALL operation

 
APPROTECTSTATUS 0x00C

Status register for access port protection

 
IDR 0x0FC

CTRL-AP identification register, IDR

 

RESET

Address offset: 0x000

Soft reset triggered through CTRL-AP

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

RESET

   

Soft reset triggered through CTRL-AP. See Reset behaviour in POWER chapter for more details.

     

NoReset

0

Reset is not active

     

Reset

1

Reset is active. Device is held in reset.

 

ERASEALL

Address offset: 0x004

Erase all

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A W

ERASEALL

   

Erase all flash and RAM

     

NoOperation

0

No operation

     

Erase

1

Erase all flash and RAM

 

ERASEALLSTATUS

Address offset: 0x008

Status register for the ERASEALL operation

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A R

ERASEALLSTATUS

   

Status register for the ERASEALL operation

     

Ready

0

ERASEALL is ready

     

Busy

1

ERASEALL is busy (on-going)

 

APPROTECTSTATUS

Address offset: 0x00C

Status register for access port protection

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                                               A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A R

APPROTECTSTATUS

   

Status register for access port protection

     

Enabled

0

Access port protection enabled

     

Disabled

1

Access port protection not enabled

 

IDR

Address offset: 0x0FC

CTRL-AP identification register, IDR

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id E E E E D D D D C C C C C C C B B B B           A A A A A A A A
Reset 0x02880000 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A R

APID

   

AP identification

B R

CLASS

   

Access port (AP) class

     

NotDefined

0x0

No defined class

     

MEMAP

0x8

Memory access port

C R

JEP106ID

   

JEDEC JEP106 identity code

D R

JEP106CONT

   

JEDEC JEP106 continuation code

E R

REVISION

   

Revision

 

Electrical specification

Control access port

Symbol Description Min. Typ. Max. Units
Rpull

Internal SWDIO and SWDCLK pull up/down resistance

13

Debug interface mode

Before the external debugger can access the CPU's access port (AHB-AP) or the control access port (CTRL-AP), the debugger must first request the device to power up via CxxxPWRUPREQ in the SWJ-DP.

As long as the debugger is requesting power via CxxxPWRUPREQ, the device will be in debug interface mode. If the debugger is not requesting power via CxxxPWRUPREQ, the device will be in normal mode.

Some peripherals will behave differently in debug interface mode compared to normal mode. These differences are described in more detail in the chapters of the peripherals that are affected.

When a debug session is over, the external debugger must make sure to put the device back into normal mode since the overall power consumption will be higher in debug interface mode compared to normal mode.

For details on how to use the debug capabilities please read the debug documentation of your IDE.

If the device is in System OFF when power is requested via CxxxPWRUPREQ, the system will wake up and the DIF flag in RESETREAS will be set.

Real-time debug

The nRF52840 supports real-time debugging.

Real-time debugging will allow interrupts to execute to completion in real time when breakpoints are set in thread mode or lower priority interrupts. This enables the developer to set a breakpoint and single-step through their code without a failure of the real-time event-driven threads running at higher priority. For example, this enables the device to continue to service the high-priority interrupts of an external controller or sensor without failure or loss of state synchronization while the developer steps through code in a low-priority thread.

Trace

The device supports ETM and ITM trace.

Trace data from the ETM and the ITM is sent to an external debugger via a 4-bit wide parallel trace port (TPIU), see TRACEDATA[0] through TRACEDATA[3] and TRACECLK in Figure 1. In addition to parallel trace, the TPIU supports serial trace via the serial wire output (SWO) trace protocol. Parallel and serial trace cannot be used at the same time.

ETM trace is only supported in parallel trace mode, while ITM trace is supported in both parallel and serial trace modes. For details on how to use the trace capabilities, please read the debug documentation of your IDE.

TPIU's trace pins are multiplexed with GPIOs, and SWO and TRACEDATA[0] use the same GPIO, see Pin assignments for more information. The speed of the trace pins depends on the drive setting of the GPIOs that the trace pins are multiplexed with. Trace speed is configured in the TRACECONFIG register.

Only S0S1 and H0H1 drives are suitable for debugging. S0S1 is the default drive at reset. If parallel or serial trace port signals are not fast enough in the debugging conditions, all GPIOs in use for tracing should be set to high drive (H0H1). The user must make sure that these GPIOs' drive is not overwritten by software during the debugging session.

Electrical specification

Trace port

Symbol Description Min. Typ. Max. Units
Tcyc

Clock period, as defined by ARM (See ARM Infocenter, Embedded Trace Macrocell Architecture Specification, Trace Port Physical Interface, Timing specifications)

62.5 500 ns

Documentation feedback | Developer Zone | Updated 2017-07-06