ACL — Access control lists

The Access control lists (ACL) peripheral is designed to assign and enforce access permissions to different regions of the on-chip flash memory map.

Flash memory regions can be assigned individual ACL permission schemes. The following registers are involved:

  • PERM register, where the permissions are configured.
  • ADDR register, where the word-aligned start address for the flash page is defined.
  • SIZE register, where the size of the region the permissions are applied to is determined.
Important: The size of the region in bytes is restricted to a multiple of the flash page size. See the Memory chapter for more information.
Figure 1. Protected regions of on-chip flash memory

There are four defined ACL permission schemes, with different combinations of read/write permissions:

Table 1. Permission schemes
Read Write Protection description
0 0 No protection. Entire region can be executed, read, written or erased.
0 1 Region can be executed and read, but not written or erased.
1 0 Region can be written and erased, but not executed or read.
1 1 Region is locked for all access until next reset.
Important: If a permission violation to a protected region is detected by the ACL peripheral, the request is blocked and a Bus Fault exception is triggered.

Access control to a configured region is enforced by the hardware two CPU clock cycles after the ADDR, SIZE, and PERM registers for an ACL instance have been successfully written. The protection is only enforced if a valid start address of the flash page boundary is written into the ADDR register, and the values of the SIZE and PERM registers are not zero.

The ADDR, SIZE, and PERM registers can only be written once. All ACL configuration registers are cleared on reset (by resetting the device from any reset source), which is also the only way of clearing the configuration registers. To ensure that the desired permission schemes are always enforced by the ACL peripheral, the device boot sequence must perform the necessary configuration.

The protection mechanism for regions is by default turned off when in debug interface mode, and the DISABLEINDEBUG register is set to "Disabled". See the Debug and trace chapter for more information.

Registers

Table 2. Instances
Base address Peripheral Instance Description Configuration
0x4001E000 ACL ACL

Access control lists

   
Table 3. Register Overview
Register Offset Description
DISABLEINDEBUG 0x704

Disable all ACL protection mechanisms for regions while in debug mode

 
ACL[0].ADDR 0x800

Configure the word-aligned start address of region 0 to protect

 
ACL[0].SIZE 0x804

Size of region to protect counting from address ACL[0].ADDR. Write '0' as no effect.

 
ACL[0].PERM 0x808

Access permissions for region 0 as defined by start address ACL[0].ADDR and size ACL[0].SIZE

 
  0x80C  

Reserved

ACL[1].ADDR 0x810

Configure the word-aligned start address of region 1 to protect

 
ACL[1].SIZE 0x814

Size of region to protect counting from address ACL[1].ADDR. Write '0' as no effect.

 
ACL[1].PERM 0x818

Access permissions for region 1 as defined by start address ACL[1].ADDR and size ACL[1].SIZE

 
  0x81C  

Reserved

ACL[2].ADDR 0x820

Configure the word-aligned start address of region 2 to protect

 
ACL[2].SIZE 0x824

Size of region to protect counting from address ACL[2].ADDR. Write '0' as no effect.

 
ACL[2].PERM 0x828

Access permissions for region 2 as defined by start address ACL[2].ADDR and size ACL[2].SIZE

 
  0x82C  

Reserved

ACL[3].ADDR 0x830

Configure the word-aligned start address of region 3 to protect

 
ACL[3].SIZE 0x834

Size of region to protect counting from address ACL[3].ADDR. Write '0' as no effect.

 
ACL[3].PERM 0x838

Access permissions for region 3 as defined by start address ACL[3].ADDR and size ACL[3].SIZE

 
  0x83C  

Reserved

ACL[4].ADDR 0x840

Configure the word-aligned start address of region 4 to protect

 
ACL[4].SIZE 0x844

Size of region to protect counting from address ACL[4].ADDR. Write '0' as no effect.

 
ACL[4].PERM 0x848

Access permissions for region 4 as defined by start address ACL[4].ADDR and size ACL[4].SIZE

 
  0x84C  

Reserved

ACL[5].ADDR 0x850

Configure the word-aligned start address of region 5 to protect

 
ACL[5].SIZE 0x854

Size of region to protect counting from address ACL[5].ADDR. Write '0' as no effect.

 
ACL[5].PERM 0x858

Access permissions for region 5 as defined by start address ACL[5].ADDR and size ACL[5].SIZE

 
  0x85C  

Reserved

ACL[6].ADDR 0x860

Configure the word-aligned start address of region 6 to protect

 
ACL[6].SIZE 0x864

Size of region to protect counting from address ACL[6].ADDR. Write '0' as no effect.

 
ACL[6].PERM 0x868

Access permissions for region 6 as defined by start address ACL[6].ADDR and size ACL[6].SIZE

 
  0x86C  

Reserved

ACL[7].ADDR 0x870

Configure the word-aligned start address of region 7 to protect

 
ACL[7].SIZE 0x874

Size of region to protect counting from address ACL[7].ADDR. Write '0' as no effect.

 
ACL[7].PERM 0x878

Access permissions for region 7 as defined by start address ACL[7].ADDR and size ACL[7].SIZE

 
  0x87C  

Reserved

DISABLEINDEBUG

Address offset: 0x704

Disable all ACL protection mechanisms for regions while in debug mode

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                                               A
Reset 0x00000001 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Id RW Field Value Id Value Description
A RW

DISABLEINDEBUG

   

Disable the protection mechanism for regions while in debug mode.

     

Disabled

1

ACL is disabled in debug mode

     

Enabled

0

ACL is enabled in debug mode

 

ACL[0].ADDR

Address offset: 0x800

Configure the word-aligned start address of region 0 to protect

This register can only be written once.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

ADDR

   

Valid word-aligned start address of region 0 to protect. Address must point to a flash page boundary.

 

ACL[0].SIZE

Address offset: 0x804

Size of region to protect counting from address ACL[0].ADDR. Write '0' as no effect.

This register can only be written once.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

SIZE

   

Size of flash region 0 in bytes. Must be a multiple of the flash page size.

 

ACL[0].PERM

Address offset: 0x808

Access permissions for region 0 as defined by start address ACL[0].ADDR and size ACL[0].SIZE

This register can only be written once.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                                     C B
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
B RW

WRITE

   

Configure write and erase permissions for region 0. Write '0' has no effect.

     

Enable

0

Allow write and erase instructions to region 0

     

Disable

1

Block write and erase instructions to region 0

C RW

READ

   

Configure read permissions for region 0. Write '0' has no effect.

     

Enable

0

Allow read instructions to region 0

     

Disable

1

Block read instructions to region 0

 

ACL[1].ADDR

Address offset: 0x810

Configure the word-aligned start address of region 1 to protect

This register can only be written once.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

ADDR

   

Valid word-aligned start address of region 1 to protect. Address must point to a flash page boundary.

 

ACL[1].SIZE

Address offset: 0x814

Size of region to protect counting from address ACL[1].ADDR. Write '0' as no effect.

This register can only be written once.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

SIZE

   

Size of flash region 1 in bytes. Must be a multiple of the flash page size.

 

ACL[1].PERM

Address offset: 0x818

Access permissions for region 1 as defined by start address ACL[1].ADDR and size ACL[1].SIZE

This register can only be written once.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                                     C B
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
B RW

WRITE

   

Configure write and erase permissions for region 1. Write '0' has no effect.

     

Enable

0

Allow write and erase instructions to region 1

     

Disable

1

Block write and erase instructions to region 1

C RW

READ

   

Configure read permissions for region 1. Write '0' has no effect.

     

Enable

0

Allow read instructions to region 1

     

Disable

1

Block read instructions to region 1

 

ACL[2].ADDR

Address offset: 0x820

Configure the word-aligned start address of region 2 to protect

This register can only be written once.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

ADDR

   

Valid word-aligned start address of region 2 to protect. Address must point to a flash page boundary.

 

ACL[2].SIZE

Address offset: 0x824

Size of region to protect counting from address ACL[2].ADDR. Write '0' as no effect.

This register can only be written once.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

SIZE

   

Size of flash region 2 in bytes. Must be a multiple of the flash page size.

 

ACL[2].PERM

Address offset: 0x828

Access permissions for region 2 as defined by start address ACL[2].ADDR and size ACL[2].SIZE

This register can only be written once.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                                     C B
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
B RW

WRITE

   

Configure write and erase permissions for region 2. Write '0' has no effect.

     

Enable

0

Allow write and erase instructions to region 2

     

Disable

1

Block write and erase instructions to region 2

C RW

READ

   

Configure read permissions for region 2. Write '0' has no effect.

     

Enable

0

Allow read instructions to region 2

     

Disable

1

Block read instructions to region 2

 

ACL[3].ADDR

Address offset: 0x830

Configure the word-aligned start address of region 3 to protect

This register can only be written once.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

ADDR

   

Valid word-aligned start address of region 3 to protect. Address must point to a flash page boundary.

 

ACL[3].SIZE

Address offset: 0x834

Size of region to protect counting from address ACL[3].ADDR. Write '0' as no effect.

This register can only be written once.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

SIZE

   

Size of flash region 3 in bytes. Must be a multiple of the flash page size.

 

ACL[3].PERM

Address offset: 0x838

Access permissions for region 3 as defined by start address ACL[3].ADDR and size ACL[3].SIZE

This register can only be written once.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                                     C B
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
B RW

WRITE

   

Configure write and erase permissions for region 3. Write '0' has no effect.

     

Enable

0

Allow write and erase instructions to region 3

     

Disable

1

Block write and erase instructions to region 3

C RW

READ

   

Configure read permissions for region 3. Write '0' has no effect.

     

Enable

0

Allow read instructions to region 3

     

Disable

1

Block read instructions to region 3

 

ACL[4].ADDR

Address offset: 0x840

Configure the word-aligned start address of region 4 to protect

This register can only be written once.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

ADDR

   

Valid word-aligned start address of region 4 to protect. Address must point to a flash page boundary.

 

ACL[4].SIZE

Address offset: 0x844

Size of region to protect counting from address ACL[4].ADDR. Write '0' as no effect.

This register can only be written once.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

SIZE

   

Size of flash region 4 in bytes. Must be a multiple of the flash page size.

 

ACL[4].PERM

Address offset: 0x848

Access permissions for region 4 as defined by start address ACL[4].ADDR and size ACL[4].SIZE

This register can only be written once.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                                     C B
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
B RW

WRITE

   

Configure write and erase permissions for region 4. Write '0' has no effect.

     

Enable

0

Allow write and erase instructions to region 4

     

Disable

1

Block write and erase instructions to region 4

C RW

READ

   

Configure read permissions for region 4. Write '0' has no effect.

     

Enable

0

Allow read instructions to region 4

     

Disable

1

Block read instructions to region 4

 

ACL[5].ADDR

Address offset: 0x850

Configure the word-aligned start address of region 5 to protect

This register can only be written once.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

ADDR

   

Valid word-aligned start address of region 5 to protect. Address must point to a flash page boundary.

 

ACL[5].SIZE

Address offset: 0x854

Size of region to protect counting from address ACL[5].ADDR. Write '0' as no effect.

This register can only be written once.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

SIZE

   

Size of flash region 5 in bytes. Must be a multiple of the flash page size.

 

ACL[5].PERM

Address offset: 0x858

Access permissions for region 5 as defined by start address ACL[5].ADDR and size ACL[5].SIZE

This register can only be written once.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                                     C B
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
B RW

WRITE

   

Configure write and erase permissions for region 5. Write '0' has no effect.

     

Enable

0

Allow write and erase instructions to region 5

     

Disable

1

Block write and erase instructions to region 5

C RW

READ

   

Configure read permissions for region 5. Write '0' has no effect.

     

Enable

0

Allow read instructions to region 5

     

Disable

1

Block read instructions to region 5

 

ACL[6].ADDR

Address offset: 0x860

Configure the word-aligned start address of region 6 to protect

This register can only be written once.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

ADDR

   

Valid word-aligned start address of region 6 to protect. Address must point to a flash page boundary.

 

ACL[6].SIZE

Address offset: 0x864

Size of region to protect counting from address ACL[6].ADDR. Write '0' as no effect.

This register can only be written once.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

SIZE

   

Size of flash region 6 in bytes. Must be a multiple of the flash page size.

 

ACL[6].PERM

Address offset: 0x868

Access permissions for region 6 as defined by start address ACL[6].ADDR and size ACL[6].SIZE

This register can only be written once.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                                     C B
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
B RW

WRITE

   

Configure write and erase permissions for region 6. Write '0' has no effect.

     

Enable

0

Allow write and erase instructions to region 6

     

Disable

1

Block write and erase instructions to region 6

C RW

READ

   

Configure read permissions for region 6. Write '0' has no effect.

     

Enable

0

Allow read instructions to region 6

     

Disable

1

Block read instructions to region 6

 

ACL[7].ADDR

Address offset: 0x870

Configure the word-aligned start address of region 7 to protect

This register can only be written once.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

ADDR

   

Valid word-aligned start address of region 7 to protect. Address must point to a flash page boundary.

 

ACL[7].SIZE

Address offset: 0x874

Size of region to protect counting from address ACL[7].ADDR. Write '0' as no effect.

This register can only be written once.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW

SIZE

   

Size of flash region 7 in bytes. Must be a multiple of the flash page size.

 

ACL[7].PERM

Address offset: 0x878

Access permissions for region 7 as defined by start address ACL[7].ADDR and size ACL[7].SIZE

This register can only be written once.

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id                                                     C B
Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
B RW

WRITE

   

Configure write and erase permissions for region 7. Write '0' has no effect.

     

Enable

0

Allow write and erase instructions to region 7

     

Disable

1

Block write and erase instructions to region 7

C RW

READ

   

Configure read permissions for region 7. Write '0' has no effect.

     

Enable

0

Allow read instructions to region 7

     

Disable

1

Block read instructions to region 7

 

Documentation feedback | Developer Zone | Updated 2016-12-05