[184] NVMC: Erase or write operations from the external debugger fail when CPU is not halted

This anomaly applies to IC Rev. Engineering C, build codes QIAA-CA0, CKAA-CA0.

It was inherited from the previous IC revision Engineering B nRF52840.

Symptoms

The erase or write operation fails or takes longer time than specified.

Conditions

NVMC erase or write operation initiated using an external debugger. CPU is not halted.

Consequences

The NVMC erase or write operation fails or takes longer time than specified.

Workaround

Halt the CPU by writing to DHCSR (Debug Halting Control and Status Register) before starting NVMC erase or write operation from the external debugger. See the ARM infocenter to get the details of the DHCSR register.

Programming tools provided by Nordic Semiconductor comply with this.