The TWI master is compatible with I2C operating at 100 kHz and 400 kHz.
This TWI master is not compatible with CBUS. The TWI transmitter and receiver are single buffered.
See, Figure 1.
A TWI setup comprising one master and three slaves is illustrated in Figure 2. This TWI master is only able to operate as the only master on the TWI bus.
This TWI master supports clock stretching performed by the slaves. The TWI master is started by triggering the STARTTX or STARTRX tasks, and stopped by triggering the STOP task.
If a NACK is clocked in from the slave, the TWI master will generate an ERROR event.
The different signals SCL and SDA associated with the TWI master are mapped to physical pins according to the configuration specified in the PSELSCL and PSELSDA registers respectively.
If a value of 0xFFFFFFFF is specified in any of these registers, the associated TWI master signal is not connected to any physical pin. The PSELSCL and PSELSDA registers and their configurations are only used as long as the TWI master is enabled, and retained only as long as the device is in ON mode. PSELSCL and PSELSDA must only be configured when the TWI is disabled.
To secure correct signal levels on the pins used by the TWI master when the system is in OFF mode, and when the TWI master is disabled, these pins must be configured in the GPIO peripheral as described in Table 1.
Only one peripheral can be assigned to drive a particular GPIO pin at a time, failing to do so may result in unpredictable behavior.
TWI master signal | TWI master pin | Direction | Drive strength | Output value |
---|---|---|---|---|
SCL | As specified in PSELSCL | Input | S0D1 | Not applicable |
SDA | As specified in PSELSDA | Input | S0D1 | Not applicable |
The TWI shares registers and other resources with other peripherals that have the same ID as the TWI.
Therefore, you must disable all peripherals that have the same ID as the TWI before the TWI can be configured and used. Disabling a peripheral that has the same ID as the TWI will not reset any of the registers that are shared with the TWI. It is therefore important to configure all relevant TWI registers explicitly to secure that it operates correctly.
The Instantiation table in Instantiation shows which peripherals have the same ID as the TWI.
A TWI master write sequence is started by triggering the STARTTX task. After the STARTTX task has been triggered, the TWI master will generate a start condition on the TWI bus, followed by clocking out the address and the READ/WRITE bit set to 0 (WRITE=0, READ=1).
The address must match the address of the slave device that the master wants to write to. The READ/WRITE bit is followed by an ACK/NACK bit (ACK=0 or NACK=1) generated by the slave.
After receiving the ACK bit, the TWI master will clock out the data bytes that are written to the TXD register. Each byte clocked out from the master will be followed by an ACK/NACK bit clocked in from the slave. A TXDSENT event will be generated each time the TWI master has clocked out a TXD byte, and the associated ACK/NACK bit has been clocked in from the slave.
The TWI master transmitter is single buffered, and a second byte can only be written to the TXD register after the previous byte has been clocked out and the ACK/NACK bit clocked in, that is, after the TXDSENT event has been generated.
If the CPU is prevented from writing to TXD when the TWI master is ready to clock out a byte, the TWI master will stretch the clock until the CPU has written a byte to the TXD register.
A typical TWI master write sequence is illustrated in Figure 3. Occurrence 3 in the figure illustrates delayed processing of the TXDSENT event associated with TXD byte 1. In this scenario the TWI master will stretch the clock to prevent writing erroneous data to the slave.
The TWI master write sequence is stopped when the STOP task is triggered whereupon the TWI master will generate a stop condition on the TWI bus.
A TWI master read sequence is started by triggering the STARTRX task. After the STARTRX task has been triggered the TWI master will generate a start condition on the TWI bus, followed by clocking out the address and the READ/WRITE bit set to 1 (WRITE = 0, READ = 1).
The address must match the address of the slave device that the master wants to read from. The READ/WRITE bit is followed by an ACK/NACK bit (ACK=0 or NACK = 1) generated by the slave.
After having sent the ACK bit the TWI slave will send data to the master using the clock generated by the master.
The TWI master will generate a RXDRDY event every time a new byte is received in the RXD register.
After receiving a byte, the TWI master will delay sending the ACK/NACK bit by stretching the clock until the CPU has extracted the received byte, that is, by reading the RXD register.
The TWI master read sequence is stopped by triggering the STOP task. This task must be triggered before the last byte is extracted from RXD to ensure that the TWI master sends a NACK back to the slave before generating the stop condition.
A typical TWI master read sequence is illustrated in Figure 4. Occurrence 3 in this figure illustrates delayed processing of the RXDRDY event associated with RXD byte B. In this scenario the TWI master will stretch the clock to prevent the slave from overwriting the contents of the RXD register.
A typical repeated start sequence is one in which the TWI master writes one byte to the slave followed by reading M bytes from the slave. Any combination and number of transmit and receive sequences can be combined in this fashion. Only one shortcut to STOP can be enabled at any given time.
The figure below illustrates a repeated start sequence where the TWI master writes one byte, followed by reading M bytes from the slave without performing a stop in-between.
To generate a repeated start after a read sequence, a second start task must be triggered instead of the STOP task, that is, STARTRX or STARTTX. This start task must be triggered before the last byte is extracted from RXD to ensure that the TWI master sends a NACK back to the slave before generating the repeated start condition.
When putting the system in low power and the peripheral is not needed, lowest possible power consumption is achieved by stopping, and then disabling the peripheral.
The STOP task may not be always needed (the peripheral might already be stopped), but if it is sent, software shall wait until the STOPPED event was received as a response before disabling the peripheral through the ENABLE register.
Base address | Peripheral | Instance | Description | Configuration | |
---|---|---|---|---|---|
0x40003000 | TWI | TWI0 |
Two-wire interface master 0 |
Deprecated |
|
0x40004000 | TWI | TWI1 |
Two-wire interface master 1 |
Deprecated |
Register | Offset | Description | |
---|---|---|---|
TASKS_STARTRX | 0x000 |
Start TWI receive sequence |
|
TASKS_STARTTX | 0x008 |
Start TWI transmit sequence |
|
TASKS_STOP | 0x014 |
Stop TWI transaction |
|
TASKS_SUSPEND | 0x01C |
Suspend TWI transaction |
|
TASKS_RESUME | 0x020 |
Resume TWI transaction |
|
EVENTS_STOPPED | 0x104 |
TWI stopped |
|
EVENTS_RXDREADY | 0x108 |
TWI RXD byte received |
|
EVENTS_TXDSENT | 0x11C |
TWI TXD byte sent |
|
EVENTS_ERROR | 0x124 |
TWI error |
|
EVENTS_BB | 0x138 |
TWI byte boundary, generated before each byte that is sent or received |
|
EVENTS_SUSPENDED | 0x148 |
TWI entered the suspended state |
|
SHORTS | 0x200 |
Shortcut register |
|
INTENSET | 0x304 |
Enable interrupt |
|
INTENCLR | 0x308 |
Disable interrupt |
|
ERRORSRC | 0x4C4 |
Error source |
|
ENABLE | 0x500 |
Enable TWI |
|
PSELSCL | 0x508 |
Pin select for SCL |
|
PSELSDA | 0x50C |
Pin select for SDA |
|
RXD | 0x518 |
RXD register |
|
TXD | 0x51C |
TXD register |
|
FREQUENCY | 0x524 |
TWI frequency |
|
ADDRESS | 0x588 |
Address used in the TWI transfer |
Address offset: 0x200
Shortcut register
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Id | B | A | |||||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
BB_SUSPEND |
Shortcut between BB event and SUSPEND task See EVENTS_BB and TASKS_SUSPEND |
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Disabled |
0 |
Disable shortcut |
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Enabled |
1 |
Enable shortcut |
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B | RW |
BB_STOP |
Shortcut between BB event and STOP task See EVENTS_BB and TASKS_STOP |
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Disabled |
0 |
Disable shortcut |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Enable shortcut |
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Address offset: 0x304
Enable interrupt
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Id | F | E | D | C | B | A | |||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
STOPPED |
Write '1' to Enable interrupt for STOPPED event See EVENTS_STOPPED |
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Set |
1 |
Enable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Read: Enabled |
|||||||||||||||||||||||||||||||||
B | RW |
RXDREADY |
Write '1' to Enable interrupt for RXDREADY event See EVENTS_RXDREADY |
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Set |
1 |
Enable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Read: Enabled |
|||||||||||||||||||||||||||||||||
C | RW |
TXDSENT |
Write '1' to Enable interrupt for TXDSENT event See EVENTS_TXDSENT |
||||||||||||||||||||||||||||||||
Set |
1 |
Enable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
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Enabled |
1 |
Read: Enabled |
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D | RW |
ERROR |
Write '1' to Enable interrupt for ERROR event See EVENTS_ERROR |
||||||||||||||||||||||||||||||||
Set |
1 |
Enable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Read: Enabled |
|||||||||||||||||||||||||||||||||
E | RW |
BB |
Write '1' to Enable interrupt for BB event See EVENTS_BB |
||||||||||||||||||||||||||||||||
Set |
1 |
Enable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Read: Enabled |
|||||||||||||||||||||||||||||||||
F | RW |
SUSPENDED |
Write '1' to Enable interrupt for SUSPENDED event See EVENTS_SUSPENDED |
||||||||||||||||||||||||||||||||
Set |
1 |
Enable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Read: Enabled |
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Address offset: 0x308
Disable interrupt
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Id | F | E | D | C | B | A | |||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
STOPPED |
Write '1' to Disable interrupt for STOPPED event See EVENTS_STOPPED |
||||||||||||||||||||||||||||||||
Clear |
1 |
Disable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Read: Enabled |
|||||||||||||||||||||||||||||||||
B | RW |
RXDREADY |
Write '1' to Disable interrupt for RXDREADY event See EVENTS_RXDREADY |
||||||||||||||||||||||||||||||||
Clear |
1 |
Disable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Read: Enabled |
|||||||||||||||||||||||||||||||||
C | RW |
TXDSENT |
Write '1' to Disable interrupt for TXDSENT event See EVENTS_TXDSENT |
||||||||||||||||||||||||||||||||
Clear |
1 |
Disable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Read: Enabled |
|||||||||||||||||||||||||||||||||
D | RW |
ERROR |
Write '1' to Disable interrupt for ERROR event See EVENTS_ERROR |
||||||||||||||||||||||||||||||||
Clear |
1 |
Disable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Read: Enabled |
|||||||||||||||||||||||||||||||||
E | RW |
BB |
Write '1' to Disable interrupt for BB event See EVENTS_BB |
||||||||||||||||||||||||||||||||
Clear |
1 |
Disable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Read: Enabled |
|||||||||||||||||||||||||||||||||
F | RW |
SUSPENDED |
Write '1' to Disable interrupt for SUSPENDED event See EVENTS_SUSPENDED |
||||||||||||||||||||||||||||||||
Clear |
1 |
Disable |
|||||||||||||||||||||||||||||||||
Disabled |
0 |
Read: Disabled |
|||||||||||||||||||||||||||||||||
Enabled |
1 |
Read: Enabled |
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Address offset: 0x4C4
Error source
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Id | C | B | A | ||||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
OVERRUN |
Overrun error A new byte was received before previous byte got read by software from the RXD register. (Previous data is lost) |
||||||||||||||||||||||||||||||||
NotPresent |
0 |
Read: no overrun occured |
|||||||||||||||||||||||||||||||||
Present |
1 |
Read: overrun occured |
|||||||||||||||||||||||||||||||||
Clear |
1 |
Write: clear error on writing '1' |
|||||||||||||||||||||||||||||||||
B | RW |
ANACK |
NACK received after sending the address (write '1' to clear) |
||||||||||||||||||||||||||||||||
NotPresent |
0 |
Read: error not present |
|||||||||||||||||||||||||||||||||
Present |
1 |
Read: error present |
|||||||||||||||||||||||||||||||||
Clear |
1 |
Write: clear error on writing '1' |
|||||||||||||||||||||||||||||||||
C | RW |
DNACK |
NACK received after sending a data byte (write '1' to clear) |
||||||||||||||||||||||||||||||||
NotPresent |
0 |
Read: error not present |
|||||||||||||||||||||||||||||||||
Present |
1 |
Read: error present |
|||||||||||||||||||||||||||||||||
Clear |
1 |
Write: clear error on writing '1' |
|||||||||||||||||||||||||||||||||
Address offset: 0x500
Enable TWI
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Id | A | A | A | A | |||||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
ENABLE |
Enable or disable TWI |
||||||||||||||||||||||||||||||||
Disabled |
0 |
Disable TWI |
|||||||||||||||||||||||||||||||||
Enabled |
5 |
Enable TWI |
|||||||||||||||||||||||||||||||||
Address offset: 0x508
Pin select for SCL
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Id | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | |||
Reset 0xFFFFFFFF | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
PSELSCL |
[0..31] |
Pin number configuration for TWI SCL signal |
|||||||||||||||||||||||||||||||
Disconnected |
0xFFFFFFFF |
Disconnect |
|||||||||||||||||||||||||||||||||
Address offset: 0x50C
Pin select for SDA
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Id | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | |||
Reset 0xFFFFFFFF | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
PSELSDA |
[0..31] |
Pin number configuration for TWI SDA signal |
|||||||||||||||||||||||||||||||
Disconnected |
0xFFFFFFFF |
Disconnect |
|||||||||||||||||||||||||||||||||
Address offset: 0x518
RXD register
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Id | A | A | A | A | A | A | A | A | |||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | R |
RXD |
RXD register |
||||||||||||||||||||||||||||||||
Address offset: 0x51C
TXD register
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Id | A | A | A | A | A | A | A | A | |||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
TXD |
TXD register |
||||||||||||||||||||||||||||||||
Address offset: 0x524
TWI frequency
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Id | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | A | |||
Reset 0x04000000 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
FREQUENCY |
TWI master clock frequency |
||||||||||||||||||||||||||||||||
K100 |
0x01980000 |
100 kbps |
|||||||||||||||||||||||||||||||||
K250 |
0x04000000 |
250 kbps |
|||||||||||||||||||||||||||||||||
K400 |
0x06680000 |
400 kbps (actual rate 410.256 kbps) |
|||||||||||||||||||||||||||||||||
Address offset: 0x588
Address used in the TWI transfer
Bit number | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Id | A | A | A | A | A | A | A | ||||||||||||||||||||||||||||
Reset 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||
Id | RW | Field | Value Id | Value | Description | ||||||||||||||||||||||||||||||
A | RW |
ADDRESS |
Address used in the TWI transfer |
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Symbol | Description | Min. | Typ. | Max. | Units | ||||
---|---|---|---|---|---|---|---|---|---|
fTWI |
Bit rates for TWI1 |
100 | 400 | kbps | |||||
ITWI,100kbps |
Run current for TWI, 100 kbps |
50 | µA | ||||||
ITWI,400kbps |
Run current for TWI, 400 kbps |
50 | µA | ||||||
tTWI,START,LP |
Time from STARTRX/STARTTX task to transmission started, Low power mode |
tTWI,START,CL + tSTART_HFINT | µs | ||||||
tTWI,START,CL |
Time from STARTRX/STARTTX task to transmission started, Constant latency mode |
1.5 | µs |
Symbol | Description | Min. | Typ. | Max. | Units | ||||
---|---|---|---|---|---|---|---|---|---|
fTWI,SCL,100kbps |
SCL clock frequency, 100 kbps |
100 | kHz | ||||||
fTWI,SCL,250kbps |
SCL clock frequency, 250 kbps |
250 | kHz | ||||||
fTWI,SCL,400kbps |
SCL clock frequency, 400 kbps |
400 | kHz | ||||||
tTWI,SU_DAT |
Data setup time before positive edge on SCL – all modes |
300 | ns | ||||||
tTWI,HD_DAT |
Data hold time after negative edge on SCL – all modes |
500 | ns | ||||||
tTWI,HD_STA,100kbps |
TWI master hold time for START and repeated START condition, 100 kbps |
10000 | ns | ||||||
tTWI,HD_STA,250kbps |
TWI master hold time for START and repeated START condition, 250kbps |
4000 | ns | ||||||
tTWI,HD_STA,400kbps |
TWI master hold time for START and repeated START condition, 400 kbps |
2500 | ns | ||||||
tTWI,SU_STO,100kbps |
TWI master setup time from SCL high to STOP condition, 100 kbps |
5000 | ns | ||||||
tTWI,SU_STO,250kbps |
TWI master setup time from SCL high to STOP condition, 250 kbps |
2000 | ns | ||||||
tTWI,SU_STO,400kbps |
TWI master setup time from SCL high to STOP condition, 400 kbps |
1250 | ns | ||||||
tTWI,BUF,100kbps |
TWI master bus free time between STOP and START conditions, 100 kbps |
5800 | ns | ||||||
tTWI,BUF,250kbps |
TWI master bus free time between STOP and START conditions, 250 kbps |
2700 | ns | ||||||
tTWI,BUF,400kbps |
TWI master bus free time between STOP and START conditions, 400 kbps |
2100 | ns |