New and inherited anomalies

The following anomalies are present in revision Engineering C of the nRF52832 chip.

Table 1. New and inherited anomalies
ID Module Description New in Engineering C Inherited from Engineering B
12 COMP Reference ladder is not correctly calibrated   X
15 POWER RAM[x].POWERSET/CLR read as zero   X
20 RTC Register values are invalid   X
31 CLOCK Calibration values are not correctly loaded from FICR at reset   X
36 CLOCK Some registers are not reset when expected   X
51 I2S Aligned stereo slave mode does not work   X
54 I2S Wrong LRCK polarity in Aligned mode   X
55 I2S RXPTRUPD and TXPTRUPD events asserted after STOP   X
58 SPIM An additional byte is clocked out when RXD.MAXCNT = 1   X
64 NFCT Only full bytes can be received or transmitted, but supports 4-bit frame transmit   X
66 TEMP Linearity specification not met with default settings X  
67 NFCT,PPI Some events cannot be used with the PPI   X
68 CLOCK EVENTS_HFCLKSTARTED can be generated before HFCLK is stable   X
72 NFCT,PPI TASKS_ACTIVATE cannot be used with the PPI   X
74 SAADC Started events fires prematurely   X
75 MWU Increased current consumption   X
76 LPCOMP READY event is set sooner than it should   X
77 CLOCK RC oscillator is not calibrated when first started   X
78 TIMER High current consumption when using timer STOP task only   X
79 NFCT A false EVENTS_FIELDDETECTED event occurs after the field is lost   X
81 GPIO PIN_CNF is not retained when in debug interface mode   X
83 TWIS STOPPED event occurs twice if the STOP task is triggered during a transaction   X
84 COMP ISOURCE not functional   X
86 SAADC Triggering START task after offset calibration may write a sample to RAM   X
87 CPU Unexpected wake from System ON Idle when using FPU   X
88 WDT Increased current consumption when configured to pause in System ON idle   X
89 GPIOTE Static 400 µA current while using GPIOTE   X
91 RADIO Radio performance using CSP package version X  
97 GPIOTE High current consumption in System ON Idle mode   X
101 CLOCK Sleep current increases after soft reset   X
102 RADIO PAYLOAD/END events delayed or not triggered after ADDRESS   X
106 RADIO Higher CRC error rates for some access addresses X  
107 RADIO Immediate address match for access addresses containing MSBs 0x00 X  
108 RAM RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode   X
109 DMA DMA access transfers might be corrupted X  
113 COMP Single-ended mode with external reference is not functional X  
132 CLOCK The LFRC oscillator might not start X  
136 System Bits in RESETREAS are set when they should not be   X
138 RADIO Spurious emission on GPIO exceeds limits in radiated tests X  
141 NFCT HFCLK not stopped when entering SENSE mode X  
143 RADIO False CRC failures on specific addresses X  
146 CLOCK LFRC frequency deviation   X
149 TWIM First clock pulse after clock stretching may be too long or too short X  
150 SAADC EVENT_STARTED does not fire X  
155 GPIOTE IN event may occur more than once on input edge X  
156 GPIOTE Some CLR tasks give unintentional behavior X  
173 GPIO Writes to LATCH register take several CPU cycles to take effect X  
176 System Flash erase through CTRL-AP fails due to watchdog time-out X  
178 SAADC END event firing too early X  
179 RTC COMPARE event is generated twice from a single RTC compare match X  
183 PWM False SEQEND[0] and SEQEND[1] events X  
192 CLOCK LFRC frequency offset after calibration X  
194 I2S STOP task does not switch off all resources X  
196 I2S PSEL acquires GPIOs regardless of ENABLE X  
201 CLOCK EVENTS_HFCLKSTARTED might be generated twice X