Reference circuitry

To ensure good RF performance when designing PCBs, it is highly recommended to use the PCB layouts and component values provided by Nordic Semiconductor.

Documentation for the different package reference circuits, including Altium Designer files, PCB layout files, and PCB production files can be downloaded from Reference layout nRF52 Series .

Schematic QFAA QFN48 with internal LDO regulator setup

In addition to the schematic, the bill of material (BOM) is also provided.

Figure 1. QFAA QFN48 with internal LDO regulator setup
Schematic: QFAA QFN48 with internal LDO regulator setup

Note: For PCB reference layouts, see Reference layout nRF52 Series.
Table 1. Bill of material for QFAA QFN48 with internal LDO regulator setup
Designator Value Description Footprint
C1, C2, C11, C12 12 pF Capacitor, NP0, ±2% 0402
C3 0.8 pF Capacitor, NP0, ±5% 0402
C4, C5, C8 100 nF Capacitor, X7R, ±10% 0402
C6 N.C. Not mounted 0402
C7 100 pF Capacitor, NP0, ±5% 0402
C9 4.7 µF Capacitor, X5R, ±10% 0603
C10 1.0 µF Capacitor, X7R, ±10% 0603
L1 3.9 nH High frequency chip inductor ±5% 0402
U1 nRF52810-QFAA Multi-protocol Bluetooth® low energy, ANT and 2.4 GHz proprietary system on chip QFN-48
X1 32 MHz XTAL SMD 2016, 32 MHz, Cl = 8 pF, Total Tol: ±40 ppm XTAL_2016
X2 32.768 kHz XTAL SMD 3215, 32.768 kHz, Cl = 9 pF, Total Tol: ±20 ppm XTAL_3215

Schematic QFAA QFN48 with DC/DC regulator setup

In addition to the schematic, the bill of material (BOM) is also provided.

Figure 2. QFAA QFN48 with DC/DC regulator setup

Note: For PCB reference layouts, see Reference layout nRF52 Series.
Table 2. Bill of material for QFAA QFN48 with DC/DC regulator setup
Designator Value Description Footprint
C1, C2, C11, C12 12 pF Capacitor, NP0, ±2% 0402
C3 0.8 pF Capacitor, NP0, ±5% 0402
C4, C5, C8 100 nF Capacitor, X7R, ±10% 0402
C6 N.C. Not mounted 0402
C7 100 pF Capacitor, NP0, ±5% 0402
C9 4.7 µF Capacitor, X5R, ±10% 0603
C10 1.0 µF Capacitor, X7R, ±10% 0603
L1 3.9 nH High frequency chip inductor ±5% 0402
L2 10 µH Chip inductor, IDC,min = 50 mA, ±20% 0603
L3 15 nH High frequency chip inductor ±10% 0402
U1 nRF52810-QFAA Multi-protocol Bluetooth® low energy, ANT and 2.4 GHz proprietary system on chip QFN-48
X1 32 MHz XTAL SMD 2016, 32 MHz, Cl = 8 pF, Total Tol: ±40 ppm XTAL_2016
X2 32.768 kHz XTAL SMD 3215, 32.768 kHz, Cl = 9 pF, Total Tol: ±20 ppm XTAL_3215

Schematic QCAA QFN32 with internal LDO regulator setup

In addition to the schematic, the bill of material (BOM) is also provided.

Figure 3. QCAA QFN32 with internal LDO regulator setup
Schematic: QCAA QFN32 with internal LDO regulator setup

Note: For PCB reference layouts, see Reference layout nRF52 Series.
Table 3. Bill of material for QCAA QFN32 with internal LDO regulator setup
Designator Value Description Footprint
C1, C2, C11, C12 12 pF Capacitor, NP0, ±2% 0402
C3 0.8 pF Capacitor, NP0, ±5% 0402
C4, C5, C8 100 nF Capacitor, X7R, ±10% 0402
C6 N.C. Not mounted 0402
C7 100 pF Capacitor, NP0, ±5% 0402
C9 4.7 µF Capacitor, X5R, ±10% 0603
C10 1.0 µF Capacitor, X7R, ±10% 0603
L1 3.9 nH High frequency chip inductor ±5% 0402
U1 nRF52810-QCAA Multi-protocol Bluetooth® low energy, ANT and 2.4 GHz proprietary system on chip QFN-32
X1 32 MHz XTAL SMD 2016, 32 MHz, Cl = 8 pF, Total Tol: ±40 ppm XTAL_2016
X2 32.768 kHz XTAL SMD 3215, 32.768 kHz, Cl = 9 pF, Total Tol: ±20 ppm XTAL_3215

Schematic QCAA QFN32 with DC/DC regulator setup

In addition to the schematic, the bill of material (BOM) is also provided.

Figure 4. QCAA QFN32 with DC/DC regulator setup
Schematic: QCAA QFN32 with DC/DC regulator setup

Note: For PCB reference layouts, see Reference layout nRF52 Series.
Table 4. Bill of material for QCAA QFN32 with DC/DC regulator setup
Designator Value Description Footprint
C1, C2, C11, C12 12 pF Capacitor, NP0, ±2% 0402
C3 0.8 pF Capacitor, NP0, ±5% 0402
C4, C5, C8 100 nF Capacitor, X7R, ±10% 0402
C6 N.C. Not mounted 0402
C7 100 pF Capacitor, NP0, ±5% 0402
C9 4.7 µF Capacitor, X5R, ±10% 0603
C10 1.0 µF Capacitor, X7R, ±10% 0603
L1 3.9 nH High frequency chip inductor ±5% 0402
L2 10 µH Chip inductor, IDC,min = 50 mA, ±20% 0603
L3 15 nH High frequency chip inductor ±10% 0402
U1 nRF52810-QCAA Multi-protocol Bluetooth® low energy, ANT and 2.4 GHz proprietary system on chip QFN-32
X1 32 MHz XTAL SMD 2016, 32 MHz, Cl = 8 pF, Total Tol: ±40 ppm XTAL_2016
X2 32.768 kHz XTAL SMD 3215, 32.768 kHz, Cl = 9 pF, Total Tol: ±20 ppm XTAL_3215

Schematic CAAA WLCSP with internal LDO regulator setup

In addition to the schematic, the bill of material (BOM) is also provided.

Figure 5. CAAA WLCSP with internal LDO regulator setup
Schematic: CAAA WLCSP with internal LDO regulator setup

Note: For PCB reference layouts, see Reference layout nRF52 Series.
Table 5. Bill of material for CAAA WLCSP with internal LDO regulator setup
Designator Value Description Footprint
C1, C2, C9, C10 12 pF Capacitor, NP0, ±2 % 0201
C3 1.2 pF Capacitor, NP0, ±5 % 0201
C4, C5 100 nF Capacitor, X5R, ±10 % 0201
C6 100 pF Capacitor, NP0, ±2 % 0201
C7 4.7 µF Capacitor, X5R, ±10 % 0603
C8 1.0 µF Capacitor, X5R, ±5 % 0402
L1 2.2 nH High frequency chip inductor ±5 % 0201
L2 3.3 nH High frequency chip inductor ±5 % 0201
U1 nRF52810-CAAA Multi-protocol Bluetooth® low energy, ANT and 2.4 GHz proprietary system on chip WLCSP-33
X1 32 MHz XTAL SMD 2016, 32 MHz, Cl = 8 pF, Total Tol: ±40 ppm XTAL_2016
X2 32.768 kHz XTAL SMD 2012, 32.768 kHz, Cl = 9 pF, Total Tol: ±50 ppm XTAL_2012

Schematic CAAA WLCSP with DC/DC regulator setup

In addition to the schematic, the bill of material (BOM) is also provided.

Figure 6. CAAA WLCSP with DC/DC regulator setup
Schematic: CAAA WLCSP with DC/DC regulator setup

Note: For PCB reference layouts, see Reference layout nRF52 Series.
Table 6. Bill of material for CAAA WLCSP with DC/DC regulator setup
Designator Value Description Footprint
C1, C2, C9, C10 12 pF Capacitor, NP0, ±2 % 0201
C3 1.2 pF Capacitor, NP0, ±5 % 0201
C4, C5 100 nF Capacitor, X5R, ±10 % 0201
C6 100 pF Capacitor, NP0, ±2 % 0201
C7 4.7 µF Capacitor, X5R, ±10 % 0603
C8 1.0 µF Capacitor, X5R, ±5 % 0402
L1 2.2 nH High frequency chip inductor ±5 % 0201
L2 3.3 nH High frequency chip inductor ±5 % 0201
L3 10 µH Chip inductor, IDC,min = 50 mA, ±20 % 0603
L4 15 nH High frequency chip inductor ±10 % 0402
U1 nRF52810-CAAA Multi-protocol Bluetooth® low energy, ANT and 2.4 GHz proprietary system on chip WLCSP-33
X1 32 MHz XTAL SMD 2016, 32 MHz, Cl = 8 pF, Total Tol: ±40 ppm XTAL_2016
X2 32.768 kHz XTAL SMD 2012, 32.768 kHz, Cl = 9 pF, Total Tol: ±50 ppm XTAL_2012

Schematic CAAA WLCSP with two layers

In addition to the schematic, the bill of material (BOM) is also provided.

Figure 7. CAAA WLCSP 2-layer setup
Schematic: CAAA WLCSP 2-layer setup

Note: For PCB reference layouts, see Reference layout nRF52 Series.
Table 7. Bill of material for CAAA WLCSP 2-layer setup
Designator Value Description Footprint
C1, C2 12 pF Capacitor, NP0, ±2 % 0201
C3 1.2 pF Capacitor, NP0, ±5 % 0201
C4, C5 100 nF Capacitor, X5R, ±10 % 0201
C6 100 pF Capacitor, NP0, ±2 % 0201
C7 4.7 µF Capacitor, X5R, ±10 % 0603
C8 1.0 µF Capacitor, X5R, ±5 % 0402
L1 2.2 nH High frequency chip inductor ±5 % 0201
L2 3.3 nH High frequency chip inductor ±5 % 0201
L3 10 µH Chip inductor, IDC,min = 50 mA, ±20 % 0603
L4 15 nH High frequency chip inductor ±10 % 0402
U1 nRF52810-CAAA Multi-protocol Bluetooth® low energy, ANT and 2.4 GHz proprietary system on chip WLCSP-33
X1 32 MHz XTAL SMD 2016, 32 MHz, Cl = 8 pF, Total Tol: ±40 ppm XTAL_2016

PCB guidelines

A well designed PCB is necessary to achieve good RF performance. Poor layout can lead to loss in performance or functionality.

A qualified RF layout for the IC and its surrounding components, including matching networks, can be downloaded from Reference layout nRF52 Series .

To ensure optimal performance it is essential that you follow the schematics and layout references closely. Especially in the case of the antenna matching circuitry (components between device pin ANT and the antenna), any changes to the layout can change the behavior, resulting in degradation of RF performance or a need to change component values. All reference circuits are designed for use with a 50 Ω single-ended antenna.

A PCB with a minimum of two layers, including a ground plane, is recommended for optimal performance. On PCBs with more than two layers, put a keep-out area on the inner layers directly below the antenna matching circuitry (components between device pin ANT and the antenna) to reduce the stray capacitances that influence RF performance.

A matching network is needed between the RF pin ANT and the antenna, to match the antenna impedance (normally 50 Ω) to the optimum RF load impedance for the chip. For optimum performance, the impedance for the matching network should be set as described in the recommended package reference circuitry in Reference circuitry above.

The DC supply voltage should be decoupled as close as possible to the VDD pins with high performance RF capacitors. See the schematics for recommended decoupling capacitor values. The supply voltage for the chip should be filtered and routed separately from the supply voltages of any digital circuitry.

Long power supply lines on the PCB should be avoided. All device grounds, VDD connections, and VDD bypass capacitors must be connected as close as possible to the IC. For a PCB with a topside RF ground plane, the VSS pins should be connected directly to the ground plane. For a PCB with a bottom ground plane, the best technique is to have via holes as close as possible to the VSS pads. A minimum of one via hole should be used for each VSS pin.

Fast switching digital signals should not be routed close to the crystal or the power supply lines. Capacitive loading of fast switching digital output lines should be minimized in order to avoid radio interference.

PCB layout example

The PCB layout shown as the example is a reference layout for the QFN48 package with internal LDO setup.

Important: Pay attention to how the capacitor C3 is grounded. It is not directly connected to the ground plane, but grounded via VSS pin 31. This is done to create additional filtering of harmonic components.

For all available reference layouts, see Reference layout nRF52 Series.

Figure 8. Top silk layer
Layout/image: Top silk layer

Figure 9. Top layer
Layout/image: Top layer

Figure 10. Bottom layer
Layout/image: Bottom layer

Important: No components in bottom layer.